1 /* 2 * arch/arm/mach-orion5x/pci.c 3 * 4 * PCI and PCIe functions for Marvell Orion System On Chip 5 * 6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/slab.h> 16 #include <linux/mbus.h> 17 #include <video/vga.h> 18 #include <asm/irq.h> 19 #include <asm/mach/pci.h> 20 #include <plat/pcie.h> 21 #include <plat/addr-map.h> 22 #include "common.h" 23 24 /***************************************************************************** 25 * Orion has one PCIe controller and one PCI controller. 26 * 27 * Note1: The local PCIe bus number is '0'. The local PCI bus number 28 * follows the scanned PCIe bridged busses, if any. 29 * 30 * Note2: It is possible for PCI/PCIe agents to access many subsystem's 31 * space, by configuring BARs and Address Decode Windows, e.g. flashes on 32 * device bus, Orion registers, etc. However this code only enable the 33 * access to DDR banks. 34 ****************************************************************************/ 35 36 37 /***************************************************************************** 38 * PCIe controller 39 ****************************************************************************/ 40 #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) 41 42 void __init orion5x_pcie_id(u32 *dev, u32 *rev) 43 { 44 *dev = orion_pcie_dev_id(PCIE_BASE); 45 *rev = orion_pcie_rev(PCIE_BASE); 46 } 47 48 static int pcie_valid_config(int bus, int dev) 49 { 50 /* 51 * Don't go out when trying to access -- 52 * 1. nonexisting device on local bus 53 * 2. where there's no device connected (no link) 54 */ 55 if (bus == 0 && dev == 0) 56 return 1; 57 58 if (!orion_pcie_link_up(PCIE_BASE)) 59 return 0; 60 61 if (bus == 0 && dev != 1) 62 return 0; 63 64 return 1; 65 } 66 67 68 /* 69 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register 70 * and then reading the PCIE_CONF_DATA register. Need to make sure these 71 * transactions are atomic. 72 */ 73 static DEFINE_SPINLOCK(orion5x_pcie_lock); 74 75 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 76 int size, u32 *val) 77 { 78 unsigned long flags; 79 int ret; 80 81 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 82 *val = 0xffffffff; 83 return PCIBIOS_DEVICE_NOT_FOUND; 84 } 85 86 spin_lock_irqsave(&orion5x_pcie_lock, flags); 87 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); 88 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 89 90 return ret; 91 } 92 93 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, 94 int where, int size, u32 *val) 95 { 96 int ret; 97 98 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 99 *val = 0xffffffff; 100 return PCIBIOS_DEVICE_NOT_FOUND; 101 } 102 103 /* 104 * We only support access to the non-extended configuration 105 * space when using the WA access method (or we would have to 106 * sacrifice 256M of CPU virtual address space.) 107 */ 108 if (where >= 0x100) { 109 *val = 0xffffffff; 110 return PCIBIOS_DEVICE_NOT_FOUND; 111 } 112 113 ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, 114 bus, devfn, where, size, val); 115 116 return ret; 117 } 118 119 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 120 int where, int size, u32 val) 121 { 122 unsigned long flags; 123 int ret; 124 125 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) 126 return PCIBIOS_DEVICE_NOT_FOUND; 127 128 spin_lock_irqsave(&orion5x_pcie_lock, flags); 129 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); 130 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 131 132 return ret; 133 } 134 135 static struct pci_ops pcie_ops = { 136 .read = pcie_rd_conf, 137 .write = pcie_wr_conf, 138 }; 139 140 141 static int __init pcie_setup(struct pci_sys_data *sys) 142 { 143 struct resource *res; 144 int dev; 145 146 /* 147 * Generic PCIe unit setup. 148 */ 149 orion_pcie_setup(PCIE_BASE); 150 151 /* 152 * Check whether to apply Orion-1/Orion-NAS PCIe config 153 * read transaction workaround. 154 */ 155 dev = orion_pcie_dev_id(PCIE_BASE); 156 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 157 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " 158 "read transaction workaround\n"); 159 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, 160 ORION5X_PCIE_WA_SIZE); 161 pcie_ops.read = pcie_rd_conf_wa; 162 } 163 164 /* 165 * Request resources. 166 */ 167 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 168 if (!res) 169 panic("pcie_setup unable to alloc resources"); 170 171 /* 172 * IORESOURCE_IO 173 */ 174 res[0].name = "PCIe I/O Space"; 175 res[0].flags = IORESOURCE_IO; 176 res[0].start = ORION5X_PCIE_IO_BUS_BASE; 177 res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; 178 if (request_resource(&ioport_resource, &res[0])) 179 panic("Request PCIe IO resource failed\n"); 180 sys->resource[0] = &res[0]; 181 182 /* 183 * IORESOURCE_MEM 184 */ 185 res[1].name = "PCIe Memory Space"; 186 res[1].flags = IORESOURCE_MEM; 187 res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; 188 res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; 189 if (request_resource(&iomem_resource, &res[1])) 190 panic("Request PCIe Memory resource failed\n"); 191 sys->resource[1] = &res[1]; 192 193 sys->resource[2] = NULL; 194 sys->io_offset = 0; 195 196 return 1; 197 } 198 199 /***************************************************************************** 200 * PCI controller 201 ****************************************************************************/ 202 #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) 203 #define PCI_MODE ORION5X_PCI_REG(0xd00) 204 #define PCI_CMD ORION5X_PCI_REG(0xc00) 205 #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) 206 #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) 207 #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) 208 209 /* 210 * PCI_MODE bits 211 */ 212 #define PCI_MODE_64BIT (1 << 2) 213 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) 214 215 /* 216 * PCI_CMD bits 217 */ 218 #define PCI_CMD_HOST_REORDER (1 << 29) 219 220 /* 221 * PCI_P2P_CONF bits 222 */ 223 #define PCI_P2P_BUS_OFFS 16 224 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) 225 #define PCI_P2P_DEV_OFFS 24 226 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) 227 228 /* 229 * PCI_CONF_ADDR bits 230 */ 231 #define PCI_CONF_REG(reg) ((reg) & 0xfc) 232 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) 233 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) 234 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) 235 #define PCI_CONF_ADDR_EN (1 << 31) 236 237 /* 238 * Internal configuration space 239 */ 240 #define PCI_CONF_FUNC_STAT_CMD 0 241 #define PCI_CONF_REG_STAT_CMD 4 242 #define PCIX_STAT 0x64 243 #define PCIX_STAT_BUS_OFFS 8 244 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) 245 246 /* 247 * PCI Address Decode Windows registers 248 */ 249 #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ 250 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ 251 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ 252 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) 253 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ 254 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ 255 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ 256 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) 257 #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) 258 #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) 259 260 /* 261 * PCI configuration helpers for BAR settings 262 */ 263 #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) 264 #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) 265 #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) 266 267 /* 268 * PCI config cycles are done by programming the PCI_CONF_ADDR register 269 * and then reading the PCI_CONF_DATA register. Need to make sure these 270 * transactions are atomic. 271 */ 272 static DEFINE_SPINLOCK(orion5x_pci_lock); 273 274 static int orion5x_pci_cardbus_mode; 275 276 static int orion5x_pci_local_bus_nr(void) 277 { 278 u32 conf = readl(PCI_P2P_CONF); 279 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); 280 } 281 282 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, 283 u32 where, u32 size, u32 *val) 284 { 285 unsigned long flags; 286 spin_lock_irqsave(&orion5x_pci_lock, flags); 287 288 writel(PCI_CONF_BUS(bus) | 289 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 290 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 291 292 *val = readl(PCI_CONF_DATA); 293 294 if (size == 1) 295 *val = (*val >> (8*(where & 0x3))) & 0xff; 296 else if (size == 2) 297 *val = (*val >> (8*(where & 0x3))) & 0xffff; 298 299 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 300 301 return PCIBIOS_SUCCESSFUL; 302 } 303 304 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, 305 u32 where, u32 size, u32 val) 306 { 307 unsigned long flags; 308 int ret = PCIBIOS_SUCCESSFUL; 309 310 spin_lock_irqsave(&orion5x_pci_lock, flags); 311 312 writel(PCI_CONF_BUS(bus) | 313 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 314 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 315 316 if (size == 4) { 317 __raw_writel(val, PCI_CONF_DATA); 318 } else if (size == 2) { 319 __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); 320 } else if (size == 1) { 321 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); 322 } else { 323 ret = PCIBIOS_BAD_REGISTER_NUMBER; 324 } 325 326 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 327 328 return ret; 329 } 330 331 static int orion5x_pci_valid_config(int bus, u32 devfn) 332 { 333 if (bus == orion5x_pci_local_bus_nr()) { 334 /* 335 * Don't go out for local device 336 */ 337 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) 338 return 0; 339 340 /* 341 * When the PCI signals are directly connected to a 342 * Cardbus slot, ignore all but device IDs 0 and 1. 343 */ 344 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) 345 return 0; 346 } 347 348 return 1; 349 } 350 351 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, 352 int where, int size, u32 *val) 353 { 354 if (!orion5x_pci_valid_config(bus->number, devfn)) { 355 *val = 0xffffffff; 356 return PCIBIOS_DEVICE_NOT_FOUND; 357 } 358 359 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), 360 PCI_FUNC(devfn), where, size, val); 361 } 362 363 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, 364 int where, int size, u32 val) 365 { 366 if (!orion5x_pci_valid_config(bus->number, devfn)) 367 return PCIBIOS_DEVICE_NOT_FOUND; 368 369 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), 370 PCI_FUNC(devfn), where, size, val); 371 } 372 373 static struct pci_ops pci_ops = { 374 .read = orion5x_pci_rd_conf, 375 .write = orion5x_pci_wr_conf, 376 }; 377 378 static void __init orion5x_pci_set_bus_nr(int nr) 379 { 380 u32 p2p = readl(PCI_P2P_CONF); 381 382 if (readl(PCI_MODE) & PCI_MODE_PCIX) { 383 /* 384 * PCI-X mode 385 */ 386 u32 pcix_status, bus, dev; 387 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; 388 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; 389 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); 390 pcix_status &= ~PCIX_STAT_BUS_MASK; 391 pcix_status |= (nr << PCIX_STAT_BUS_OFFS); 392 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); 393 } else { 394 /* 395 * PCI Conventional mode 396 */ 397 p2p &= ~PCI_P2P_BUS_MASK; 398 p2p |= (nr << PCI_P2P_BUS_OFFS); 399 writel(p2p, PCI_P2P_CONF); 400 } 401 } 402 403 static void __init orion5x_pci_master_slave_enable(void) 404 { 405 int bus_nr, func, reg; 406 u32 val; 407 408 bus_nr = orion5x_pci_local_bus_nr(); 409 func = PCI_CONF_FUNC_STAT_CMD; 410 reg = PCI_CONF_REG_STAT_CMD; 411 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); 412 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 413 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); 414 } 415 416 static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) 417 { 418 u32 win_enable; 419 int bus; 420 int i; 421 422 /* 423 * First, disable windows. 424 */ 425 win_enable = 0xffffffff; 426 writel(win_enable, PCI_BAR_ENABLE); 427 428 /* 429 * Setup windows for DDR banks. 430 */ 431 bus = orion5x_pci_local_bus_nr(); 432 433 for (i = 0; i < dram->num_cs; i++) { 434 struct mbus_dram_window *cs = dram->cs + i; 435 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); 436 u32 reg; 437 u32 val; 438 439 /* 440 * Write DRAM bank base address register. 441 */ 442 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); 443 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); 444 val = (cs->base & 0xfffff000) | (val & 0xfff); 445 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); 446 447 /* 448 * Write DRAM bank size register. 449 */ 450 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); 451 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); 452 writel((cs->size - 1) & 0xfffff000, 453 PCI_BAR_SIZE_DDR_CS(cs->cs_index)); 454 writel(cs->base & 0xfffff000, 455 PCI_BAR_REMAP_DDR_CS(cs->cs_index)); 456 457 /* 458 * Enable decode window for this chip select. 459 */ 460 win_enable &= ~(1 << cs->cs_index); 461 } 462 463 /* 464 * Re-enable decode windows. 465 */ 466 writel(win_enable, PCI_BAR_ENABLE); 467 468 /* 469 * Disable automatic update of address remapping when writing to BARs. 470 */ 471 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); 472 } 473 474 static int __init pci_setup(struct pci_sys_data *sys) 475 { 476 struct resource *res; 477 478 /* 479 * Point PCI unit MBUS decode windows to DRAM space. 480 */ 481 orion5x_setup_pci_wins(&orion_mbus_dram_info); 482 483 /* 484 * Master + Slave enable 485 */ 486 orion5x_pci_master_slave_enable(); 487 488 /* 489 * Force ordering 490 */ 491 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); 492 493 /* 494 * Request resources 495 */ 496 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 497 if (!res) 498 panic("pci_setup unable to alloc resources"); 499 500 /* 501 * IORESOURCE_IO 502 */ 503 res[0].name = "PCI I/O Space"; 504 res[0].flags = IORESOURCE_IO; 505 res[0].start = ORION5X_PCI_IO_BUS_BASE; 506 res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; 507 if (request_resource(&ioport_resource, &res[0])) 508 panic("Request PCI IO resource failed\n"); 509 sys->resource[0] = &res[0]; 510 511 /* 512 * IORESOURCE_MEM 513 */ 514 res[1].name = "PCI Memory Space"; 515 res[1].flags = IORESOURCE_MEM; 516 res[1].start = ORION5X_PCI_MEM_PHYS_BASE; 517 res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; 518 if (request_resource(&iomem_resource, &res[1])) 519 panic("Request PCI Memory resource failed\n"); 520 sys->resource[1] = &res[1]; 521 522 sys->resource[2] = NULL; 523 sys->io_offset = 0; 524 525 return 1; 526 } 527 528 529 /***************************************************************************** 530 * General PCIe + PCI 531 ****************************************************************************/ 532 static void __devinit rc_pci_fixup(struct pci_dev *dev) 533 { 534 /* 535 * Prevent enumeration of root complex. 536 */ 537 if (dev->bus->parent == NULL && dev->devfn == 0) { 538 int i; 539 540 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 541 dev->resource[i].start = 0; 542 dev->resource[i].end = 0; 543 dev->resource[i].flags = 0; 544 } 545 } 546 } 547 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); 548 549 static int orion5x_pci_disabled __initdata; 550 551 void __init orion5x_pci_disable(void) 552 { 553 orion5x_pci_disabled = 1; 554 } 555 556 void __init orion5x_pci_set_cardbus_mode(void) 557 { 558 orion5x_pci_cardbus_mode = 1; 559 } 560 561 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) 562 { 563 int ret = 0; 564 565 vga_base = ORION5X_PCIE_MEM_PHYS_BASE; 566 567 if (nr == 0) { 568 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); 569 ret = pcie_setup(sys); 570 } else if (nr == 1 && !orion5x_pci_disabled) { 571 orion5x_pci_set_bus_nr(sys->busnr); 572 ret = pci_setup(sys); 573 } 574 575 return ret; 576 } 577 578 struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) 579 { 580 struct pci_bus *bus; 581 582 if (nr == 0) { 583 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 584 } else if (nr == 1 && !orion5x_pci_disabled) { 585 bus = pci_scan_bus(sys->busnr, &pci_ops, sys); 586 } else { 587 bus = NULL; 588 BUG(); 589 } 590 591 return bus; 592 } 593 594 int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 595 { 596 int bus = dev->bus->number; 597 598 /* 599 * PCIe endpoint? 600 */ 601 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) 602 return IRQ_ORION5X_PCIE0_INT; 603 604 return -1; 605 } 606