1 /* 2 * arch/arm/mach-orion5x/pci.c 3 * 4 * PCI and PCIe functions for Marvell Orion System On Chip 5 * 6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/slab.h> 16 #include <linux/mbus.h> 17 #include <video/vga.h> 18 #include <asm/irq.h> 19 #include <asm/mach/pci.h> 20 #include <plat/pcie.h> 21 #include "common.h" 22 23 /***************************************************************************** 24 * Orion has one PCIe controller and one PCI controller. 25 * 26 * Note1: The local PCIe bus number is '0'. The local PCI bus number 27 * follows the scanned PCIe bridged busses, if any. 28 * 29 * Note2: It is possible for PCI/PCIe agents to access many subsystem's 30 * space, by configuring BARs and Address Decode Windows, e.g. flashes on 31 * device bus, Orion registers, etc. However this code only enable the 32 * access to DDR banks. 33 ****************************************************************************/ 34 35 36 /***************************************************************************** 37 * PCIe controller 38 ****************************************************************************/ 39 #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) 40 41 void __init orion5x_pcie_id(u32 *dev, u32 *rev) 42 { 43 *dev = orion_pcie_dev_id(PCIE_BASE); 44 *rev = orion_pcie_rev(PCIE_BASE); 45 } 46 47 static int pcie_valid_config(int bus, int dev) 48 { 49 /* 50 * Don't go out when trying to access -- 51 * 1. nonexisting device on local bus 52 * 2. where there's no device connected (no link) 53 */ 54 if (bus == 0 && dev == 0) 55 return 1; 56 57 if (!orion_pcie_link_up(PCIE_BASE)) 58 return 0; 59 60 if (bus == 0 && dev != 1) 61 return 0; 62 63 return 1; 64 } 65 66 67 /* 68 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register 69 * and then reading the PCIE_CONF_DATA register. Need to make sure these 70 * transactions are atomic. 71 */ 72 static DEFINE_SPINLOCK(orion5x_pcie_lock); 73 74 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 75 int size, u32 *val) 76 { 77 unsigned long flags; 78 int ret; 79 80 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 81 *val = 0xffffffff; 82 return PCIBIOS_DEVICE_NOT_FOUND; 83 } 84 85 spin_lock_irqsave(&orion5x_pcie_lock, flags); 86 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); 87 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 88 89 return ret; 90 } 91 92 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, 93 int where, int size, u32 *val) 94 { 95 int ret; 96 97 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { 98 *val = 0xffffffff; 99 return PCIBIOS_DEVICE_NOT_FOUND; 100 } 101 102 /* 103 * We only support access to the non-extended configuration 104 * space when using the WA access method (or we would have to 105 * sacrifice 256M of CPU virtual address space.) 106 */ 107 if (where >= 0x100) { 108 *val = 0xffffffff; 109 return PCIBIOS_DEVICE_NOT_FOUND; 110 } 111 112 ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, 113 bus, devfn, where, size, val); 114 115 return ret; 116 } 117 118 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 119 int where, int size, u32 val) 120 { 121 unsigned long flags; 122 int ret; 123 124 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) 125 return PCIBIOS_DEVICE_NOT_FOUND; 126 127 spin_lock_irqsave(&orion5x_pcie_lock, flags); 128 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); 129 spin_unlock_irqrestore(&orion5x_pcie_lock, flags); 130 131 return ret; 132 } 133 134 static struct pci_ops pcie_ops = { 135 .read = pcie_rd_conf, 136 .write = pcie_wr_conf, 137 }; 138 139 140 static int __init pcie_setup(struct pci_sys_data *sys) 141 { 142 struct resource *res; 143 int dev; 144 145 /* 146 * Generic PCIe unit setup. 147 */ 148 orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); 149 150 /* 151 * Check whether to apply Orion-1/Orion-NAS PCIe config 152 * read transaction workaround. 153 */ 154 dev = orion_pcie_dev_id(PCIE_BASE); 155 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 156 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " 157 "read transaction workaround\n"); 158 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, 159 ORION5X_PCIE_WA_SIZE); 160 pcie_ops.read = pcie_rd_conf_wa; 161 } 162 163 /* 164 * Request resources. 165 */ 166 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 167 if (!res) 168 panic("pcie_setup unable to alloc resources"); 169 170 /* 171 * IORESOURCE_IO 172 */ 173 res[0].name = "PCIe I/O Space"; 174 res[0].flags = IORESOURCE_IO; 175 res[0].start = ORION5X_PCIE_IO_BUS_BASE; 176 res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; 177 if (request_resource(&ioport_resource, &res[0])) 178 panic("Request PCIe IO resource failed\n"); 179 sys->resource[0] = &res[0]; 180 181 /* 182 * IORESOURCE_MEM 183 */ 184 res[1].name = "PCIe Memory Space"; 185 res[1].flags = IORESOURCE_MEM; 186 res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; 187 res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; 188 if (request_resource(&iomem_resource, &res[1])) 189 panic("Request PCIe Memory resource failed\n"); 190 sys->resource[1] = &res[1]; 191 192 sys->resource[2] = NULL; 193 sys->io_offset = 0; 194 195 return 1; 196 } 197 198 /***************************************************************************** 199 * PCI controller 200 ****************************************************************************/ 201 #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) 202 #define PCI_MODE ORION5X_PCI_REG(0xd00) 203 #define PCI_CMD ORION5X_PCI_REG(0xc00) 204 #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) 205 #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) 206 #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) 207 208 /* 209 * PCI_MODE bits 210 */ 211 #define PCI_MODE_64BIT (1 << 2) 212 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) 213 214 /* 215 * PCI_CMD bits 216 */ 217 #define PCI_CMD_HOST_REORDER (1 << 29) 218 219 /* 220 * PCI_P2P_CONF bits 221 */ 222 #define PCI_P2P_BUS_OFFS 16 223 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) 224 #define PCI_P2P_DEV_OFFS 24 225 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) 226 227 /* 228 * PCI_CONF_ADDR bits 229 */ 230 #define PCI_CONF_REG(reg) ((reg) & 0xfc) 231 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) 232 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) 233 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) 234 #define PCI_CONF_ADDR_EN (1 << 31) 235 236 /* 237 * Internal configuration space 238 */ 239 #define PCI_CONF_FUNC_STAT_CMD 0 240 #define PCI_CONF_REG_STAT_CMD 4 241 #define PCIX_STAT 0x64 242 #define PCIX_STAT_BUS_OFFS 8 243 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) 244 245 /* 246 * PCI Address Decode Windows registers 247 */ 248 #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ 249 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ 250 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ 251 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) 252 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ 253 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ 254 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ 255 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) 256 #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) 257 #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) 258 259 /* 260 * PCI configuration helpers for BAR settings 261 */ 262 #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) 263 #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) 264 #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) 265 266 /* 267 * PCI config cycles are done by programming the PCI_CONF_ADDR register 268 * and then reading the PCI_CONF_DATA register. Need to make sure these 269 * transactions are atomic. 270 */ 271 static DEFINE_SPINLOCK(orion5x_pci_lock); 272 273 static int orion5x_pci_cardbus_mode; 274 275 static int orion5x_pci_local_bus_nr(void) 276 { 277 u32 conf = readl(PCI_P2P_CONF); 278 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); 279 } 280 281 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, 282 u32 where, u32 size, u32 *val) 283 { 284 unsigned long flags; 285 spin_lock_irqsave(&orion5x_pci_lock, flags); 286 287 writel(PCI_CONF_BUS(bus) | 288 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 289 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 290 291 *val = readl(PCI_CONF_DATA); 292 293 if (size == 1) 294 *val = (*val >> (8*(where & 0x3))) & 0xff; 295 else if (size == 2) 296 *val = (*val >> (8*(where & 0x3))) & 0xffff; 297 298 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 299 300 return PCIBIOS_SUCCESSFUL; 301 } 302 303 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, 304 u32 where, u32 size, u32 val) 305 { 306 unsigned long flags; 307 int ret = PCIBIOS_SUCCESSFUL; 308 309 spin_lock_irqsave(&orion5x_pci_lock, flags); 310 311 writel(PCI_CONF_BUS(bus) | 312 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 313 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); 314 315 if (size == 4) { 316 __raw_writel(val, PCI_CONF_DATA); 317 } else if (size == 2) { 318 __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); 319 } else if (size == 1) { 320 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); 321 } else { 322 ret = PCIBIOS_BAD_REGISTER_NUMBER; 323 } 324 325 spin_unlock_irqrestore(&orion5x_pci_lock, flags); 326 327 return ret; 328 } 329 330 static int orion5x_pci_valid_config(int bus, u32 devfn) 331 { 332 if (bus == orion5x_pci_local_bus_nr()) { 333 /* 334 * Don't go out for local device 335 */ 336 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) 337 return 0; 338 339 /* 340 * When the PCI signals are directly connected to a 341 * Cardbus slot, ignore all but device IDs 0 and 1. 342 */ 343 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) 344 return 0; 345 } 346 347 return 1; 348 } 349 350 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, 351 int where, int size, u32 *val) 352 { 353 if (!orion5x_pci_valid_config(bus->number, devfn)) { 354 *val = 0xffffffff; 355 return PCIBIOS_DEVICE_NOT_FOUND; 356 } 357 358 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), 359 PCI_FUNC(devfn), where, size, val); 360 } 361 362 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, 363 int where, int size, u32 val) 364 { 365 if (!orion5x_pci_valid_config(bus->number, devfn)) 366 return PCIBIOS_DEVICE_NOT_FOUND; 367 368 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), 369 PCI_FUNC(devfn), where, size, val); 370 } 371 372 static struct pci_ops pci_ops = { 373 .read = orion5x_pci_rd_conf, 374 .write = orion5x_pci_wr_conf, 375 }; 376 377 static void __init orion5x_pci_set_bus_nr(int nr) 378 { 379 u32 p2p = readl(PCI_P2P_CONF); 380 381 if (readl(PCI_MODE) & PCI_MODE_PCIX) { 382 /* 383 * PCI-X mode 384 */ 385 u32 pcix_status, bus, dev; 386 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; 387 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; 388 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); 389 pcix_status &= ~PCIX_STAT_BUS_MASK; 390 pcix_status |= (nr << PCIX_STAT_BUS_OFFS); 391 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); 392 } else { 393 /* 394 * PCI Conventional mode 395 */ 396 p2p &= ~PCI_P2P_BUS_MASK; 397 p2p |= (nr << PCI_P2P_BUS_OFFS); 398 writel(p2p, PCI_P2P_CONF); 399 } 400 } 401 402 static void __init orion5x_pci_master_slave_enable(void) 403 { 404 int bus_nr, func, reg; 405 u32 val; 406 407 bus_nr = orion5x_pci_local_bus_nr(); 408 func = PCI_CONF_FUNC_STAT_CMD; 409 reg = PCI_CONF_REG_STAT_CMD; 410 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); 411 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 412 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); 413 } 414 415 static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) 416 { 417 u32 win_enable; 418 int bus; 419 int i; 420 421 /* 422 * First, disable windows. 423 */ 424 win_enable = 0xffffffff; 425 writel(win_enable, PCI_BAR_ENABLE); 426 427 /* 428 * Setup windows for DDR banks. 429 */ 430 bus = orion5x_pci_local_bus_nr(); 431 432 for (i = 0; i < dram->num_cs; i++) { 433 struct mbus_dram_window *cs = dram->cs + i; 434 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); 435 u32 reg; 436 u32 val; 437 438 /* 439 * Write DRAM bank base address register. 440 */ 441 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); 442 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); 443 val = (cs->base & 0xfffff000) | (val & 0xfff); 444 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); 445 446 /* 447 * Write DRAM bank size register. 448 */ 449 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); 450 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); 451 writel((cs->size - 1) & 0xfffff000, 452 PCI_BAR_SIZE_DDR_CS(cs->cs_index)); 453 writel(cs->base & 0xfffff000, 454 PCI_BAR_REMAP_DDR_CS(cs->cs_index)); 455 456 /* 457 * Enable decode window for this chip select. 458 */ 459 win_enable &= ~(1 << cs->cs_index); 460 } 461 462 /* 463 * Re-enable decode windows. 464 */ 465 writel(win_enable, PCI_BAR_ENABLE); 466 467 /* 468 * Disable automatic update of address remapping when writing to BARs. 469 */ 470 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); 471 } 472 473 static int __init pci_setup(struct pci_sys_data *sys) 474 { 475 struct resource *res; 476 477 /* 478 * Point PCI unit MBUS decode windows to DRAM space. 479 */ 480 orion5x_setup_pci_wins(&orion5x_mbus_dram_info); 481 482 /* 483 * Master + Slave enable 484 */ 485 orion5x_pci_master_slave_enable(); 486 487 /* 488 * Force ordering 489 */ 490 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); 491 492 /* 493 * Request resources 494 */ 495 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 496 if (!res) 497 panic("pci_setup unable to alloc resources"); 498 499 /* 500 * IORESOURCE_IO 501 */ 502 res[0].name = "PCI I/O Space"; 503 res[0].flags = IORESOURCE_IO; 504 res[0].start = ORION5X_PCI_IO_BUS_BASE; 505 res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; 506 if (request_resource(&ioport_resource, &res[0])) 507 panic("Request PCI IO resource failed\n"); 508 sys->resource[0] = &res[0]; 509 510 /* 511 * IORESOURCE_MEM 512 */ 513 res[1].name = "PCI Memory Space"; 514 res[1].flags = IORESOURCE_MEM; 515 res[1].start = ORION5X_PCI_MEM_PHYS_BASE; 516 res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; 517 if (request_resource(&iomem_resource, &res[1])) 518 panic("Request PCI Memory resource failed\n"); 519 sys->resource[1] = &res[1]; 520 521 sys->resource[2] = NULL; 522 sys->io_offset = 0; 523 524 return 1; 525 } 526 527 528 /***************************************************************************** 529 * General PCIe + PCI 530 ****************************************************************************/ 531 static void __devinit rc_pci_fixup(struct pci_dev *dev) 532 { 533 /* 534 * Prevent enumeration of root complex. 535 */ 536 if (dev->bus->parent == NULL && dev->devfn == 0) { 537 int i; 538 539 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 540 dev->resource[i].start = 0; 541 dev->resource[i].end = 0; 542 dev->resource[i].flags = 0; 543 } 544 } 545 } 546 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); 547 548 static int orion5x_pci_disabled __initdata; 549 550 void __init orion5x_pci_disable(void) 551 { 552 orion5x_pci_disabled = 1; 553 } 554 555 void __init orion5x_pci_set_cardbus_mode(void) 556 { 557 orion5x_pci_cardbus_mode = 1; 558 } 559 560 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) 561 { 562 int ret = 0; 563 564 vga_base = ORION5X_PCIE_MEM_PHYS_BASE; 565 566 if (nr == 0) { 567 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); 568 ret = pcie_setup(sys); 569 } else if (nr == 1 && !orion5x_pci_disabled) { 570 orion5x_pci_set_bus_nr(sys->busnr); 571 ret = pci_setup(sys); 572 } 573 574 return ret; 575 } 576 577 struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) 578 { 579 struct pci_bus *bus; 580 581 if (nr == 0) { 582 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 583 } else if (nr == 1 && !orion5x_pci_disabled) { 584 bus = pci_scan_bus(sys->busnr, &pci_ops, sys); 585 } else { 586 bus = NULL; 587 BUG(); 588 } 589 590 return bus; 591 } 592 593 int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 594 { 595 int bus = dev->bus->number; 596 597 /* 598 * PCIe endpoint? 599 */ 600 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) 601 return IRQ_ORION5X_PCIE0_INT; 602 603 return -1; 604 } 605