1 /* 2 * arch/arm/mach-orion5x/common.c 3 * 4 * Core functions for Marvell Orion 5x SoCs 5 * 6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/platform_device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/serial_8250.h> 19 #include <linux/mv643xx_i2c.h> 20 #include <linux/ata_platform.h> 21 #include <linux/delay.h> 22 #include <linux/clk-provider.h> 23 #include <linux/cpu.h> 24 #include <linux/platform_data/dsa.h> 25 #include <asm/page.h> 26 #include <asm/setup.h> 27 #include <asm/system_misc.h> 28 #include <asm/mach/arch.h> 29 #include <asm/mach/map.h> 30 #include <asm/mach/time.h> 31 #include <linux/platform_data/mtd-orion_nand.h> 32 #include <linux/platform_data/usb-ehci-orion.h> 33 #include <plat/time.h> 34 #include <plat/common.h> 35 36 #include "bridge-regs.h" 37 #include "common.h" 38 #include "orion5x.h" 39 40 /***************************************************************************** 41 * I/O Address Mapping 42 ****************************************************************************/ 43 static struct map_desc orion5x_io_desc[] __initdata = { 44 { 45 .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE, 46 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), 47 .length = ORION5X_REGS_SIZE, 48 .type = MT_DEVICE, 49 }, { 50 .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE, 51 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), 52 .length = ORION5X_PCIE_WA_SIZE, 53 .type = MT_DEVICE, 54 }, 55 }; 56 57 void __init orion5x_map_io(void) 58 { 59 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); 60 } 61 62 63 /***************************************************************************** 64 * CLK tree 65 ****************************************************************************/ 66 static struct clk *tclk; 67 68 void __init clk_init(void) 69 { 70 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk); 71 72 orion_clkdev_init(tclk); 73 } 74 75 /***************************************************************************** 76 * EHCI0 77 ****************************************************************************/ 78 void __init orion5x_ehci0_init(void) 79 { 80 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, 81 EHCI_PHY_ORION); 82 } 83 84 85 /***************************************************************************** 86 * EHCI1 87 ****************************************************************************/ 88 void __init orion5x_ehci1_init(void) 89 { 90 orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); 91 } 92 93 94 /***************************************************************************** 95 * GE00 96 ****************************************************************************/ 97 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) 98 { 99 orion_ge00_init(eth_data, 100 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, 101 IRQ_ORION5X_ETH_ERR, 102 MV643XX_TX_CSUM_DEFAULT_LIMIT); 103 } 104 105 106 /***************************************************************************** 107 * Ethernet switch 108 ****************************************************************************/ 109 void __init orion5x_eth_switch_init(struct dsa_chip_data *d) 110 { 111 orion_ge00_switch_init(d); 112 } 113 114 115 /***************************************************************************** 116 * I2C 117 ****************************************************************************/ 118 void __init orion5x_i2c_init(void) 119 { 120 orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); 121 122 } 123 124 125 /***************************************************************************** 126 * SATA 127 ****************************************************************************/ 128 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) 129 { 130 orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); 131 } 132 133 134 /***************************************************************************** 135 * SPI 136 ****************************************************************************/ 137 void __init orion5x_spi_init(void) 138 { 139 orion_spi_init(SPI_PHYS_BASE); 140 } 141 142 143 /***************************************************************************** 144 * UART0 145 ****************************************************************************/ 146 void __init orion5x_uart0_init(void) 147 { 148 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, 149 IRQ_ORION5X_UART0, tclk); 150 } 151 152 /***************************************************************************** 153 * UART1 154 ****************************************************************************/ 155 void __init orion5x_uart1_init(void) 156 { 157 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, 158 IRQ_ORION5X_UART1, tclk); 159 } 160 161 /***************************************************************************** 162 * XOR engine 163 ****************************************************************************/ 164 void __init orion5x_xor_init(void) 165 { 166 orion_xor0_init(ORION5X_XOR_PHYS_BASE, 167 ORION5X_XOR_PHYS_BASE + 0x200, 168 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); 169 } 170 171 /***************************************************************************** 172 * Cryptographic Engines and Security Accelerator (CESA) 173 ****************************************************************************/ 174 static void __init orion5x_crypto_init(void) 175 { 176 mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET, 177 ORION_MBUS_SRAM_ATTR, 178 ORION5X_SRAM_PHYS_BASE, 179 ORION5X_SRAM_SIZE); 180 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, 181 SZ_8K, IRQ_ORION5X_CESA); 182 } 183 184 /***************************************************************************** 185 * Watchdog 186 ****************************************************************************/ 187 static struct resource orion_wdt_resource[] = { 188 DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), 189 DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), 190 }; 191 192 static struct platform_device orion_wdt_device = { 193 .name = "orion_wdt", 194 .id = -1, 195 .num_resources = ARRAY_SIZE(orion_wdt_resource), 196 .resource = orion_wdt_resource, 197 }; 198 199 static void __init orion5x_wdt_init(void) 200 { 201 platform_device_register(&orion_wdt_device); 202 } 203 204 205 /***************************************************************************** 206 * Time handling 207 ****************************************************************************/ 208 void __init orion5x_init_early(void) 209 { 210 u32 rev, dev; 211 const char *mbus_soc_name; 212 213 orion_time_set_base(TIMER_VIRT_BASE); 214 215 /* Initialize the MBUS driver */ 216 orion5x_pcie_id(&dev, &rev); 217 if (dev == MV88F5281_DEV_ID) 218 mbus_soc_name = "marvell,orion5x-88f5281-mbus"; 219 else if (dev == MV88F5182_DEV_ID) 220 mbus_soc_name = "marvell,orion5x-88f5182-mbus"; 221 else if (dev == MV88F5181_DEV_ID) 222 mbus_soc_name = "marvell,orion5x-88f5181-mbus"; 223 else if (dev == MV88F6183_DEV_ID) 224 mbus_soc_name = "marvell,orion5x-88f6183-mbus"; 225 else 226 mbus_soc_name = NULL; 227 mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE, 228 ORION5X_BRIDGE_WINS_SZ, 229 ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ); 230 } 231 232 void orion5x_setup_wins(void) 233 { 234 /* 235 * The PCIe windows will no longer be statically allocated 236 * here once Orion5x is migrated to the pci-mvebu driver. 237 */ 238 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, 239 ORION_MBUS_PCIE_IO_ATTR, 240 ORION5X_PCIE_IO_PHYS_BASE, 241 ORION5X_PCIE_IO_SIZE, 242 ORION5X_PCIE_IO_BUS_BASE); 243 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, 244 ORION_MBUS_PCIE_MEM_ATTR, 245 ORION5X_PCIE_MEM_PHYS_BASE, 246 ORION5X_PCIE_MEM_SIZE); 247 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET, 248 ORION_MBUS_PCI_IO_ATTR, 249 ORION5X_PCI_IO_PHYS_BASE, 250 ORION5X_PCI_IO_SIZE, 251 ORION5X_PCI_IO_BUS_BASE); 252 mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET, 253 ORION_MBUS_PCI_MEM_ATTR, 254 ORION5X_PCI_MEM_PHYS_BASE, 255 ORION5X_PCI_MEM_SIZE); 256 } 257 258 int orion5x_tclk; 259 260 static int __init orion5x_find_tclk(void) 261 { 262 u32 dev, rev; 263 264 orion5x_pcie_id(&dev, &rev); 265 if (dev == MV88F6183_DEV_ID && 266 (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) 267 return 133333333; 268 269 return 166666667; 270 } 271 272 void __init orion5x_timer_init(void) 273 { 274 orion5x_tclk = orion5x_find_tclk(); 275 276 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 277 IRQ_ORION5X_BRIDGE, orion5x_tclk); 278 } 279 280 281 /***************************************************************************** 282 * General 283 ****************************************************************************/ 284 /* 285 * Identify device ID and rev from PCIe configuration header space '0'. 286 */ 287 void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) 288 { 289 orion5x_pcie_id(dev, rev); 290 291 if (*dev == MV88F5281_DEV_ID) { 292 if (*rev == MV88F5281_REV_D2) { 293 *dev_name = "MV88F5281-D2"; 294 } else if (*rev == MV88F5281_REV_D1) { 295 *dev_name = "MV88F5281-D1"; 296 } else if (*rev == MV88F5281_REV_D0) { 297 *dev_name = "MV88F5281-D0"; 298 } else { 299 *dev_name = "MV88F5281-Rev-Unsupported"; 300 } 301 } else if (*dev == MV88F5182_DEV_ID) { 302 if (*rev == MV88F5182_REV_A2) { 303 *dev_name = "MV88F5182-A2"; 304 } else { 305 *dev_name = "MV88F5182-Rev-Unsupported"; 306 } 307 } else if (*dev == MV88F5181_DEV_ID) { 308 if (*rev == MV88F5181_REV_B1) { 309 *dev_name = "MV88F5181-Rev-B1"; 310 } else if (*rev == MV88F5181L_REV_A1) { 311 *dev_name = "MV88F5181L-Rev-A1"; 312 } else { 313 *dev_name = "MV88F5181(L)-Rev-Unsupported"; 314 } 315 } else if (*dev == MV88F6183_DEV_ID) { 316 if (*rev == MV88F6183_REV_B0) { 317 *dev_name = "MV88F6183-Rev-B0"; 318 } else { 319 *dev_name = "MV88F6183-Rev-Unsupported"; 320 } 321 } else { 322 *dev_name = "Device-Unknown"; 323 } 324 } 325 326 void __init orion5x_init(void) 327 { 328 char *dev_name; 329 u32 dev, rev; 330 331 orion5x_id(&dev, &rev, &dev_name); 332 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); 333 334 /* 335 * Setup Orion address map 336 */ 337 orion5x_setup_wins(); 338 339 /* Setup root of clk tree */ 340 clk_init(); 341 342 /* 343 * Don't issue "Wait for Interrupt" instruction if we are 344 * running on D0 5281 silicon. 345 */ 346 if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { 347 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); 348 cpu_idle_poll_ctrl(true); 349 } 350 351 /* 352 * The 5082/5181l/5182/6082/6082l/6183 have crypto 353 * while 5180n/5181/5281 don't have crypto. 354 */ 355 if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || 356 dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) 357 orion5x_crypto_init(); 358 359 /* 360 * Register watchdog driver 361 */ 362 orion5x_wdt_init(); 363 } 364 365 void orion5x_restart(enum reboot_mode mode, const char *cmd) 366 { 367 /* 368 * Enable and issue soft reset 369 */ 370 orion5x_setbits(RSTOUTn_MASK, (1 << 2)); 371 orion5x_setbits(CPU_SOFT_RESET, 1); 372 mdelay(200); 373 orion5x_clrbits(CPU_SOFT_RESET, 1); 374 } 375 376 /* 377 * Many orion-based systems have buggy bootloader implementations. 378 * This is a common fixup for bogus memory tags. 379 */ 380 void __init tag_fixup_mem32(struct tag *t, char **from) 381 { 382 for (; t->hdr.size; t = tag_next(t)) 383 if (t->hdr.tag == ATAG_MEM && 384 (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || 385 t->u.mem.start & ~PAGE_MASK)) { 386 printk(KERN_WARNING 387 "Clearing invalid memory bank %dKB@0x%08x\n", 388 t->u.mem.size / 1024, t->u.mem.start); 389 t->hdr.tag = 0; 390 } 391 } 392