1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * arch/arm/mach-orion5x/common.c 4 * 5 * Core functions for Marvell Orion 5x SoCs 6 * 7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/platform_device.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/serial_8250.h> 16 #include <linux/mv643xx_i2c.h> 17 #include <linux/ata_platform.h> 18 #include <linux/delay.h> 19 #include <linux/clk-provider.h> 20 #include <linux/cpu.h> 21 #include <linux/platform_data/dsa.h> 22 #include <asm/page.h> 23 #include <asm/setup.h> 24 #include <asm/system_misc.h> 25 #include <asm/mach/arch.h> 26 #include <asm/mach/map.h> 27 #include <asm/mach/time.h> 28 #include <linux/platform_data/mtd-orion_nand.h> 29 #include <linux/platform_data/usb-ehci-orion.h> 30 #include <plat/time.h> 31 #include <plat/common.h> 32 33 #include "bridge-regs.h" 34 #include "common.h" 35 #include "orion5x.h" 36 37 /***************************************************************************** 38 * I/O Address Mapping 39 ****************************************************************************/ 40 static struct map_desc orion5x_io_desc[] __initdata = { 41 { 42 .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE, 43 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), 44 .length = ORION5X_REGS_SIZE, 45 .type = MT_DEVICE, 46 }, { 47 .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE, 48 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), 49 .length = ORION5X_PCIE_WA_SIZE, 50 .type = MT_DEVICE, 51 }, 52 }; 53 54 void __init orion5x_map_io(void) 55 { 56 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); 57 } 58 59 60 /***************************************************************************** 61 * CLK tree 62 ****************************************************************************/ 63 static struct clk *tclk; 64 65 void __init clk_init(void) 66 { 67 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk); 68 69 orion_clkdev_init(tclk); 70 } 71 72 /***************************************************************************** 73 * EHCI0 74 ****************************************************************************/ 75 void __init orion5x_ehci0_init(void) 76 { 77 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, 78 EHCI_PHY_ORION); 79 } 80 81 82 /***************************************************************************** 83 * EHCI1 84 ****************************************************************************/ 85 void __init orion5x_ehci1_init(void) 86 { 87 orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); 88 } 89 90 91 /***************************************************************************** 92 * GE00 93 ****************************************************************************/ 94 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) 95 { 96 orion_ge00_init(eth_data, 97 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, 98 IRQ_ORION5X_ETH_ERR, 99 MV643XX_TX_CSUM_DEFAULT_LIMIT); 100 } 101 102 103 /***************************************************************************** 104 * Ethernet switch 105 ****************************************************************************/ 106 void __init orion5x_eth_switch_init(struct dsa_chip_data *d) 107 { 108 orion_ge00_switch_init(d); 109 } 110 111 112 /***************************************************************************** 113 * I2C 114 ****************************************************************************/ 115 void __init orion5x_i2c_init(void) 116 { 117 orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); 118 119 } 120 121 122 /***************************************************************************** 123 * SATA 124 ****************************************************************************/ 125 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) 126 { 127 orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); 128 } 129 130 131 /***************************************************************************** 132 * SPI 133 ****************************************************************************/ 134 void __init orion5x_spi_init(void) 135 { 136 orion_spi_init(SPI_PHYS_BASE); 137 } 138 139 140 /***************************************************************************** 141 * UART0 142 ****************************************************************************/ 143 void __init orion5x_uart0_init(void) 144 { 145 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, 146 IRQ_ORION5X_UART0, tclk); 147 } 148 149 /***************************************************************************** 150 * UART1 151 ****************************************************************************/ 152 void __init orion5x_uart1_init(void) 153 { 154 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, 155 IRQ_ORION5X_UART1, tclk); 156 } 157 158 /***************************************************************************** 159 * XOR engine 160 ****************************************************************************/ 161 void __init orion5x_xor_init(void) 162 { 163 orion_xor0_init(ORION5X_XOR_PHYS_BASE, 164 ORION5X_XOR_PHYS_BASE + 0x200, 165 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); 166 } 167 168 /***************************************************************************** 169 * Cryptographic Engines and Security Accelerator (CESA) 170 ****************************************************************************/ 171 static void __init orion5x_crypto_init(void) 172 { 173 mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET, 174 ORION_MBUS_SRAM_ATTR, 175 ORION5X_SRAM_PHYS_BASE, 176 ORION5X_SRAM_SIZE); 177 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, 178 SZ_8K, IRQ_ORION5X_CESA); 179 } 180 181 /***************************************************************************** 182 * Watchdog 183 ****************************************************************************/ 184 static struct resource orion_wdt_resource[] = { 185 DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), 186 DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), 187 }; 188 189 static struct platform_device orion_wdt_device = { 190 .name = "orion_wdt", 191 .id = -1, 192 .num_resources = ARRAY_SIZE(orion_wdt_resource), 193 .resource = orion_wdt_resource, 194 }; 195 196 static void __init orion5x_wdt_init(void) 197 { 198 platform_device_register(&orion_wdt_device); 199 } 200 201 202 /***************************************************************************** 203 * Time handling 204 ****************************************************************************/ 205 void __init orion5x_init_early(void) 206 { 207 u32 rev, dev; 208 const char *mbus_soc_name; 209 210 orion_time_set_base(TIMER_VIRT_BASE); 211 212 /* Initialize the MBUS driver */ 213 orion5x_pcie_id(&dev, &rev); 214 if (dev == MV88F5281_DEV_ID) 215 mbus_soc_name = "marvell,orion5x-88f5281-mbus"; 216 else if (dev == MV88F5182_DEV_ID) 217 mbus_soc_name = "marvell,orion5x-88f5182-mbus"; 218 else if (dev == MV88F5181_DEV_ID) 219 mbus_soc_name = "marvell,orion5x-88f5181-mbus"; 220 else if (dev == MV88F6183_DEV_ID) 221 mbus_soc_name = "marvell,orion5x-88f6183-mbus"; 222 else 223 mbus_soc_name = NULL; 224 mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE, 225 ORION5X_BRIDGE_WINS_SZ, 226 ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ); 227 } 228 229 void orion5x_setup_wins(void) 230 { 231 /* 232 * The PCIe windows will no longer be statically allocated 233 * here once Orion5x is migrated to the pci-mvebu driver. 234 */ 235 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, 236 ORION_MBUS_PCIE_IO_ATTR, 237 ORION5X_PCIE_IO_PHYS_BASE, 238 ORION5X_PCIE_IO_SIZE, 239 ORION5X_PCIE_IO_BUS_BASE); 240 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, 241 ORION_MBUS_PCIE_MEM_ATTR, 242 ORION5X_PCIE_MEM_PHYS_BASE, 243 ORION5X_PCIE_MEM_SIZE); 244 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET, 245 ORION_MBUS_PCI_IO_ATTR, 246 ORION5X_PCI_IO_PHYS_BASE, 247 ORION5X_PCI_IO_SIZE, 248 ORION5X_PCI_IO_BUS_BASE); 249 mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET, 250 ORION_MBUS_PCI_MEM_ATTR, 251 ORION5X_PCI_MEM_PHYS_BASE, 252 ORION5X_PCI_MEM_SIZE); 253 } 254 255 int orion5x_tclk; 256 257 static int __init orion5x_find_tclk(void) 258 { 259 u32 dev, rev; 260 261 orion5x_pcie_id(&dev, &rev); 262 if (dev == MV88F6183_DEV_ID && 263 (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) 264 return 133333333; 265 266 return 166666667; 267 } 268 269 void __init orion5x_timer_init(void) 270 { 271 orion5x_tclk = orion5x_find_tclk(); 272 273 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 274 IRQ_ORION5X_BRIDGE, orion5x_tclk); 275 } 276 277 278 /***************************************************************************** 279 * General 280 ****************************************************************************/ 281 /* 282 * Identify device ID and rev from PCIe configuration header space '0'. 283 */ 284 void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) 285 { 286 orion5x_pcie_id(dev, rev); 287 288 if (*dev == MV88F5281_DEV_ID) { 289 if (*rev == MV88F5281_REV_D2) { 290 *dev_name = "MV88F5281-D2"; 291 } else if (*rev == MV88F5281_REV_D1) { 292 *dev_name = "MV88F5281-D1"; 293 } else if (*rev == MV88F5281_REV_D0) { 294 *dev_name = "MV88F5281-D0"; 295 } else { 296 *dev_name = "MV88F5281-Rev-Unsupported"; 297 } 298 } else if (*dev == MV88F5182_DEV_ID) { 299 if (*rev == MV88F5182_REV_A2) { 300 *dev_name = "MV88F5182-A2"; 301 } else { 302 *dev_name = "MV88F5182-Rev-Unsupported"; 303 } 304 } else if (*dev == MV88F5181_DEV_ID) { 305 if (*rev == MV88F5181_REV_B1) { 306 *dev_name = "MV88F5181-Rev-B1"; 307 } else if (*rev == MV88F5181L_REV_A1) { 308 *dev_name = "MV88F5181L-Rev-A1"; 309 } else { 310 *dev_name = "MV88F5181(L)-Rev-Unsupported"; 311 } 312 } else if (*dev == MV88F6183_DEV_ID) { 313 if (*rev == MV88F6183_REV_B0) { 314 *dev_name = "MV88F6183-Rev-B0"; 315 } else { 316 *dev_name = "MV88F6183-Rev-Unsupported"; 317 } 318 } else { 319 *dev_name = "Device-Unknown"; 320 } 321 } 322 323 void __init orion5x_init(void) 324 { 325 char *dev_name; 326 u32 dev, rev; 327 328 orion5x_id(&dev, &rev, &dev_name); 329 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); 330 331 /* 332 * Setup Orion address map 333 */ 334 orion5x_setup_wins(); 335 336 /* Setup root of clk tree */ 337 clk_init(); 338 339 /* 340 * Don't issue "Wait for Interrupt" instruction if we are 341 * running on D0 5281 silicon. 342 */ 343 if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { 344 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); 345 cpu_idle_poll_ctrl(true); 346 } 347 348 /* 349 * The 5082/5181l/5182/6082/6082l/6183 have crypto 350 * while 5180n/5181/5281 don't have crypto. 351 */ 352 if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || 353 dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) 354 orion5x_crypto_init(); 355 356 /* 357 * Register watchdog driver 358 */ 359 orion5x_wdt_init(); 360 } 361 362 void orion5x_restart(enum reboot_mode mode, const char *cmd) 363 { 364 /* 365 * Enable and issue soft reset 366 */ 367 orion5x_setbits(RSTOUTn_MASK, (1 << 2)); 368 orion5x_setbits(CPU_SOFT_RESET, 1); 369 mdelay(200); 370 orion5x_clrbits(CPU_SOFT_RESET, 1); 371 } 372 373 /* 374 * Many orion-based systems have buggy bootloader implementations. 375 * This is a common fixup for bogus memory tags. 376 */ 377 void __init tag_fixup_mem32(struct tag *t, char **from) 378 { 379 for (; t->hdr.size; t = tag_next(t)) 380 if (t->hdr.tag == ATAG_MEM && 381 (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || 382 t->u.mem.start & ~PAGE_MASK)) { 383 printk(KERN_WARNING 384 "Clearing invalid memory bank %dKB@0x%08x\n", 385 t->u.mem.size / 1024, t->u.mem.start); 386 t->hdr.tag = 0; 387 } 388 } 389