1 /* 2 * arch/arm/mach-orion5x/common.c 3 * 4 * Core functions for Marvell Orion 5x SoCs 5 * 6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/platform_device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/serial_8250.h> 18 #include <linux/mv643xx_i2c.h> 19 #include <linux/ata_platform.h> 20 #include <linux/delay.h> 21 #include <net/dsa.h> 22 #include <asm/page.h> 23 #include <asm/setup.h> 24 #include <asm/system_misc.h> 25 #include <asm/timex.h> 26 #include <asm/mach/arch.h> 27 #include <asm/mach/map.h> 28 #include <asm/mach/time.h> 29 #include <mach/bridge-regs.h> 30 #include <mach/hardware.h> 31 #include <mach/orion5x.h> 32 #include <plat/orion_nand.h> 33 #include <plat/ehci-orion.h> 34 #include <plat/time.h> 35 #include <plat/common.h> 36 #include <plat/addr-map.h> 37 #include "common.h" 38 39 /***************************************************************************** 40 * I/O Address Mapping 41 ****************************************************************************/ 42 static struct map_desc orion5x_io_desc[] __initdata = { 43 { 44 .virtual = ORION5X_REGS_VIRT_BASE, 45 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), 46 .length = ORION5X_REGS_SIZE, 47 .type = MT_DEVICE, 48 }, { 49 .virtual = ORION5X_PCIE_IO_VIRT_BASE, 50 .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), 51 .length = ORION5X_PCIE_IO_SIZE, 52 .type = MT_DEVICE, 53 }, { 54 .virtual = ORION5X_PCI_IO_VIRT_BASE, 55 .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), 56 .length = ORION5X_PCI_IO_SIZE, 57 .type = MT_DEVICE, 58 }, { 59 .virtual = ORION5X_PCIE_WA_VIRT_BASE, 60 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), 61 .length = ORION5X_PCIE_WA_SIZE, 62 .type = MT_DEVICE, 63 }, 64 }; 65 66 void __init orion5x_map_io(void) 67 { 68 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); 69 } 70 71 72 /***************************************************************************** 73 * EHCI0 74 ****************************************************************************/ 75 void __init orion5x_ehci0_init(void) 76 { 77 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, 78 EHCI_PHY_ORION); 79 } 80 81 82 /***************************************************************************** 83 * EHCI1 84 ****************************************************************************/ 85 void __init orion5x_ehci1_init(void) 86 { 87 orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); 88 } 89 90 91 /***************************************************************************** 92 * GE00 93 ****************************************************************************/ 94 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) 95 { 96 orion_ge00_init(eth_data, 97 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, 98 IRQ_ORION5X_ETH_ERR, orion5x_tclk); 99 } 100 101 102 /***************************************************************************** 103 * Ethernet switch 104 ****************************************************************************/ 105 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) 106 { 107 orion_ge00_switch_init(d, irq); 108 } 109 110 111 /***************************************************************************** 112 * I2C 113 ****************************************************************************/ 114 void __init orion5x_i2c_init(void) 115 { 116 orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); 117 118 } 119 120 121 /***************************************************************************** 122 * SATA 123 ****************************************************************************/ 124 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) 125 { 126 orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); 127 } 128 129 130 /***************************************************************************** 131 * SPI 132 ****************************************************************************/ 133 void __init orion5x_spi_init() 134 { 135 orion_spi_init(SPI_PHYS_BASE, orion5x_tclk); 136 } 137 138 139 /***************************************************************************** 140 * UART0 141 ****************************************************************************/ 142 void __init orion5x_uart0_init(void) 143 { 144 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, 145 IRQ_ORION5X_UART0, orion5x_tclk); 146 } 147 148 /***************************************************************************** 149 * UART1 150 ****************************************************************************/ 151 void __init orion5x_uart1_init(void) 152 { 153 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, 154 IRQ_ORION5X_UART1, orion5x_tclk); 155 } 156 157 /***************************************************************************** 158 * XOR engine 159 ****************************************************************************/ 160 void __init orion5x_xor_init(void) 161 { 162 orion_xor0_init(ORION5X_XOR_PHYS_BASE, 163 ORION5X_XOR_PHYS_BASE + 0x200, 164 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); 165 } 166 167 /***************************************************************************** 168 * Cryptographic Engines and Security Accelerator (CESA) 169 ****************************************************************************/ 170 static void __init orion5x_crypto_init(void) 171 { 172 orion5x_setup_sram_win(); 173 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, 174 SZ_8K, IRQ_ORION5X_CESA); 175 } 176 177 /***************************************************************************** 178 * Watchdog 179 ****************************************************************************/ 180 void __init orion5x_wdt_init(void) 181 { 182 orion_wdt_init(orion5x_tclk); 183 } 184 185 186 /***************************************************************************** 187 * Time handling 188 ****************************************************************************/ 189 void __init orion5x_init_early(void) 190 { 191 orion_time_set_base(TIMER_VIRT_BASE); 192 } 193 194 int orion5x_tclk; 195 196 int __init orion5x_find_tclk(void) 197 { 198 u32 dev, rev; 199 200 orion5x_pcie_id(&dev, &rev); 201 if (dev == MV88F6183_DEV_ID && 202 (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) 203 return 133333333; 204 205 return 166666667; 206 } 207 208 static void orion5x_timer_init(void) 209 { 210 orion5x_tclk = orion5x_find_tclk(); 211 212 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 213 IRQ_ORION5X_BRIDGE, orion5x_tclk); 214 } 215 216 struct sys_timer orion5x_timer = { 217 .init = orion5x_timer_init, 218 }; 219 220 221 /***************************************************************************** 222 * General 223 ****************************************************************************/ 224 /* 225 * Identify device ID and rev from PCIe configuration header space '0'. 226 */ 227 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) 228 { 229 orion5x_pcie_id(dev, rev); 230 231 if (*dev == MV88F5281_DEV_ID) { 232 if (*rev == MV88F5281_REV_D2) { 233 *dev_name = "MV88F5281-D2"; 234 } else if (*rev == MV88F5281_REV_D1) { 235 *dev_name = "MV88F5281-D1"; 236 } else if (*rev == MV88F5281_REV_D0) { 237 *dev_name = "MV88F5281-D0"; 238 } else { 239 *dev_name = "MV88F5281-Rev-Unsupported"; 240 } 241 } else if (*dev == MV88F5182_DEV_ID) { 242 if (*rev == MV88F5182_REV_A2) { 243 *dev_name = "MV88F5182-A2"; 244 } else { 245 *dev_name = "MV88F5182-Rev-Unsupported"; 246 } 247 } else if (*dev == MV88F5181_DEV_ID) { 248 if (*rev == MV88F5181_REV_B1) { 249 *dev_name = "MV88F5181-Rev-B1"; 250 } else if (*rev == MV88F5181L_REV_A1) { 251 *dev_name = "MV88F5181L-Rev-A1"; 252 } else { 253 *dev_name = "MV88F5181(L)-Rev-Unsupported"; 254 } 255 } else if (*dev == MV88F6183_DEV_ID) { 256 if (*rev == MV88F6183_REV_B0) { 257 *dev_name = "MV88F6183-Rev-B0"; 258 } else { 259 *dev_name = "MV88F6183-Rev-Unsupported"; 260 } 261 } else { 262 *dev_name = "Device-Unknown"; 263 } 264 } 265 266 void __init orion5x_init(void) 267 { 268 char *dev_name; 269 u32 dev, rev; 270 271 orion5x_id(&dev, &rev, &dev_name); 272 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); 273 274 /* 275 * Setup Orion address map 276 */ 277 orion5x_setup_cpu_mbus_bridge(); 278 279 /* 280 * Don't issue "Wait for Interrupt" instruction if we are 281 * running on D0 5281 silicon. 282 */ 283 if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { 284 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n"); 285 disable_hlt(); 286 } 287 288 /* 289 * The 5082/5181l/5182/6082/6082l/6183 have crypto 290 * while 5180n/5181/5281 don't have crypto. 291 */ 292 if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || 293 dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) 294 orion5x_crypto_init(); 295 296 /* 297 * Register watchdog driver 298 */ 299 orion5x_wdt_init(); 300 } 301 302 void orion5x_restart(char mode, const char *cmd) 303 { 304 /* 305 * Enable and issue soft reset 306 */ 307 orion5x_setbits(RSTOUTn_MASK, (1 << 2)); 308 orion5x_setbits(CPU_SOFT_RESET, 1); 309 mdelay(200); 310 orion5x_clrbits(CPU_SOFT_RESET, 1); 311 } 312 313 /* 314 * Many orion-based systems have buggy bootloader implementations. 315 * This is a common fixup for bogus memory tags. 316 */ 317 void __init tag_fixup_mem32(struct tag *t, char **from, 318 struct meminfo *meminfo) 319 { 320 for (; t->hdr.size; t = tag_next(t)) 321 if (t->hdr.tag == ATAG_MEM && 322 (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || 323 t->u.mem.start & ~PAGE_MASK)) { 324 printk(KERN_WARNING 325 "Clearing invalid memory bank %dKB@0x%08x\n", 326 t->u.mem.size / 1024, t->u.mem.start); 327 t->hdr.tag = 0; 328 } 329 } 330