1c22c2c60SArnd Bergmann /* 2c22c2c60SArnd Bergmann * Orion CPU Bridge Registers 3c22c2c60SArnd Bergmann * 4c22c2c60SArnd Bergmann * This file is licensed under the terms of the GNU General Public 5c22c2c60SArnd Bergmann * License version 2. This program is licensed "as is" without any 6c22c2c60SArnd Bergmann * warranty of any kind, whether express or implied. 7c22c2c60SArnd Bergmann */ 8c22c2c60SArnd Bergmann 9c22c2c60SArnd Bergmann #ifndef __ASM_ARCH_BRIDGE_REGS_H 10c22c2c60SArnd Bergmann #define __ASM_ARCH_BRIDGE_REGS_H 11c22c2c60SArnd Bergmann 12c22c2c60SArnd Bergmann #include "orion5x.h" 13c22c2c60SArnd Bergmann 14c22c2c60SArnd Bergmann #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) 15c22c2c60SArnd Bergmann 16c22c2c60SArnd Bergmann #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) 17c22c2c60SArnd Bergmann 18c22c2c60SArnd Bergmann #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) 19c22c2c60SArnd Bergmann #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108) 20c22c2c60SArnd Bergmann 21c22c2c60SArnd Bergmann #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) 22c22c2c60SArnd Bergmann 23c22c2c60SArnd Bergmann #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) 24c22c2c60SArnd Bergmann 25c22c2c60SArnd Bergmann #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) 26c22c2c60SArnd Bergmann 27c22c2c60SArnd Bergmann #define BRIDGE_INT_TIMER1_CLR (~0x0004) 28c22c2c60SArnd Bergmann 29c22c2c60SArnd Bergmann #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) 30c22c2c60SArnd Bergmann 31c22c2c60SArnd Bergmann #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) 32c22c2c60SArnd Bergmann 33c22c2c60SArnd Bergmann #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) 34c22c2c60SArnd Bergmann #define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) 35c22c2c60SArnd Bergmann #endif 36