1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OMAP Voltage Controller (VC) interface 4 * 5 * Copyright (C) 2011 Texas Instruments, Inc. 6 */ 7 #include <linux/kernel.h> 8 #include <linux/delay.h> 9 #include <linux/init.h> 10 #include <linux/bug.h> 11 #include <linux/io.h> 12 13 #include <asm/div64.h> 14 15 #include "iomap.h" 16 #include "soc.h" 17 #include "voltage.h" 18 #include "vc.h" 19 #include "prm-regbits-34xx.h" 20 #include "prm-regbits-44xx.h" 21 #include "prm44xx.h" 22 #include "pm.h" 23 #include "scrm44xx.h" 24 #include "control.h" 25 26 #define OMAP4430_VDD_IVA_I2C_DISABLE BIT(14) 27 #define OMAP4430_VDD_MPU_I2C_DISABLE BIT(13) 28 #define OMAP4430_VDD_CORE_I2C_DISABLE BIT(12) 29 #define OMAP4430_VDD_IVA_PRESENCE BIT(9) 30 #define OMAP4430_VDD_MPU_PRESENCE BIT(8) 31 #define OMAP4430_AUTO_CTRL_VDD_IVA(x) ((x) << 4) 32 #define OMAP4430_AUTO_CTRL_VDD_MPU(x) ((x) << 2) 33 #define OMAP4430_AUTO_CTRL_VDD_CORE(x) ((x) << 0) 34 #define OMAP4430_AUTO_CTRL_VDD_RET 2 35 36 #define OMAP4430_VDD_I2C_DISABLE_MASK \ 37 (OMAP4430_VDD_IVA_I2C_DISABLE | \ 38 OMAP4430_VDD_MPU_I2C_DISABLE | \ 39 OMAP4430_VDD_CORE_I2C_DISABLE) 40 41 #define OMAP4_VDD_DEFAULT_VAL \ 42 (OMAP4430_VDD_I2C_DISABLE_MASK | \ 43 OMAP4430_VDD_IVA_PRESENCE | OMAP4430_VDD_MPU_PRESENCE | \ 44 OMAP4430_AUTO_CTRL_VDD_IVA(OMAP4430_AUTO_CTRL_VDD_RET) | \ 45 OMAP4430_AUTO_CTRL_VDD_MPU(OMAP4430_AUTO_CTRL_VDD_RET) | \ 46 OMAP4430_AUTO_CTRL_VDD_CORE(OMAP4430_AUTO_CTRL_VDD_RET)) 47 48 #define OMAP4_VDD_RET_VAL \ 49 (OMAP4_VDD_DEFAULT_VAL & ~OMAP4430_VDD_I2C_DISABLE_MASK) 50 51 /** 52 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield 53 * @sa: bit for slave address 54 * @rav: bit for voltage configuration register 55 * @rac: bit for command configuration register 56 * @racen: enable bit for RAC 57 * @cmd: bit for command value set selection 58 * 59 * Channel configuration bits, common for OMAP3+ 60 * OMAP3 register: PRM_VC_CH_CONF 61 * OMAP4 register: PRM_VC_CFG_CHANNEL 62 * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG 63 */ 64 struct omap_vc_channel_cfg { 65 u8 sa; 66 u8 rav; 67 u8 rac; 68 u8 racen; 69 u8 cmd; 70 }; 71 72 static struct omap_vc_channel_cfg vc_default_channel_cfg = { 73 .sa = BIT(0), 74 .rav = BIT(1), 75 .rac = BIT(2), 76 .racen = BIT(3), 77 .cmd = BIT(4), 78 }; 79 80 /* 81 * On OMAP3+, all VC channels have the above default bitfield 82 * configuration, except the OMAP4 MPU channel. This appears 83 * to be a freak accident as every other VC channel has the 84 * default configuration, thus creating a mutant channel config. 85 */ 86 static struct omap_vc_channel_cfg vc_mutant_channel_cfg = { 87 .sa = BIT(0), 88 .rav = BIT(2), 89 .rac = BIT(3), 90 .racen = BIT(4), 91 .cmd = BIT(1), 92 }; 93 94 static struct omap_vc_channel_cfg *vc_cfg_bits; 95 96 /* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */ 97 static u32 sr_i2c_pcb_length = 63; 98 #define CFG_CHANNEL_MASK 0x1f 99 100 /** 101 * omap_vc_config_channel - configure VC channel to PMIC mappings 102 * @voltdm: pointer to voltagdomain defining the desired VC channel 103 * 104 * Configures the VC channel to PMIC mappings for the following 105 * PMIC settings 106 * - i2c slave address (SA) 107 * - voltage configuration address (RAV) 108 * - command configuration address (RAC) and enable bit (RACEN) 109 * - command values for ON, ONLP, RET and OFF (CMD) 110 * 111 * This function currently only allows flexible configuration of the 112 * non-default channel. Starting with OMAP4, there are more than 2 113 * channels, with one defined as the default (on OMAP4, it's MPU.) 114 * Only the non-default channel can be configured. 115 */ 116 static int omap_vc_config_channel(struct voltagedomain *voltdm) 117 { 118 struct omap_vc_channel *vc = voltdm->vc; 119 120 /* 121 * For default channel, the only configurable bit is RACEN. 122 * All others must stay at zero (see function comment above.) 123 */ 124 if (vc->flags & OMAP_VC_CHANNEL_DEFAULT) 125 vc->cfg_channel &= vc_cfg_bits->racen; 126 127 voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift, 128 vc->cfg_channel << vc->cfg_channel_sa_shift, 129 vc->cfg_channel_reg); 130 131 return 0; 132 } 133 134 /* Voltage scale and accessory APIs */ 135 int omap_vc_pre_scale(struct voltagedomain *voltdm, 136 unsigned long target_volt, 137 u8 *target_vsel, u8 *current_vsel) 138 { 139 struct omap_vc_channel *vc = voltdm->vc; 140 u32 vc_cmdval; 141 142 /* Check if sufficient pmic info is available for this vdd */ 143 if (!voltdm->pmic) { 144 pr_err("%s: Insufficient pmic info to scale the vdd_%s\n", 145 __func__, voltdm->name); 146 return -EINVAL; 147 } 148 149 if (!voltdm->pmic->uv_to_vsel) { 150 pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n", 151 __func__, voltdm->name); 152 return -ENODATA; 153 } 154 155 if (!voltdm->read || !voltdm->write) { 156 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 157 __func__, voltdm->name); 158 return -EINVAL; 159 } 160 161 *target_vsel = voltdm->pmic->uv_to_vsel(target_volt); 162 *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt); 163 164 /* Setting the ON voltage to the new target voltage */ 165 vc_cmdval = voltdm->read(vc->cmdval_reg); 166 vc_cmdval &= ~vc->common->cmd_on_mask; 167 vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift); 168 voltdm->write(vc_cmdval, vc->cmdval_reg); 169 170 voltdm->vc_param->on = target_volt; 171 172 omap_vp_update_errorgain(voltdm, target_volt); 173 174 return 0; 175 } 176 177 void omap_vc_post_scale(struct voltagedomain *voltdm, 178 unsigned long target_volt, 179 u8 target_vsel, u8 current_vsel) 180 { 181 u32 smps_steps = 0, smps_delay = 0; 182 183 smps_steps = abs(target_vsel - current_vsel); 184 /* SMPS slew rate / step size. 2us added as buffer. */ 185 smps_delay = ((smps_steps * voltdm->pmic->step_size) / 186 voltdm->pmic->slew_rate) + 2; 187 udelay(smps_delay); 188 } 189 190 /* vc_bypass_scale - VC bypass method of voltage scaling */ 191 int omap_vc_bypass_scale(struct voltagedomain *voltdm, 192 unsigned long target_volt) 193 { 194 struct omap_vc_channel *vc = voltdm->vc; 195 u32 loop_cnt = 0, retries_cnt = 0; 196 u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; 197 u8 target_vsel, current_vsel; 198 int ret; 199 200 ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel); 201 if (ret) 202 return ret; 203 204 vc_valid = vc->common->valid; 205 vc_bypass_val_reg = vc->common->bypass_val_reg; 206 vc_bypass_value = (target_vsel << vc->common->data_shift) | 207 (vc->volt_reg_addr << vc->common->regaddr_shift) | 208 (vc->i2c_slave_addr << vc->common->slaveaddr_shift); 209 210 voltdm->write(vc_bypass_value, vc_bypass_val_reg); 211 voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg); 212 213 vc_bypass_value = voltdm->read(vc_bypass_val_reg); 214 /* 215 * Loop till the bypass command is acknowledged from the SMPS. 216 * NOTE: This is legacy code. The loop count and retry count needs 217 * to be revisited. 218 */ 219 while (!(vc_bypass_value & vc_valid)) { 220 loop_cnt++; 221 222 if (retries_cnt > 10) { 223 pr_warn("%s: Retry count exceeded\n", __func__); 224 return -ETIMEDOUT; 225 } 226 227 if (loop_cnt > 50) { 228 retries_cnt++; 229 loop_cnt = 0; 230 udelay(10); 231 } 232 vc_bypass_value = voltdm->read(vc_bypass_val_reg); 233 } 234 235 omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel); 236 return 0; 237 } 238 239 /* Convert microsecond value to number of 32kHz clock cycles */ 240 static inline u32 omap_usec_to_32k(u32 usec) 241 { 242 return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL); 243 } 244 245 struct omap3_vc_timings { 246 u32 voltsetup1; 247 u32 voltsetup2; 248 }; 249 250 struct omap3_vc { 251 struct voltagedomain *vd; 252 u32 voltctrl; 253 u32 voltsetup1; 254 u32 voltsetup2; 255 struct omap3_vc_timings timings[2]; 256 }; 257 static struct omap3_vc vc; 258 259 void omap3_vc_set_pmic_signaling(int core_next_state) 260 { 261 struct voltagedomain *vd = vc.vd; 262 struct omap3_vc_timings *c = vc.timings; 263 u32 voltctrl, voltsetup1, voltsetup2; 264 265 voltctrl = vc.voltctrl; 266 voltsetup1 = vc.voltsetup1; 267 voltsetup2 = vc.voltsetup2; 268 269 switch (core_next_state) { 270 case PWRDM_POWER_OFF: 271 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET | 272 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); 273 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF; 274 if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF) 275 voltsetup2 = c->voltsetup2; 276 else 277 voltsetup1 = c->voltsetup1; 278 break; 279 case PWRDM_POWER_RET: 280 default: 281 c++; 282 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF | 283 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); 284 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET; 285 voltsetup1 = c->voltsetup1; 286 break; 287 } 288 289 if (voltctrl != vc.voltctrl) { 290 vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET); 291 vc.voltctrl = voltctrl; 292 } 293 if (voltsetup1 != vc.voltsetup1) { 294 vd->write(c->voltsetup1, 295 OMAP3_PRM_VOLTSETUP1_OFFSET); 296 vc.voltsetup1 = voltsetup1; 297 } 298 if (voltsetup2 != vc.voltsetup2) { 299 vd->write(c->voltsetup2, 300 OMAP3_PRM_VOLTSETUP2_OFFSET); 301 vc.voltsetup2 = voltsetup2; 302 } 303 } 304 305 void omap4_vc_set_pmic_signaling(int core_next_state) 306 { 307 struct voltagedomain *vd = vc.vd; 308 u32 val; 309 310 if (!vd) 311 return; 312 313 switch (core_next_state) { 314 case PWRDM_POWER_RET: 315 val = OMAP4_VDD_RET_VAL; 316 break; 317 default: 318 val = OMAP4_VDD_DEFAULT_VAL; 319 break; 320 } 321 322 vd->write(val, OMAP4_PRM_VOLTCTRL_OFFSET); 323 } 324 325 /* 326 * Configure signal polarity for sys_clkreq and sys_off_mode pins 327 * as the default values are wrong and can cause the system to hang 328 * if any twl4030 scripts are loaded. 329 */ 330 static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm) 331 { 332 u32 val; 333 334 if (vc.vd) 335 return; 336 337 vc.vd = voltdm; 338 339 val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET); 340 if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) || 341 (val & OMAP3430_PRM_POLCTRL_OFFMODE_POL)) { 342 val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL; 343 val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL; 344 pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n", 345 val); 346 voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET); 347 } 348 349 /* 350 * By default let's use I2C4 signaling for retention idle 351 * and sys_off_mode pin signaling for off idle. This way we 352 * have sys_clk_req pin go down for retention and both 353 * sys_clk_req and sys_off_mode pins will go down for off 354 * idle. And we can also scale voltages to zero for off-idle. 355 * Note that no actual voltage scaling during off-idle will 356 * happen unless the board specific twl4030 PMIC scripts are 357 * loaded. See also omap_vc_i2c_init for comments regarding 358 * erratum i531. 359 */ 360 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); 361 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { 362 val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF; 363 pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n", 364 val); 365 voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET); 366 } 367 vc.voltctrl = val; 368 369 omap3_vc_set_pmic_signaling(PWRDM_POWER_ON); 370 } 371 372 static void omap3_init_voltsetup1(struct voltagedomain *voltdm, 373 struct omap3_vc_timings *c, u32 idle) 374 { 375 unsigned long val; 376 377 val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate; 378 val *= voltdm->sys_clk.rate / 8 / 1000000 + 1; 379 val <<= __ffs(voltdm->vfsm->voltsetup_mask); 380 c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask; 381 c->voltsetup1 |= val; 382 } 383 384 /** 385 * omap3_set_i2c_timings - sets i2c sleep timings for a channel 386 * @voltdm: channel to configure 387 * @off_mode: select whether retention or off mode values used 388 * 389 * Calculates and sets up voltage controller to use I2C based 390 * voltage scaling for sleep modes. This can be used for either off mode 391 * or retention. Off mode has additionally an option to use sys_off_mode 392 * pad, which uses a global signal to program the whole power IC to 393 * off-mode. 394 * 395 * Note that pmic is not controlling the voltage scaling during 396 * retention signaled over I2C4, so we can keep voltsetup2 as 0. 397 * And the oscillator is not shut off over I2C4, so no need to 398 * set clksetup. 399 */ 400 static void omap3_set_i2c_timings(struct voltagedomain *voltdm) 401 { 402 struct omap3_vc_timings *c = vc.timings; 403 404 /* Configure PRWDM_POWER_OFF over I2C4 */ 405 omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off); 406 c++; 407 /* Configure PRWDM_POWER_RET over I2C4 */ 408 omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret); 409 } 410 411 /** 412 * omap3_set_off_timings - sets off-mode timings for a channel 413 * @voltdm: channel to configure 414 * 415 * Calculates and sets up off-mode timings for a channel. Off-mode 416 * can use either I2C based voltage scaling, or alternatively 417 * sys_off_mode pad can be used to send a global command to power IC.n, 418 * sys_off_mode has the additional benefit that voltages can be 419 * scaled to zero volt level with TWL4030 / TWL5030, I2C can only 420 * scale to 600mV. 421 * 422 * Note that omap is not controlling the voltage scaling during 423 * off idle signaled by sys_off_mode, so we can keep voltsetup1 424 * as 0. 425 */ 426 static void omap3_set_off_timings(struct voltagedomain *voltdm) 427 { 428 struct omap3_vc_timings *c = vc.timings; 429 u32 tstart, tshut, clksetup, voltoffset; 430 431 if (c->voltsetup2) 432 return; 433 434 omap_pm_get_oscillator(&tstart, &tshut); 435 if (tstart == ULONG_MAX) { 436 pr_debug("PM: oscillator start-up time not initialized, using 10ms\n"); 437 clksetup = omap_usec_to_32k(10000); 438 } else { 439 clksetup = omap_usec_to_32k(tstart); 440 } 441 442 /* 443 * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to 444 * switch from HFCLKIN to internal oscillator. That means timings 445 * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And 446 * that means we can calculate the value based on the oscillator 447 * start-up time since voltoffset2 = clksetup - voltoffset. 448 */ 449 voltoffset = omap_usec_to_32k(488); 450 c->voltsetup2 = clksetup - voltoffset; 451 voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET); 452 voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET); 453 } 454 455 static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) 456 { 457 omap3_vc_init_pmic_signaling(voltdm); 458 omap3_set_off_timings(voltdm); 459 omap3_set_i2c_timings(voltdm); 460 } 461 462 /** 463 * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4 464 * @voltdm: channel to calculate values for 465 * @voltage_diff: voltage difference in microvolts 466 * 467 * Calculates voltage ramp prescaler + counter values for a voltage 468 * difference on omap4. Returns a field value suitable for writing to 469 * VOLTSETUP register for a channel in following format: 470 * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference. 471 */ 472 static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff) 473 { 474 u32 prescaler; 475 u32 cycles; 476 u32 time; 477 478 time = voltage_diff / voltdm->pmic->slew_rate; 479 480 cycles = voltdm->sys_clk.rate / 1000 * time / 1000; 481 482 cycles /= 64; 483 prescaler = 0; 484 485 /* shift to next prescaler until no overflow */ 486 487 /* scale for div 256 = 64 * 4 */ 488 if (cycles > 63) { 489 cycles /= 4; 490 prescaler++; 491 } 492 493 /* scale for div 512 = 256 * 2 */ 494 if (cycles > 63) { 495 cycles /= 2; 496 prescaler++; 497 } 498 499 /* scale for div 2048 = 512 * 4 */ 500 if (cycles > 63) { 501 cycles /= 4; 502 prescaler++; 503 } 504 505 /* check for overflow => invalid ramp time */ 506 if (cycles > 63) { 507 pr_warn("%s: invalid setuptime for vdd_%s\n", __func__, 508 voltdm->name); 509 return 0; 510 } 511 512 cycles++; 513 514 return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) | 515 (cycles << OMAP4430_RAMP_UP_COUNT_SHIFT); 516 } 517 518 /** 519 * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield 520 * @usec: microseconds 521 * @shift: number of bits to shift left 522 * @mask: bitfield mask 523 * 524 * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is 525 * shifted to requested position, and checked agains the mask value. 526 * If larger, forced to the max value of the field (i.e. the mask itself.) 527 * Returns the SCRM bitfield value. 528 */ 529 static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask) 530 { 531 u32 val; 532 533 val = omap_usec_to_32k(usec) << shift; 534 535 /* Check for overflow, if yes, force to max value */ 536 if (val > mask) 537 val = mask; 538 539 return val; 540 } 541 542 /** 543 * omap4_set_timings - set voltage ramp timings for a channel 544 * @voltdm: channel to configure 545 * @off_mode: whether off-mode values are used 546 * 547 * Calculates and sets the voltage ramp up / down values for a channel. 548 */ 549 static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode) 550 { 551 u32 val; 552 u32 ramp; 553 int offset; 554 u32 tstart, tshut; 555 556 if (off_mode) { 557 ramp = omap4_calc_volt_ramp(voltdm, 558 voltdm->vc_param->on - voltdm->vc_param->off); 559 offset = voltdm->vfsm->voltsetup_off_reg; 560 } else { 561 ramp = omap4_calc_volt_ramp(voltdm, 562 voltdm->vc_param->on - voltdm->vc_param->ret); 563 offset = voltdm->vfsm->voltsetup_reg; 564 } 565 566 if (!ramp) 567 return; 568 569 val = voltdm->read(offset); 570 571 val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT; 572 573 val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT; 574 575 voltdm->write(val, offset); 576 577 omap_pm_get_oscillator(&tstart, &tshut); 578 579 val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT, 580 OMAP4_SETUPTIME_MASK); 581 val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT, 582 OMAP4_DOWNTIME_MASK); 583 584 writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME); 585 } 586 587 static void __init omap4_vc_init_pmic_signaling(struct voltagedomain *voltdm) 588 { 589 if (vc.vd) 590 return; 591 592 vc.vd = voltdm; 593 voltdm->write(OMAP4_VDD_DEFAULT_VAL, OMAP4_PRM_VOLTCTRL_OFFSET); 594 } 595 596 /* OMAP4 specific voltage init functions */ 597 static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) 598 { 599 omap4_vc_init_pmic_signaling(voltdm); 600 omap4_set_timings(voltdm, true); 601 omap4_set_timings(voltdm, false); 602 } 603 604 struct i2c_init_data { 605 u8 loadbits; 606 u8 load; 607 u8 hsscll_38_4; 608 u8 hsscll_26; 609 u8 hsscll_19_2; 610 u8 hsscll_16_8; 611 u8 hsscll_12; 612 }; 613 614 static const struct i2c_init_data omap4_i2c_timing_data[] __initconst = { 615 { 616 .load = 50, 617 .loadbits = 0x3, 618 .hsscll_38_4 = 13, 619 .hsscll_26 = 11, 620 .hsscll_19_2 = 9, 621 .hsscll_16_8 = 9, 622 .hsscll_12 = 8, 623 }, 624 { 625 .load = 25, 626 .loadbits = 0x2, 627 .hsscll_38_4 = 13, 628 .hsscll_26 = 11, 629 .hsscll_19_2 = 9, 630 .hsscll_16_8 = 9, 631 .hsscll_12 = 8, 632 }, 633 { 634 .load = 12, 635 .loadbits = 0x1, 636 .hsscll_38_4 = 11, 637 .hsscll_26 = 10, 638 .hsscll_19_2 = 9, 639 .hsscll_16_8 = 9, 640 .hsscll_12 = 8, 641 }, 642 { 643 .load = 0, 644 .loadbits = 0x0, 645 .hsscll_38_4 = 12, 646 .hsscll_26 = 10, 647 .hsscll_19_2 = 9, 648 .hsscll_16_8 = 8, 649 .hsscll_12 = 8, 650 }, 651 }; 652 653 /** 654 * omap4_vc_i2c_timing_init - sets up board I2C timing parameters 655 * @voltdm: voltagedomain pointer to get data from 656 * 657 * Use PMIC + board supplied settings for calculating the total I2C 658 * channel capacitance and set the timing parameters based on this. 659 * Pre-calculated values are provided in data tables, as it is not 660 * too straightforward to calculate these runtime. 661 */ 662 static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm) 663 { 664 u32 capacitance; 665 u32 val; 666 u16 hsscll; 667 const struct i2c_init_data *i2c_data; 668 669 if (!voltdm->pmic->i2c_high_speed) { 670 pr_info("%s: using bootloader low-speed timings\n", __func__); 671 return; 672 } 673 674 /* PCB trace capacitance, 0.125pF / mm => mm / 8 */ 675 capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8); 676 677 /* OMAP pad capacitance */ 678 capacitance += 4; 679 680 /* PMIC pad capacitance */ 681 capacitance += voltdm->pmic->i2c_pad_load; 682 683 /* Search for capacitance match in the table */ 684 i2c_data = omap4_i2c_timing_data; 685 686 while (i2c_data->load > capacitance) 687 i2c_data++; 688 689 /* Select proper values based on sysclk frequency */ 690 switch (voltdm->sys_clk.rate) { 691 case 38400000: 692 hsscll = i2c_data->hsscll_38_4; 693 break; 694 case 26000000: 695 hsscll = i2c_data->hsscll_26; 696 break; 697 case 19200000: 698 hsscll = i2c_data->hsscll_19_2; 699 break; 700 case 16800000: 701 hsscll = i2c_data->hsscll_16_8; 702 break; 703 case 12000000: 704 hsscll = i2c_data->hsscll_12; 705 break; 706 default: 707 pr_warn("%s: unsupported sysclk rate: %d!\n", __func__, 708 voltdm->sys_clk.rate); 709 return; 710 } 711 712 /* Loadbits define pull setup for the I2C channels */ 713 val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29; 714 715 /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */ 716 writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP + 717 OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2)); 718 719 /* HSSCLH can always be zero */ 720 val = hsscll << OMAP4430_HSSCLL_SHIFT; 721 val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT); 722 723 /* Write setup times to I2C config register */ 724 voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); 725 } 726 727 728 729 /** 730 * omap_vc_i2c_init - initialize I2C interface to PMIC 731 * @voltdm: voltage domain containing VC data 732 * 733 * Use PMIC supplied settings for I2C high-speed mode and 734 * master code (if set) and program the VC I2C configuration 735 * register. 736 * 737 * The VC I2C configuration is common to all VC channels, 738 * so this function only configures I2C for the first VC 739 * channel registers. All other VC channels will use the 740 * same configuration. 741 */ 742 static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) 743 { 744 struct omap_vc_channel *vc = voltdm->vc; 745 static bool initialized; 746 static bool i2c_high_speed; 747 u8 mcode; 748 749 if (initialized) { 750 if (voltdm->pmic->i2c_high_speed != i2c_high_speed) 751 pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n", 752 __func__, voltdm->name, i2c_high_speed); 753 return; 754 } 755 756 /* 757 * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around 758 * erratum i531 "Extra Power Consumed When Repeated Start Operation 759 * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)". 760 * Otherwise I2C4 eventually leads into about 23mW extra power being 761 * consumed even during off idle using VMODE. 762 */ 763 i2c_high_speed = voltdm->pmic->i2c_high_speed; 764 if (i2c_high_speed) 765 voltdm->rmw(vc->common->i2c_cfg_clear_mask, 766 vc->common->i2c_cfg_hsen_mask, 767 vc->common->i2c_cfg_reg); 768 769 mcode = voltdm->pmic->i2c_mcode; 770 if (mcode) 771 voltdm->rmw(vc->common->i2c_mcode_mask, 772 mcode << __ffs(vc->common->i2c_mcode_mask), 773 vc->common->i2c_cfg_reg); 774 775 if (cpu_is_omap44xx()) 776 omap4_vc_i2c_timing_init(voltdm); 777 778 initialized = true; 779 } 780 781 /** 782 * omap_vc_calc_vsel - calculate vsel value for a channel 783 * @voltdm: channel to calculate value for 784 * @uvolt: microvolt value to convert to vsel 785 * 786 * Converts a microvolt value to vsel value for the used PMIC. 787 * This checks whether the microvolt value is out of bounds, and 788 * adjusts the value accordingly. If unsupported value detected, 789 * warning is thrown. 790 */ 791 static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt) 792 { 793 if (voltdm->pmic->vddmin > uvolt) 794 uvolt = voltdm->pmic->vddmin; 795 if (voltdm->pmic->vddmax < uvolt) { 796 WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n", 797 __func__, uvolt, voltdm->pmic->vddmax); 798 /* Lets try maximum value anyway */ 799 uvolt = voltdm->pmic->vddmax; 800 } 801 802 return voltdm->pmic->uv_to_vsel(uvolt); 803 } 804 805 void __init omap_vc_init_channel(struct voltagedomain *voltdm) 806 { 807 struct omap_vc_channel *vc = voltdm->vc; 808 u8 on_vsel, onlp_vsel, ret_vsel, off_vsel; 809 u32 val; 810 811 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { 812 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name); 813 return; 814 } 815 816 if (!voltdm->read || !voltdm->write) { 817 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 818 __func__, voltdm->name); 819 return; 820 } 821 822 vc->cfg_channel = 0; 823 if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT) 824 vc_cfg_bits = &vc_mutant_channel_cfg; 825 else 826 vc_cfg_bits = &vc_default_channel_cfg; 827 828 /* get PMIC/board specific settings */ 829 vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr; 830 vc->volt_reg_addr = voltdm->pmic->volt_reg_addr; 831 vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr; 832 833 /* Configure the i2c slave address for this VC */ 834 voltdm->rmw(vc->smps_sa_mask, 835 vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), 836 vc->smps_sa_reg); 837 vc->cfg_channel |= vc_cfg_bits->sa; 838 839 /* 840 * Configure the PMIC register addresses. 841 */ 842 voltdm->rmw(vc->smps_volra_mask, 843 vc->volt_reg_addr << __ffs(vc->smps_volra_mask), 844 vc->smps_volra_reg); 845 vc->cfg_channel |= vc_cfg_bits->rav; 846 847 if (vc->cmd_reg_addr) { 848 voltdm->rmw(vc->smps_cmdra_mask, 849 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), 850 vc->smps_cmdra_reg); 851 vc->cfg_channel |= vc_cfg_bits->rac; 852 } 853 854 if (vc->cmd_reg_addr == vc->volt_reg_addr) 855 vc->cfg_channel |= vc_cfg_bits->racen; 856 857 /* Set up the on, inactive, retention and off voltage */ 858 on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on); 859 onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp); 860 ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret); 861 off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off); 862 863 val = ((on_vsel << vc->common->cmd_on_shift) | 864 (onlp_vsel << vc->common->cmd_onlp_shift) | 865 (ret_vsel << vc->common->cmd_ret_shift) | 866 (off_vsel << vc->common->cmd_off_shift)); 867 voltdm->write(val, vc->cmdval_reg); 868 vc->cfg_channel |= vc_cfg_bits->cmd; 869 870 /* Channel configuration */ 871 omap_vc_config_channel(voltdm); 872 873 omap_vc_i2c_init(voltdm); 874 875 if (cpu_is_omap34xx()) 876 omap3_vc_init_channel(voltdm); 877 else if (cpu_is_omap44xx()) 878 omap4_vc_init_channel(voltdm); 879 } 880