1 /* 2 * OMAP Voltage Controller (VC) interface 3 * 4 * Copyright (C) 2011 Texas Instruments, Inc. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 #include <linux/kernel.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/bug.h> 14 15 #include <plat/cpu.h> 16 17 #include "voltage.h" 18 #include "vc.h" 19 #include "prm-regbits-34xx.h" 20 #include "prm-regbits-44xx.h" 21 #include "prm44xx.h" 22 23 /** 24 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield 25 * @sa: bit for slave address 26 * @rav: bit for voltage configuration register 27 * @rac: bit for command configuration register 28 * @racen: enable bit for RAC 29 * @cmd: bit for command value set selection 30 * 31 * Channel configuration bits, common for OMAP3+ 32 * OMAP3 register: PRM_VC_CH_CONF 33 * OMAP4 register: PRM_VC_CFG_CHANNEL 34 * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG 35 */ 36 struct omap_vc_channel_cfg { 37 u8 sa; 38 u8 rav; 39 u8 rac; 40 u8 racen; 41 u8 cmd; 42 }; 43 44 static struct omap_vc_channel_cfg vc_default_channel_cfg = { 45 .sa = BIT(0), 46 .rav = BIT(1), 47 .rac = BIT(2), 48 .racen = BIT(3), 49 .cmd = BIT(4), 50 }; 51 52 /* 53 * On OMAP3+, all VC channels have the above default bitfield 54 * configuration, except the OMAP4 MPU channel. This appears 55 * to be a freak accident as every other VC channel has the 56 * default configuration, thus creating a mutant channel config. 57 */ 58 static struct omap_vc_channel_cfg vc_mutant_channel_cfg = { 59 .sa = BIT(0), 60 .rav = BIT(2), 61 .rac = BIT(3), 62 .racen = BIT(4), 63 .cmd = BIT(1), 64 }; 65 66 static struct omap_vc_channel_cfg *vc_cfg_bits; 67 #define CFG_CHANNEL_MASK 0x1f 68 69 /** 70 * omap_vc_config_channel - configure VC channel to PMIC mappings 71 * @voltdm: pointer to voltagdomain defining the desired VC channel 72 * 73 * Configures the VC channel to PMIC mappings for the following 74 * PMIC settings 75 * - i2c slave address (SA) 76 * - voltage configuration address (RAV) 77 * - command configuration address (RAC) and enable bit (RACEN) 78 * - command values for ON, ONLP, RET and OFF (CMD) 79 * 80 * This function currently only allows flexible configuration of the 81 * non-default channel. Starting with OMAP4, there are more than 2 82 * channels, with one defined as the default (on OMAP4, it's MPU.) 83 * Only the non-default channel can be configured. 84 */ 85 static int omap_vc_config_channel(struct voltagedomain *voltdm) 86 { 87 struct omap_vc_channel *vc = voltdm->vc; 88 89 /* 90 * For default channel, the only configurable bit is RACEN. 91 * All others must stay at zero (see function comment above.) 92 */ 93 if (vc->flags & OMAP_VC_CHANNEL_DEFAULT) 94 vc->cfg_channel &= vc_cfg_bits->racen; 95 96 voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift, 97 vc->cfg_channel << vc->cfg_channel_sa_shift, 98 vc->cfg_channel_reg); 99 100 return 0; 101 } 102 103 /* Voltage scale and accessory APIs */ 104 int omap_vc_pre_scale(struct voltagedomain *voltdm, 105 unsigned long target_volt, 106 u8 *target_vsel, u8 *current_vsel) 107 { 108 struct omap_vc_channel *vc = voltdm->vc; 109 u32 vc_cmdval; 110 111 /* Check if sufficient pmic info is available for this vdd */ 112 if (!voltdm->pmic) { 113 pr_err("%s: Insufficient pmic info to scale the vdd_%s\n", 114 __func__, voltdm->name); 115 return -EINVAL; 116 } 117 118 if (!voltdm->pmic->uv_to_vsel) { 119 pr_err("%s: PMIC function to convert voltage in uV to" 120 "vsel not registered. Hence unable to scale voltage" 121 "for vdd_%s\n", __func__, voltdm->name); 122 return -ENODATA; 123 } 124 125 if (!voltdm->read || !voltdm->write) { 126 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 127 __func__, voltdm->name); 128 return -EINVAL; 129 } 130 131 *target_vsel = voltdm->pmic->uv_to_vsel(target_volt); 132 *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt); 133 134 /* Setting the ON voltage to the new target voltage */ 135 vc_cmdval = voltdm->read(vc->cmdval_reg); 136 vc_cmdval &= ~vc->common->cmd_on_mask; 137 vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift); 138 voltdm->write(vc_cmdval, vc->cmdval_reg); 139 140 omap_vp_update_errorgain(voltdm, target_volt); 141 142 return 0; 143 } 144 145 void omap_vc_post_scale(struct voltagedomain *voltdm, 146 unsigned long target_volt, 147 u8 target_vsel, u8 current_vsel) 148 { 149 u32 smps_steps = 0, smps_delay = 0; 150 151 smps_steps = abs(target_vsel - current_vsel); 152 /* SMPS slew rate / step size. 2us added as buffer. */ 153 smps_delay = ((smps_steps * voltdm->pmic->step_size) / 154 voltdm->pmic->slew_rate) + 2; 155 udelay(smps_delay); 156 } 157 158 /* vc_bypass_scale - VC bypass method of voltage scaling */ 159 int omap_vc_bypass_scale(struct voltagedomain *voltdm, 160 unsigned long target_volt) 161 { 162 struct omap_vc_channel *vc = voltdm->vc; 163 u32 loop_cnt = 0, retries_cnt = 0; 164 u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; 165 u8 target_vsel, current_vsel; 166 int ret; 167 168 ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel); 169 if (ret) 170 return ret; 171 172 vc_valid = vc->common->valid; 173 vc_bypass_val_reg = vc->common->bypass_val_reg; 174 vc_bypass_value = (target_vsel << vc->common->data_shift) | 175 (vc->volt_reg_addr << vc->common->regaddr_shift) | 176 (vc->i2c_slave_addr << vc->common->slaveaddr_shift); 177 178 voltdm->write(vc_bypass_value, vc_bypass_val_reg); 179 voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg); 180 181 vc_bypass_value = voltdm->read(vc_bypass_val_reg); 182 /* 183 * Loop till the bypass command is acknowledged from the SMPS. 184 * NOTE: This is legacy code. The loop count and retry count needs 185 * to be revisited. 186 */ 187 while (!(vc_bypass_value & vc_valid)) { 188 loop_cnt++; 189 190 if (retries_cnt > 10) { 191 pr_warning("%s: Retry count exceeded\n", __func__); 192 return -ETIMEDOUT; 193 } 194 195 if (loop_cnt > 50) { 196 retries_cnt++; 197 loop_cnt = 0; 198 udelay(10); 199 } 200 vc_bypass_value = voltdm->read(vc_bypass_val_reg); 201 } 202 203 omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel); 204 return 0; 205 } 206 207 static void __init omap3_vfsm_init(struct voltagedomain *voltdm) 208 { 209 /* 210 * Voltage Manager FSM parameters init 211 * XXX This data should be passed in from the board file 212 */ 213 voltdm->write(OMAP3_CLKSETUP, OMAP3_PRM_CLKSETUP_OFFSET); 214 voltdm->write(OMAP3_VOLTOFFSET, OMAP3_PRM_VOLTOFFSET_OFFSET); 215 voltdm->write(OMAP3_VOLTSETUP2, OMAP3_PRM_VOLTSETUP2_OFFSET); 216 } 217 218 static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) 219 { 220 static bool is_initialized; 221 222 if (is_initialized) 223 return; 224 225 omap3_vfsm_init(voltdm); 226 227 is_initialized = true; 228 } 229 230 231 /* OMAP4 specific voltage init functions */ 232 static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) 233 { 234 static bool is_initialized; 235 u32 vc_val; 236 237 if (is_initialized) 238 return; 239 240 /* XXX These are magic numbers and do not belong! */ 241 vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT); 242 voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); 243 244 is_initialized = true; 245 } 246 247 /** 248 * omap_vc_i2c_init - initialize I2C interface to PMIC 249 * @voltdm: voltage domain containing VC data 250 * 251 * Use PMIC supplied settings for I2C high-speed mode and 252 * master code (if set) and program the VC I2C configuration 253 * register. 254 * 255 * The VC I2C configuration is common to all VC channels, 256 * so this function only configures I2C for the first VC 257 * channel registers. All other VC channels will use the 258 * same configuration. 259 */ 260 static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) 261 { 262 struct omap_vc_channel *vc = voltdm->vc; 263 static bool initialized; 264 static bool i2c_high_speed; 265 u8 mcode; 266 267 if (initialized) { 268 if (voltdm->pmic->i2c_high_speed != i2c_high_speed) 269 pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).", 270 __func__, voltdm->name, i2c_high_speed); 271 return; 272 } 273 274 i2c_high_speed = voltdm->pmic->i2c_high_speed; 275 if (i2c_high_speed) 276 voltdm->rmw(vc->common->i2c_cfg_hsen_mask, 277 vc->common->i2c_cfg_hsen_mask, 278 vc->common->i2c_cfg_reg); 279 280 mcode = voltdm->pmic->i2c_mcode; 281 if (mcode) 282 voltdm->rmw(vc->common->i2c_mcode_mask, 283 mcode << __ffs(vc->common->i2c_mcode_mask), 284 vc->common->i2c_cfg_reg); 285 286 initialized = true; 287 } 288 289 void __init omap_vc_init_channel(struct voltagedomain *voltdm) 290 { 291 struct omap_vc_channel *vc = voltdm->vc; 292 u8 on_vsel, onlp_vsel, ret_vsel, off_vsel; 293 u32 val; 294 295 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { 296 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name); 297 return; 298 } 299 300 if (!voltdm->read || !voltdm->write) { 301 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 302 __func__, voltdm->name); 303 return; 304 } 305 306 vc->cfg_channel = 0; 307 if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT) 308 vc_cfg_bits = &vc_mutant_channel_cfg; 309 else 310 vc_cfg_bits = &vc_default_channel_cfg; 311 312 /* get PMIC/board specific settings */ 313 vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr; 314 vc->volt_reg_addr = voltdm->pmic->volt_reg_addr; 315 vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr; 316 vc->setup_time = voltdm->pmic->volt_setup_time; 317 318 /* Configure the i2c slave address for this VC */ 319 voltdm->rmw(vc->smps_sa_mask, 320 vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), 321 vc->smps_sa_reg); 322 vc->cfg_channel |= vc_cfg_bits->sa; 323 324 /* 325 * Configure the PMIC register addresses. 326 */ 327 voltdm->rmw(vc->smps_volra_mask, 328 vc->volt_reg_addr << __ffs(vc->smps_volra_mask), 329 vc->smps_volra_reg); 330 vc->cfg_channel |= vc_cfg_bits->rav; 331 332 if (vc->cmd_reg_addr) { 333 voltdm->rmw(vc->smps_cmdra_mask, 334 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), 335 vc->smps_cmdra_reg); 336 vc->cfg_channel |= vc_cfg_bits->rac | vc_cfg_bits->racen; 337 } 338 339 /* Set up the on, inactive, retention and off voltage */ 340 on_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->on_volt); 341 onlp_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->onlp_volt); 342 ret_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->ret_volt); 343 off_vsel = voltdm->pmic->uv_to_vsel(voltdm->pmic->off_volt); 344 val = ((on_vsel << vc->common->cmd_on_shift) | 345 (onlp_vsel << vc->common->cmd_onlp_shift) | 346 (ret_vsel << vc->common->cmd_ret_shift) | 347 (off_vsel << vc->common->cmd_off_shift)); 348 voltdm->write(val, vc->cmdval_reg); 349 vc->cfg_channel |= vc_cfg_bits->cmd; 350 351 /* Channel configuration */ 352 omap_vc_config_channel(voltdm); 353 354 /* Configure the setup times */ 355 voltdm->rmw(voltdm->vfsm->voltsetup_mask, 356 vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask), 357 voltdm->vfsm->voltsetup_reg); 358 359 omap_vc_i2c_init(voltdm); 360 361 if (cpu_is_omap34xx()) 362 omap3_vc_init_channel(voltdm); 363 else if (cpu_is_omap44xx()) 364 omap4_vc_init_channel(voltdm); 365 } 366 367