1 /* 2 * linux/arch/arm/mach-omap2/timer.c 3 * 4 * OMAP2 GP timer support. 5 * 6 * Copyright (C) 2009 Nokia Corporation 7 * 8 * Update to use new clocksource/clockevent layers 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 10 * Copyright (C) 2007 MontaVista Software, Inc. 11 * 12 * Original driver: 13 * Copyright (C) 2005 Nokia Corporation 14 * Author: Paul Mundt <paul.mundt@nokia.com> 15 * Juha Yrjölä <juha.yrjola@nokia.com> 16 * OMAP Dual-mode timer framework support by Timo Teras 17 * 18 * Some parts based off of TI's 24xx code: 19 * 20 * Copyright (C) 2004-2009 Texas Instruments, Inc. 21 * 22 * Roughly modelled after the OMAP1 MPU timer code. 23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 24 * 25 * This file is subject to the terms and conditions of the GNU General Public 26 * License. See the file "COPYING" in the main directory of this archive 27 * for more details. 28 */ 29 #include <linux/init.h> 30 #include <linux/time.h> 31 #include <linux/interrupt.h> 32 #include <linux/err.h> 33 #include <linux/clk.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/clocksource.h> 37 #include <linux/clockchips.h> 38 #include <linux/slab.h> 39 #include <linux/of.h> 40 #include <linux/of_address.h> 41 #include <linux/of_irq.h> 42 #include <linux/platform_device.h> 43 #include <linux/platform_data/dmtimer-omap.h> 44 #include <linux/sched_clock.h> 45 46 #include <asm/mach/time.h> 47 #include <asm/smp_twd.h> 48 49 #include "omap_hwmod.h" 50 #include "omap_device.h" 51 #include <plat/counter-32k.h> 52 #include <plat/dmtimer.h> 53 #include "omap-pm.h" 54 55 #include "soc.h" 56 #include "common.h" 57 #include "control.h" 58 #include "powerdomain.h" 59 #include "omap-secure.h" 60 61 #define REALTIME_COUNTER_BASE 0x48243200 62 #define INCREMENTER_NUMERATOR_OFFSET 0x10 63 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 64 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 65 66 /* Clockevent code */ 67 68 static struct omap_dm_timer clkev; 69 static struct clock_event_device clockevent_gpt; 70 71 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 72 static unsigned long arch_timer_freq; 73 74 void set_cntfreq(void) 75 { 76 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); 77 } 78 #endif 79 80 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 81 { 82 struct clock_event_device *evt = &clockevent_gpt; 83 84 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); 85 86 evt->event_handler(evt); 87 return IRQ_HANDLED; 88 } 89 90 static struct irqaction omap2_gp_timer_irq = { 91 .name = "gp_timer", 92 .flags = IRQF_TIMER | IRQF_IRQPOLL, 93 .handler = omap2_gp_timer_interrupt, 94 }; 95 96 static int omap2_gp_timer_set_next_event(unsigned long cycles, 97 struct clock_event_device *evt) 98 { 99 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 100 0xffffffff - cycles, OMAP_TIMER_POSTED); 101 102 return 0; 103 } 104 105 static void omap2_gp_timer_set_mode(enum clock_event_mode mode, 106 struct clock_event_device *evt) 107 { 108 u32 period; 109 110 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); 111 112 switch (mode) { 113 case CLOCK_EVT_MODE_PERIODIC: 114 period = clkev.rate / HZ; 115 period -= 1; 116 /* Looks like we need to first set the load value separately */ 117 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 118 0xffffffff - period, OMAP_TIMER_POSTED); 119 __omap_dm_timer_load_start(&clkev, 120 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 121 0xffffffff - period, OMAP_TIMER_POSTED); 122 break; 123 case CLOCK_EVT_MODE_ONESHOT: 124 break; 125 case CLOCK_EVT_MODE_UNUSED: 126 case CLOCK_EVT_MODE_SHUTDOWN: 127 case CLOCK_EVT_MODE_RESUME: 128 break; 129 } 130 } 131 132 static struct clock_event_device clockevent_gpt = { 133 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 134 .rating = 300, 135 .set_next_event = omap2_gp_timer_set_next_event, 136 .set_mode = omap2_gp_timer_set_mode, 137 }; 138 139 static struct property device_disabled = { 140 .name = "status", 141 .length = sizeof("disabled"), 142 .value = "disabled", 143 }; 144 145 static const struct of_device_id omap_timer_match[] __initconst = { 146 { .compatible = "ti,omap2420-timer", }, 147 { .compatible = "ti,omap3430-timer", }, 148 { .compatible = "ti,omap4430-timer", }, 149 { .compatible = "ti,omap5430-timer", }, 150 { .compatible = "ti,dm814-timer", }, 151 { .compatible = "ti,dm816-timer", }, 152 { .compatible = "ti,am335x-timer", }, 153 { .compatible = "ti,am335x-timer-1ms", }, 154 { } 155 }; 156 157 /** 158 * omap_get_timer_dt - get a timer using device-tree 159 * @match - device-tree match structure for matching a device type 160 * @property - optional timer property to match 161 * 162 * Helper function to get a timer during early boot using device-tree for use 163 * as kernel system timer. Optionally, the property argument can be used to 164 * select a timer with a specific property. Once a timer is found then mark 165 * the timer node in device-tree as disabled, to prevent the kernel from 166 * registering this timer as a platform device and so no one else can use it. 167 */ 168 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, 169 const char *property) 170 { 171 struct device_node *np; 172 173 for_each_matching_node(np, match) { 174 if (!of_device_is_available(np)) 175 continue; 176 177 if (property && !of_get_property(np, property, NULL)) 178 continue; 179 180 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || 181 of_get_property(np, "ti,timer-dsp", NULL) || 182 of_get_property(np, "ti,timer-pwm", NULL) || 183 of_get_property(np, "ti,timer-secure", NULL))) 184 continue; 185 186 of_add_property(np, &device_disabled); 187 return np; 188 } 189 190 return NULL; 191 } 192 193 /** 194 * omap_dmtimer_init - initialisation function when device tree is used 195 * 196 * For secure OMAP3 devices, timers with device type "timer-secure" cannot 197 * be used by the kernel as they are reserved. Therefore, to prevent the 198 * kernel registering these devices remove them dynamically from the device 199 * tree on boot. 200 */ 201 static void __init omap_dmtimer_init(void) 202 { 203 struct device_node *np; 204 205 if (!cpu_is_omap34xx()) 206 return; 207 208 /* If we are a secure device, remove any secure timer nodes */ 209 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { 210 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); 211 if (np) 212 of_node_put(np); 213 } 214 } 215 216 /** 217 * omap_dm_timer_get_errata - get errata flags for a timer 218 * 219 * Get the timer errata flags that are specific to the OMAP device being used. 220 */ 221 static u32 __init omap_dm_timer_get_errata(void) 222 { 223 if (cpu_is_omap24xx()) 224 return 0; 225 226 return OMAP_TIMER_ERRATA_I103_I767; 227 } 228 229 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 230 const char *fck_source, 231 const char *property, 232 const char **timer_name, 233 int posted) 234 { 235 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 236 const char *oh_name = NULL; 237 struct device_node *np; 238 struct omap_hwmod *oh; 239 struct resource irq, mem; 240 struct clk *src; 241 int r = 0; 242 243 if (of_have_populated_dt()) { 244 np = omap_get_timer_dt(omap_timer_match, property); 245 if (!np) 246 return -ENODEV; 247 248 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 249 if (!oh_name) 250 return -ENODEV; 251 252 timer->irq = irq_of_parse_and_map(np, 0); 253 if (!timer->irq) 254 return -ENXIO; 255 256 timer->io_base = of_iomap(np, 0); 257 258 of_node_put(np); 259 } else { 260 if (omap_dm_timer_reserve_systimer(timer->id)) 261 return -ENODEV; 262 263 sprintf(name, "timer%d", timer->id); 264 oh_name = name; 265 } 266 267 oh = omap_hwmod_lookup(oh_name); 268 if (!oh) 269 return -ENODEV; 270 271 *timer_name = oh->name; 272 273 if (!of_have_populated_dt()) { 274 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, 275 &irq); 276 if (r) 277 return -ENXIO; 278 timer->irq = irq.start; 279 280 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, 281 &mem); 282 if (r) 283 return -ENXIO; 284 285 /* Static mapping, never released */ 286 timer->io_base = ioremap(mem.start, mem.end - mem.start); 287 } 288 289 if (!timer->io_base) 290 return -ENXIO; 291 292 /* After the dmtimer is using hwmod these clocks won't be needed */ 293 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); 294 if (IS_ERR(timer->fclk)) 295 return PTR_ERR(timer->fclk); 296 297 src = clk_get(NULL, fck_source); 298 if (IS_ERR(src)) 299 return PTR_ERR(src); 300 301 r = clk_set_parent(timer->fclk, src); 302 if (r < 0) { 303 pr_warn("%s: %s cannot set source\n", __func__, oh->name); 304 clk_put(src); 305 return r; 306 } 307 308 clk_put(src); 309 310 omap_hwmod_setup_one(oh_name); 311 omap_hwmod_enable(oh); 312 __omap_dm_timer_init_regs(timer); 313 314 if (posted) 315 __omap_dm_timer_enable_posted(timer); 316 317 /* Check that the intended posted configuration matches the actual */ 318 if (posted != timer->posted) 319 return -EINVAL; 320 321 timer->rate = clk_get_rate(timer->fclk); 322 timer->reserved = 1; 323 324 return r; 325 } 326 327 static void __init omap2_gp_clockevent_init(int gptimer_id, 328 const char *fck_source, 329 const char *property) 330 { 331 int res; 332 333 clkev.id = gptimer_id; 334 clkev.errata = omap_dm_timer_get_errata(); 335 336 /* 337 * For clock-event timers we never read the timer counter and 338 * so we are not impacted by errata i103 and i767. Therefore, 339 * we can safely ignore this errata for clock-event timers. 340 */ 341 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); 342 343 res = omap_dm_timer_init_one(&clkev, fck_source, property, 344 &clockevent_gpt.name, OMAP_TIMER_POSTED); 345 BUG_ON(res); 346 347 omap2_gp_timer_irq.dev_id = &clkev; 348 setup_irq(clkev.irq, &omap2_gp_timer_irq); 349 350 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 351 352 clockevent_gpt.cpumask = cpu_possible_mask; 353 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); 354 clockevents_config_and_register(&clockevent_gpt, clkev.rate, 355 3, /* Timer internal resynch latency */ 356 0xffffffff); 357 358 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, 359 clkev.rate); 360 } 361 362 /* Clocksource code */ 363 static struct omap_dm_timer clksrc; 364 static bool use_gptimer_clksrc __initdata; 365 366 /* 367 * clocksource 368 */ 369 static cycle_t clocksource_read_cycles(struct clocksource *cs) 370 { 371 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 372 OMAP_TIMER_NONPOSTED); 373 } 374 375 static struct clocksource clocksource_gpt = { 376 .rating = 300, 377 .read = clocksource_read_cycles, 378 .mask = CLOCKSOURCE_MASK(32), 379 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 380 }; 381 382 static u64 notrace dmtimer_read_sched_clock(void) 383 { 384 if (clksrc.reserved) 385 return __omap_dm_timer_read_counter(&clksrc, 386 OMAP_TIMER_NONPOSTED); 387 388 return 0; 389 } 390 391 static const struct of_device_id omap_counter_match[] __initconst = { 392 { .compatible = "ti,omap-counter32k", }, 393 { } 394 }; 395 396 /* Setup free-running counter for clocksource */ 397 static int __init __maybe_unused omap2_sync32k_clocksource_init(void) 398 { 399 int ret; 400 struct device_node *np = NULL; 401 struct omap_hwmod *oh; 402 void __iomem *vbase; 403 const char *oh_name = "counter_32k"; 404 405 /* 406 * If device-tree is present, then search the DT blob 407 * to see if the 32kHz counter is supported. 408 */ 409 if (of_have_populated_dt()) { 410 np = omap_get_timer_dt(omap_counter_match, NULL); 411 if (!np) 412 return -ENODEV; 413 414 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 415 if (!oh_name) 416 return -ENODEV; 417 } 418 419 /* 420 * First check hwmod data is available for sync32k counter 421 */ 422 oh = omap_hwmod_lookup(oh_name); 423 if (!oh || oh->slaves_cnt == 0) 424 return -ENODEV; 425 426 omap_hwmod_setup_one(oh_name); 427 428 if (np) { 429 vbase = of_iomap(np, 0); 430 of_node_put(np); 431 } else { 432 vbase = omap_hwmod_get_mpu_rt_va(oh); 433 } 434 435 if (!vbase) { 436 pr_warn("%s: failed to get counter_32k resource\n", __func__); 437 return -ENXIO; 438 } 439 440 ret = omap_hwmod_enable(oh); 441 if (ret) { 442 pr_warn("%s: failed to enable counter_32k module (%d)\n", 443 __func__, ret); 444 return ret; 445 } 446 447 ret = omap_init_clocksource_32k(vbase); 448 if (ret) { 449 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", 450 __func__, ret); 451 omap_hwmod_idle(oh); 452 } 453 454 return ret; 455 } 456 457 static void __init omap2_gptimer_clocksource_init(int gptimer_id, 458 const char *fck_source, 459 const char *property) 460 { 461 int res; 462 463 clksrc.id = gptimer_id; 464 clksrc.errata = omap_dm_timer_get_errata(); 465 466 res = omap_dm_timer_init_one(&clksrc, fck_source, property, 467 &clocksource_gpt.name, 468 OMAP_TIMER_NONPOSTED); 469 BUG_ON(res); 470 471 __omap_dm_timer_load_start(&clksrc, 472 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 473 OMAP_TIMER_NONPOSTED); 474 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); 475 476 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 477 pr_err("Could not register clocksource %s\n", 478 clocksource_gpt.name); 479 else 480 pr_info("OMAP clocksource: %s at %lu Hz\n", 481 clocksource_gpt.name, clksrc.rate); 482 } 483 484 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 485 /* 486 * The realtime counter also called master counter, is a free-running 487 * counter, which is related to real time. It produces the count used 488 * by the CPU local timer peripherals in the MPU cluster. The timer counts 489 * at a rate of 6.144 MHz. Because the device operates on different clocks 490 * in different power modes, the master counter shifts operation between 491 * clocks, adjusting the increment per clock in hardware accordingly to 492 * maintain a constant count rate. 493 */ 494 static void __init realtime_counter_init(void) 495 { 496 void __iomem *base; 497 static struct clk *sys_clk; 498 unsigned long rate; 499 unsigned int reg; 500 unsigned long long num, den; 501 502 base = ioremap(REALTIME_COUNTER_BASE, SZ_32); 503 if (!base) { 504 pr_err("%s: ioremap failed\n", __func__); 505 return; 506 } 507 sys_clk = clk_get(NULL, "sys_clkin"); 508 if (IS_ERR(sys_clk)) { 509 pr_err("%s: failed to get system clock handle\n", __func__); 510 iounmap(base); 511 return; 512 } 513 514 rate = clk_get_rate(sys_clk); 515 516 if (soc_is_dra7xx()) { 517 /* 518 * Errata i856 says the 32.768KHz crystal does not start at 519 * power on, so the CPU falls back to an emulated 32KHz clock 520 * based on sysclk / 610 instead. This causes the master counter 521 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 522 * (OR sysclk * 75 / 244) 523 * 524 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions. 525 * Of course any board built without a populated 32.768KHz 526 * crystal would also need this fix even if the CPU is fixed 527 * later. 528 * 529 * Either case can be detected by using the two speedselect bits 530 * If they are not 0, then the 32.768KHz clock driving the 531 * coarse counter that corrects the fine counter every time it 532 * ticks is actually rate/610 rather than 32.768KHz and we 533 * should compensate to avoid the 570ppm (at 20MHz, much worse 534 * at other rates) too fast system time. 535 */ 536 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); 537 if (reg & DRA7_SPEEDSELECT_MASK) { 538 num = 75; 539 den = 244; 540 goto sysclk1_based; 541 } 542 } 543 544 /* Numerator/denumerator values refer TRM Realtime Counter section */ 545 switch (rate) { 546 case 12000000: 547 num = 64; 548 den = 125; 549 break; 550 case 13000000: 551 num = 768; 552 den = 1625; 553 break; 554 case 19200000: 555 num = 8; 556 den = 25; 557 break; 558 case 20000000: 559 num = 192; 560 den = 625; 561 break; 562 case 26000000: 563 num = 384; 564 den = 1625; 565 break; 566 case 27000000: 567 num = 256; 568 den = 1125; 569 break; 570 case 38400000: 571 default: 572 /* Program it for 38.4 MHz */ 573 num = 4; 574 den = 25; 575 break; 576 } 577 578 sysclk1_based: 579 /* Program numerator and denumerator registers */ 580 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & 581 NUMERATOR_DENUMERATOR_MASK; 582 reg |= num; 583 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); 584 585 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & 586 NUMERATOR_DENUMERATOR_MASK; 587 reg |= den; 588 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 589 590 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); 591 set_cntfreq(); 592 593 iounmap(base); 594 } 595 #else 596 static inline void __init realtime_counter_init(void) 597 {} 598 #endif 599 600 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ 601 clksrc_nr, clksrc_src, clksrc_prop) \ 602 void __init omap##name##_gptimer_timer_init(void) \ 603 { \ 604 omap_clk_init(); \ 605 omap_dmtimer_init(); \ 606 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 607 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ 608 clksrc_prop); \ 609 } 610 611 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ 612 clksrc_nr, clksrc_src, clksrc_prop) \ 613 void __init omap##name##_sync32k_timer_init(void) \ 614 { \ 615 omap_clk_init(); \ 616 omap_dmtimer_init(); \ 617 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 618 /* Enable the use of clocksource="gp_timer" kernel parameter */ \ 619 if (use_gptimer_clksrc) \ 620 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ 621 clksrc_prop); \ 622 else \ 623 omap2_sync32k_clocksource_init(); \ 624 } 625 626 #ifdef CONFIG_ARCH_OMAP2 627 OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon", 628 2, "timer_sys_ck", NULL); 629 #endif /* CONFIG_ARCH_OMAP2 */ 630 631 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) 632 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon", 633 2, "timer_sys_ck", NULL); 634 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", 635 2, "timer_sys_ck", NULL); 636 #endif /* CONFIG_ARCH_OMAP3 */ 637 638 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \ 639 defined(CONFIG_SOC_AM43XX) 640 OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, 641 1, "timer_sys_ck", "ti,timer-alwon"); 642 #endif 643 644 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 645 defined(CONFIG_SOC_DRA7XX) 646 static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", 647 2, "sys_clkin_ck", NULL); 648 #endif 649 650 #ifdef CONFIG_ARCH_OMAP4 651 #ifdef CONFIG_HAVE_ARM_TWD 652 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); 653 void __init omap4_local_timer_init(void) 654 { 655 omap4_sync32k_timer_init(); 656 /* Local timers are not supprted on OMAP4430 ES1.0 */ 657 if (omap_rev() != OMAP4430_REV_ES1_0) { 658 int err; 659 660 if (of_have_populated_dt()) { 661 clocksource_of_init(); 662 return; 663 } 664 665 err = twd_local_timer_register(&twd_local_timer); 666 if (err) 667 pr_err("twd_local_timer_register failed %d\n", err); 668 } 669 } 670 #else 671 void __init omap4_local_timer_init(void) 672 { 673 omap4_sync32k_timer_init(); 674 } 675 #endif /* CONFIG_HAVE_ARM_TWD */ 676 #endif /* CONFIG_ARCH_OMAP4 */ 677 678 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 679 void __init omap5_realtime_timer_init(void) 680 { 681 omap4_sync32k_timer_init(); 682 realtime_counter_init(); 683 684 clocksource_of_init(); 685 } 686 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ 687 688 /** 689 * omap_timer_init - build and register timer device with an 690 * associated timer hwmod 691 * @oh: timer hwmod pointer to be used to build timer device 692 * @user: parameter that can be passed from calling hwmod API 693 * 694 * Called by omap_hwmod_for_each_by_class to register each of the timer 695 * devices present in the system. The number of timer devices is known 696 * by parsing through the hwmod database for a given class name. At the 697 * end of function call memory is allocated for timer device and it is 698 * registered to the framework ready to be proved by the driver. 699 */ 700 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) 701 { 702 int id; 703 int ret = 0; 704 char *name = "omap_timer"; 705 struct dmtimer_platform_data *pdata; 706 struct platform_device *pdev; 707 struct omap_timer_capability_dev_attr *timer_dev_attr; 708 709 pr_debug("%s: %s\n", __func__, oh->name); 710 711 /* on secure device, do not register secure timer */ 712 timer_dev_attr = oh->dev_attr; 713 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) 714 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) 715 return ret; 716 717 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 718 if (!pdata) { 719 pr_err("%s: No memory for [%s]\n", __func__, oh->name); 720 return -ENOMEM; 721 } 722 723 /* 724 * Extract the IDs from name field in hwmod database 725 * and use the same for constructing ids' for the 726 * timer devices. In a way, we are avoiding usage of 727 * static variable witin the function to do the same. 728 * CAUTION: We have to be careful and make sure the 729 * name in hwmod database does not change in which case 730 * we might either make corresponding change here or 731 * switch back static variable mechanism. 732 */ 733 sscanf(oh->name, "timer%2d", &id); 734 735 if (timer_dev_attr) 736 pdata->timer_capability = timer_dev_attr->timer_capability; 737 738 pdata->timer_errata = omap_dm_timer_get_errata(); 739 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 740 741 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata)); 742 743 if (IS_ERR(pdev)) { 744 pr_err("%s: Can't build omap_device for %s: %s.\n", 745 __func__, name, oh->name); 746 ret = -EINVAL; 747 } 748 749 kfree(pdata); 750 751 return ret; 752 } 753 754 /** 755 * omap2_dm_timer_init - top level regular device initialization 756 * 757 * Uses dedicated hwmod api to parse through hwmod database for 758 * given class name and then build and register the timer device. 759 */ 760 static int __init omap2_dm_timer_init(void) 761 { 762 int ret; 763 764 /* If dtb is there, the devices will be created dynamically */ 765 if (of_have_populated_dt()) 766 return -ENODEV; 767 768 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); 769 if (unlikely(ret)) { 770 pr_err("%s: device registration failed.\n", __func__); 771 return -EINVAL; 772 } 773 774 return 0; 775 } 776 omap_arch_initcall(omap2_dm_timer_init); 777 778 /** 779 * omap2_override_clocksource - clocksource override with user configuration 780 * 781 * Allows user to override default clocksource, using kernel parameter 782 * clocksource="gp_timer" (For all OMAP2PLUS architectures) 783 * 784 * Note that, here we are using same standard kernel parameter "clocksource=", 785 * and not introducing any OMAP specific interface. 786 */ 787 static int __init omap2_override_clocksource(char *str) 788 { 789 if (!str) 790 return 0; 791 /* 792 * For OMAP architecture, we only have two options 793 * - sync_32k (default) 794 * - gp_timer (sys_clk based) 795 */ 796 if (!strcmp(str, "gp_timer")) 797 use_gptimer_clksrc = true; 798 799 return 0; 800 } 801 early_param("clocksource", omap2_override_clocksource); 802