1 /* 2 * linux/arch/arm/mach-omap2/timer.c 3 * 4 * OMAP2 GP timer support. 5 * 6 * Copyright (C) 2009 Nokia Corporation 7 * 8 * Update to use new clocksource/clockevent layers 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 10 * Copyright (C) 2007 MontaVista Software, Inc. 11 * 12 * Original driver: 13 * Copyright (C) 2005 Nokia Corporation 14 * Author: Paul Mundt <paul.mundt@nokia.com> 15 * Juha Yrjölä <juha.yrjola@nokia.com> 16 * OMAP Dual-mode timer framework support by Timo Teras 17 * 18 * Some parts based off of TI's 24xx code: 19 * 20 * Copyright (C) 2004-2009 Texas Instruments, Inc. 21 * 22 * Roughly modelled after the OMAP1 MPU timer code. 23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 24 * 25 * This file is subject to the terms and conditions of the GNU General Public 26 * License. See the file "COPYING" in the main directory of this archive 27 * for more details. 28 */ 29 #include <linux/init.h> 30 #include <linux/time.h> 31 #include <linux/interrupt.h> 32 #include <linux/err.h> 33 #include <linux/clk.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/clocksource.h> 37 #include <linux/clockchips.h> 38 #include <linux/slab.h> 39 #include <linux/of.h> 40 #include <linux/of_address.h> 41 #include <linux/of_irq.h> 42 #include <linux/platform_device.h> 43 #include <linux/platform_data/dmtimer-omap.h> 44 #include <linux/sched_clock.h> 45 46 #include <asm/mach/time.h> 47 #include <asm/smp_twd.h> 48 49 #include "omap_hwmod.h" 50 #include "omap_device.h" 51 #include <plat/counter-32k.h> 52 #include <plat/dmtimer.h> 53 #include "omap-pm.h" 54 55 #include "soc.h" 56 #include "common.h" 57 #include "control.h" 58 #include "powerdomain.h" 59 #include "omap-secure.h" 60 61 #define REALTIME_COUNTER_BASE 0x48243200 62 #define INCREMENTER_NUMERATOR_OFFSET 0x10 63 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 64 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 65 66 /* Clockevent code */ 67 68 static struct omap_dm_timer clkev; 69 static struct clock_event_device clockevent_gpt; 70 71 /* Clockevent hwmod for am335x and am437x suspend */ 72 static struct omap_hwmod *clockevent_gpt_hwmod; 73 74 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 75 static unsigned long arch_timer_freq; 76 77 void set_cntfreq(void) 78 { 79 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); 80 } 81 #endif 82 83 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 84 { 85 struct clock_event_device *evt = &clockevent_gpt; 86 87 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); 88 89 evt->event_handler(evt); 90 return IRQ_HANDLED; 91 } 92 93 static struct irqaction omap2_gp_timer_irq = { 94 .name = "gp_timer", 95 .flags = IRQF_TIMER | IRQF_IRQPOLL, 96 .handler = omap2_gp_timer_interrupt, 97 }; 98 99 static int omap2_gp_timer_set_next_event(unsigned long cycles, 100 struct clock_event_device *evt) 101 { 102 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 103 0xffffffff - cycles, OMAP_TIMER_POSTED); 104 105 return 0; 106 } 107 108 static int omap2_gp_timer_shutdown(struct clock_event_device *evt) 109 { 110 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); 111 return 0; 112 } 113 114 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt) 115 { 116 u32 period; 117 118 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); 119 120 period = clkev.rate / HZ; 121 period -= 1; 122 /* Looks like we need to first set the load value separately */ 123 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period, 124 OMAP_TIMER_POSTED); 125 __omap_dm_timer_load_start(&clkev, 126 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 127 0xffffffff - period, OMAP_TIMER_POSTED); 128 return 0; 129 } 130 131 static void omap_clkevt_idle(struct clock_event_device *unused) 132 { 133 if (!clockevent_gpt_hwmod) 134 return; 135 136 omap_hwmod_idle(clockevent_gpt_hwmod); 137 } 138 139 static void omap_clkevt_unidle(struct clock_event_device *unused) 140 { 141 if (!clockevent_gpt_hwmod) 142 return; 143 144 omap_hwmod_enable(clockevent_gpt_hwmod); 145 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 146 } 147 148 static struct clock_event_device clockevent_gpt = { 149 .features = CLOCK_EVT_FEAT_PERIODIC | 150 CLOCK_EVT_FEAT_ONESHOT, 151 .rating = 300, 152 .set_next_event = omap2_gp_timer_set_next_event, 153 .set_state_shutdown = omap2_gp_timer_shutdown, 154 .set_state_periodic = omap2_gp_timer_set_periodic, 155 .set_state_oneshot = omap2_gp_timer_shutdown, 156 .tick_resume = omap2_gp_timer_shutdown, 157 }; 158 159 static struct property device_disabled = { 160 .name = "status", 161 .length = sizeof("disabled"), 162 .value = "disabled", 163 }; 164 165 static const struct of_device_id omap_timer_match[] __initconst = { 166 { .compatible = "ti,omap2420-timer", }, 167 { .compatible = "ti,omap3430-timer", }, 168 { .compatible = "ti,omap4430-timer", }, 169 { .compatible = "ti,omap5430-timer", }, 170 { .compatible = "ti,dm814-timer", }, 171 { .compatible = "ti,dm816-timer", }, 172 { .compatible = "ti,am335x-timer", }, 173 { .compatible = "ti,am335x-timer-1ms", }, 174 { } 175 }; 176 177 /** 178 * omap_get_timer_dt - get a timer using device-tree 179 * @match - device-tree match structure for matching a device type 180 * @property - optional timer property to match 181 * 182 * Helper function to get a timer during early boot using device-tree for use 183 * as kernel system timer. Optionally, the property argument can be used to 184 * select a timer with a specific property. Once a timer is found then mark 185 * the timer node in device-tree as disabled, to prevent the kernel from 186 * registering this timer as a platform device and so no one else can use it. 187 */ 188 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, 189 const char *property) 190 { 191 struct device_node *np; 192 193 for_each_matching_node(np, match) { 194 if (!of_device_is_available(np)) 195 continue; 196 197 if (property && !of_get_property(np, property, NULL)) 198 continue; 199 200 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || 201 of_get_property(np, "ti,timer-dsp", NULL) || 202 of_get_property(np, "ti,timer-pwm", NULL) || 203 of_get_property(np, "ti,timer-secure", NULL))) 204 continue; 205 206 if (!of_device_is_compatible(np, "ti,omap-counter32k")) 207 of_add_property(np, &device_disabled); 208 return np; 209 } 210 211 return NULL; 212 } 213 214 /** 215 * omap_dmtimer_init - initialisation function when device tree is used 216 * 217 * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure" 218 * cannot be used by the kernel as they are reserved. Therefore, to prevent the 219 * kernel registering these devices remove them dynamically from the device 220 * tree on boot. 221 */ 222 static void __init omap_dmtimer_init(void) 223 { 224 struct device_node *np; 225 226 if (!cpu_is_omap34xx() && !soc_is_dra7xx()) 227 return; 228 229 /* If we are a secure device, remove any secure timer nodes */ 230 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { 231 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); 232 of_node_put(np); 233 } 234 } 235 236 /** 237 * omap_dm_timer_get_errata - get errata flags for a timer 238 * 239 * Get the timer errata flags that are specific to the OMAP device being used. 240 */ 241 static u32 __init omap_dm_timer_get_errata(void) 242 { 243 if (cpu_is_omap24xx()) 244 return 0; 245 246 return OMAP_TIMER_ERRATA_I103_I767; 247 } 248 249 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 250 const char *fck_source, 251 const char *property, 252 const char **timer_name, 253 int posted) 254 { 255 const char *oh_name = NULL; 256 struct device_node *np; 257 struct omap_hwmod *oh; 258 struct clk *src; 259 int r = 0; 260 261 np = omap_get_timer_dt(omap_timer_match, property); 262 if (!np) 263 return -ENODEV; 264 265 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 266 if (!oh_name) 267 return -ENODEV; 268 269 timer->irq = irq_of_parse_and_map(np, 0); 270 if (!timer->irq) 271 return -ENXIO; 272 273 timer->io_base = of_iomap(np, 0); 274 275 timer->fclk = of_clk_get_by_name(np, "fck"); 276 277 of_node_put(np); 278 279 oh = omap_hwmod_lookup(oh_name); 280 if (!oh) 281 return -ENODEV; 282 283 *timer_name = oh->name; 284 285 if (!timer->io_base) 286 return -ENXIO; 287 288 omap_hwmod_setup_one(oh_name); 289 290 /* After the dmtimer is using hwmod these clocks won't be needed */ 291 if (IS_ERR_OR_NULL(timer->fclk)) 292 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); 293 if (IS_ERR(timer->fclk)) 294 return PTR_ERR(timer->fclk); 295 296 src = clk_get(NULL, fck_source); 297 if (IS_ERR(src)) 298 return PTR_ERR(src); 299 300 WARN(clk_set_parent(timer->fclk, src) < 0, 301 "Cannot set timer parent clock, no PLL clock driver?"); 302 303 clk_put(src); 304 305 omap_hwmod_enable(oh); 306 __omap_dm_timer_init_regs(timer); 307 308 if (posted) 309 __omap_dm_timer_enable_posted(timer); 310 311 /* Check that the intended posted configuration matches the actual */ 312 if (posted != timer->posted) 313 return -EINVAL; 314 315 timer->rate = clk_get_rate(timer->fclk); 316 timer->reserved = 1; 317 318 return r; 319 } 320 321 #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) 322 void tick_broadcast(const struct cpumask *mask) 323 { 324 } 325 #endif 326 327 static void __init omap2_gp_clockevent_init(int gptimer_id, 328 const char *fck_source, 329 const char *property) 330 { 331 int res; 332 333 clkev.id = gptimer_id; 334 clkev.errata = omap_dm_timer_get_errata(); 335 336 /* 337 * For clock-event timers we never read the timer counter and 338 * so we are not impacted by errata i103 and i767. Therefore, 339 * we can safely ignore this errata for clock-event timers. 340 */ 341 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); 342 343 res = omap_dm_timer_init_one(&clkev, fck_source, property, 344 &clockevent_gpt.name, OMAP_TIMER_POSTED); 345 BUG_ON(res); 346 347 omap2_gp_timer_irq.dev_id = &clkev; 348 setup_irq(clkev.irq, &omap2_gp_timer_irq); 349 350 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 351 352 clockevent_gpt.cpumask = cpu_possible_mask; 353 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); 354 clockevents_config_and_register(&clockevent_gpt, clkev.rate, 355 3, /* Timer internal resynch latency */ 356 0xffffffff); 357 358 if (soc_is_am33xx() || soc_is_am43xx()) { 359 clockevent_gpt.suspend = omap_clkevt_idle; 360 clockevent_gpt.resume = omap_clkevt_unidle; 361 362 clockevent_gpt_hwmod = 363 omap_hwmod_lookup(clockevent_gpt.name); 364 } 365 366 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, 367 clkev.rate); 368 } 369 370 /* Clocksource code */ 371 static struct omap_dm_timer clksrc; 372 static bool use_gptimer_clksrc __initdata; 373 374 /* 375 * clocksource 376 */ 377 static u64 clocksource_read_cycles(struct clocksource *cs) 378 { 379 return (u64)__omap_dm_timer_read_counter(&clksrc, 380 OMAP_TIMER_NONPOSTED); 381 } 382 383 static struct clocksource clocksource_gpt = { 384 .rating = 300, 385 .read = clocksource_read_cycles, 386 .mask = CLOCKSOURCE_MASK(32), 387 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 388 }; 389 390 static u64 notrace dmtimer_read_sched_clock(void) 391 { 392 if (clksrc.reserved) 393 return __omap_dm_timer_read_counter(&clksrc, 394 OMAP_TIMER_NONPOSTED); 395 396 return 0; 397 } 398 399 static const struct of_device_id omap_counter_match[] __initconst = { 400 { .compatible = "ti,omap-counter32k", }, 401 { } 402 }; 403 404 /* Setup free-running counter for clocksource */ 405 static int __init __maybe_unused omap2_sync32k_clocksource_init(void) 406 { 407 int ret; 408 struct device_node *np = NULL; 409 struct omap_hwmod *oh; 410 const char *oh_name = "counter_32k"; 411 412 /* 413 * See if the 32kHz counter is supported. 414 */ 415 np = omap_get_timer_dt(omap_counter_match, NULL); 416 if (!np) 417 return -ENODEV; 418 419 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 420 if (!oh_name) 421 return -ENODEV; 422 423 /* 424 * First check hwmod data is available for sync32k counter 425 */ 426 oh = omap_hwmod_lookup(oh_name); 427 if (!oh || oh->slaves_cnt == 0) 428 return -ENODEV; 429 430 omap_hwmod_setup_one(oh_name); 431 432 ret = omap_hwmod_enable(oh); 433 if (ret) { 434 pr_warn("%s: failed to enable counter_32k module (%d)\n", 435 __func__, ret); 436 return ret; 437 } 438 439 return ret; 440 } 441 442 static void __init omap2_gptimer_clocksource_init(int gptimer_id, 443 const char *fck_source, 444 const char *property) 445 { 446 int res; 447 448 clksrc.id = gptimer_id; 449 clksrc.errata = omap_dm_timer_get_errata(); 450 451 res = omap_dm_timer_init_one(&clksrc, fck_source, property, 452 &clocksource_gpt.name, 453 OMAP_TIMER_NONPOSTED); 454 BUG_ON(res); 455 456 __omap_dm_timer_load_start(&clksrc, 457 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 458 OMAP_TIMER_NONPOSTED); 459 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); 460 461 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 462 pr_err("Could not register clocksource %s\n", 463 clocksource_gpt.name); 464 else 465 pr_info("OMAP clocksource: %s at %lu Hz\n", 466 clocksource_gpt.name, clksrc.rate); 467 } 468 469 static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src, 470 const char *clkev_prop, int clksrc_nr, const char *clksrc_src, 471 const char *clksrc_prop, bool gptimer) 472 { 473 omap_clk_init(); 474 omap_dmtimer_init(); 475 omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop); 476 477 /* Enable the use of clocksource="gp_timer" kernel parameter */ 478 if (use_gptimer_clksrc || gptimer) 479 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src, 480 clksrc_prop); 481 else 482 omap2_sync32k_clocksource_init(); 483 } 484 485 void __init omap_init_time(void) 486 { 487 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", 488 2, "timer_sys_ck", NULL, false); 489 490 timer_probe(); 491 } 492 493 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) 494 void __init omap3_secure_sync32k_timer_init(void) 495 { 496 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure", 497 2, "timer_sys_ck", NULL, false); 498 499 timer_probe(); 500 } 501 #endif /* CONFIG_ARCH_OMAP3 */ 502 503 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \ 504 defined(CONFIG_SOC_AM43XX) 505 void __init omap3_gptimer_timer_init(void) 506 { 507 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL, 508 1, "timer_sys_ck", "ti,timer-alwon", true); 509 if (of_have_populated_dt()) 510 timer_probe(); 511 } 512 #endif 513 514 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 515 defined(CONFIG_SOC_DRA7XX) 516 static void __init omap4_sync32k_timer_init(void) 517 { 518 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon", 519 2, "sys_clkin_ck", NULL, false); 520 } 521 522 void __init omap4_local_timer_init(void) 523 { 524 omap4_sync32k_timer_init(); 525 timer_probe(); 526 } 527 #endif 528 529 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 530 531 /* 532 * The realtime counter also called master counter, is a free-running 533 * counter, which is related to real time. It produces the count used 534 * by the CPU local timer peripherals in the MPU cluster. The timer counts 535 * at a rate of 6.144 MHz. Because the device operates on different clocks 536 * in different power modes, the master counter shifts operation between 537 * clocks, adjusting the increment per clock in hardware accordingly to 538 * maintain a constant count rate. 539 */ 540 static void __init realtime_counter_init(void) 541 { 542 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 543 void __iomem *base; 544 static struct clk *sys_clk; 545 unsigned long rate; 546 unsigned int reg; 547 unsigned long long num, den; 548 549 base = ioremap(REALTIME_COUNTER_BASE, SZ_32); 550 if (!base) { 551 pr_err("%s: ioremap failed\n", __func__); 552 return; 553 } 554 sys_clk = clk_get(NULL, "sys_clkin"); 555 if (IS_ERR(sys_clk)) { 556 pr_err("%s: failed to get system clock handle\n", __func__); 557 iounmap(base); 558 return; 559 } 560 561 rate = clk_get_rate(sys_clk); 562 563 if (soc_is_dra7xx()) { 564 /* 565 * Errata i856 says the 32.768KHz crystal does not start at 566 * power on, so the CPU falls back to an emulated 32KHz clock 567 * based on sysclk / 610 instead. This causes the master counter 568 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 569 * (OR sysclk * 75 / 244) 570 * 571 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions. 572 * Of course any board built without a populated 32.768KHz 573 * crystal would also need this fix even if the CPU is fixed 574 * later. 575 * 576 * Either case can be detected by using the two speedselect bits 577 * If they are not 0, then the 32.768KHz clock driving the 578 * coarse counter that corrects the fine counter every time it 579 * ticks is actually rate/610 rather than 32.768KHz and we 580 * should compensate to avoid the 570ppm (at 20MHz, much worse 581 * at other rates) too fast system time. 582 */ 583 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); 584 if (reg & DRA7_SPEEDSELECT_MASK) { 585 num = 75; 586 den = 244; 587 goto sysclk1_based; 588 } 589 } 590 591 /* Numerator/denumerator values refer TRM Realtime Counter section */ 592 switch (rate) { 593 case 12000000: 594 num = 64; 595 den = 125; 596 break; 597 case 13000000: 598 num = 768; 599 den = 1625; 600 break; 601 case 19200000: 602 num = 8; 603 den = 25; 604 break; 605 case 20000000: 606 num = 192; 607 den = 625; 608 break; 609 case 26000000: 610 num = 384; 611 den = 1625; 612 break; 613 case 27000000: 614 num = 256; 615 den = 1125; 616 break; 617 case 38400000: 618 default: 619 /* Program it for 38.4 MHz */ 620 num = 4; 621 den = 25; 622 break; 623 } 624 625 sysclk1_based: 626 /* Program numerator and denumerator registers */ 627 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & 628 NUMERATOR_DENUMERATOR_MASK; 629 reg |= num; 630 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); 631 632 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & 633 NUMERATOR_DENUMERATOR_MASK; 634 reg |= den; 635 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 636 637 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); 638 set_cntfreq(); 639 640 iounmap(base); 641 #endif 642 } 643 644 void __init omap5_realtime_timer_init(void) 645 { 646 omap4_sync32k_timer_init(); 647 realtime_counter_init(); 648 649 timer_probe(); 650 } 651 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ 652 653 /** 654 * omap2_override_clocksource - clocksource override with user configuration 655 * 656 * Allows user to override default clocksource, using kernel parameter 657 * clocksource="gp_timer" (For all OMAP2PLUS architectures) 658 * 659 * Note that, here we are using same standard kernel parameter "clocksource=", 660 * and not introducing any OMAP specific interface. 661 */ 662 static int __init omap2_override_clocksource(char *str) 663 { 664 if (!str) 665 return 0; 666 /* 667 * For OMAP architecture, we only have two options 668 * - sync_32k (default) 669 * - gp_timer (sys_clk based) 670 */ 671 if (!strcmp(str, "gp_timer")) 672 use_gptimer_clksrc = true; 673 674 return 0; 675 } 676 early_param("clocksource", omap2_override_clocksource); 677