xref: /openbmc/linux/arch/arm/mach-omap2/timer.c (revision 95e9fd10) 
1 /*
2  * linux/arch/arm/mach-omap2/timer.c
3  *
4  * OMAP2 GP timer support.
5  *
6  * Copyright (C) 2009 Nokia Corporation
7  *
8  * Update to use new clocksource/clockevent layers
9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10  * Copyright (C) 2007 MontaVista Software, Inc.
11  *
12  * Original driver:
13  * Copyright (C) 2005 Nokia Corporation
14  * Author: Paul Mundt <paul.mundt@nokia.com>
15  *         Juha Yrjölä <juha.yrjola@nokia.com>
16  * OMAP Dual-mode timer framework support by Timo Teras
17  *
18  * Some parts based off of TI's 24xx code:
19  *
20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
21  *
22  * Roughly modelled after the OMAP1 MPU timer code.
23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24  *
25  * This file is subject to the terms and conditions of the GNU General Public
26  * License. See the file "COPYING" in the main directory of this archive
27  * for more details.
28  */
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
39 
40 #include <asm/mach/time.h>
41 #include <plat/dmtimer.h>
42 #include <asm/smp_twd.h>
43 #include <asm/sched_clock.h>
44 #include "common.h"
45 #include <plat/omap_hwmod.h>
46 #include <plat/omap_device.h>
47 #include <plat/omap-pm.h>
48 
49 #include "powerdomain.h"
50 
51 /* Parent clocks, eventually these will come from the clock framework */
52 
53 #define OMAP2_MPU_SOURCE	"sys_ck"
54 #define OMAP3_MPU_SOURCE	OMAP2_MPU_SOURCE
55 #define OMAP4_MPU_SOURCE	"sys_clkin_ck"
56 #define OMAP2_32K_SOURCE	"func_32k_ck"
57 #define OMAP3_32K_SOURCE	"omap_32k_fck"
58 #define OMAP4_32K_SOURCE	"sys_32k_ck"
59 
60 #ifdef CONFIG_OMAP_32K_TIMER
61 #define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
62 #define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
63 #define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
64 #define OMAP3_SECURE_TIMER	12
65 #else
66 #define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
67 #define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
68 #define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
69 #define OMAP3_SECURE_TIMER	1
70 #endif
71 
72 /* Clockevent code */
73 
74 static struct omap_dm_timer clkev;
75 static struct clock_event_device clockevent_gpt;
76 
77 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
78 {
79 	struct clock_event_device *evt = &clockevent_gpt;
80 
81 	__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
82 
83 	evt->event_handler(evt);
84 	return IRQ_HANDLED;
85 }
86 
87 static struct irqaction omap2_gp_timer_irq = {
88 	.name		= "gp_timer",
89 	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
90 	.handler	= omap2_gp_timer_interrupt,
91 };
92 
93 static int omap2_gp_timer_set_next_event(unsigned long cycles,
94 					 struct clock_event_device *evt)
95 {
96 	__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
97 						0xffffffff - cycles, 1);
98 
99 	return 0;
100 }
101 
102 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
103 				    struct clock_event_device *evt)
104 {
105 	u32 period;
106 
107 	__omap_dm_timer_stop(&clkev, 1, clkev.rate);
108 
109 	switch (mode) {
110 	case CLOCK_EVT_MODE_PERIODIC:
111 		period = clkev.rate / HZ;
112 		period -= 1;
113 		/* Looks like we need to first set the load value separately */
114 		__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
115 					0xffffffff - period, 1);
116 		__omap_dm_timer_load_start(&clkev,
117 					OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
118 						0xffffffff - period, 1);
119 		break;
120 	case CLOCK_EVT_MODE_ONESHOT:
121 		break;
122 	case CLOCK_EVT_MODE_UNUSED:
123 	case CLOCK_EVT_MODE_SHUTDOWN:
124 	case CLOCK_EVT_MODE_RESUME:
125 		break;
126 	}
127 }
128 
129 static struct clock_event_device clockevent_gpt = {
130 	.name		= "gp_timer",
131 	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
132 	.shift		= 32,
133 	.rating		= 300,
134 	.set_next_event	= omap2_gp_timer_set_next_event,
135 	.set_mode	= omap2_gp_timer_set_mode,
136 };
137 
138 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
139 						int gptimer_id,
140 						const char *fck_source)
141 {
142 	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
143 	struct omap_hwmod *oh;
144 	struct resource irq_rsrc, mem_rsrc;
145 	size_t size;
146 	int res = 0;
147 	int r;
148 
149 	sprintf(name, "timer%d", gptimer_id);
150 	omap_hwmod_setup_one(name);
151 	oh = omap_hwmod_lookup(name);
152 	if (!oh)
153 		return -ENODEV;
154 
155 	r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
156 	if (r)
157 		return -ENXIO;
158 	timer->irq = irq_rsrc.start;
159 
160 	r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
161 	if (r)
162 		return -ENXIO;
163 	timer->phys_base = mem_rsrc.start;
164 	size = mem_rsrc.end - mem_rsrc.start;
165 
166 	/* Static mapping, never released */
167 	timer->io_base = ioremap(timer->phys_base, size);
168 	if (!timer->io_base)
169 		return -ENXIO;
170 
171 	/* After the dmtimer is using hwmod these clocks won't be needed */
172 	timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
173 	if (IS_ERR(timer->fclk))
174 		return -ENODEV;
175 
176 	omap_hwmod_enable(oh);
177 
178 	if (omap_dm_timer_reserve_systimer(gptimer_id))
179 		return -ENODEV;
180 
181 	if (gptimer_id != 12) {
182 		struct clk *src;
183 
184 		src = clk_get(NULL, fck_source);
185 		if (IS_ERR(src)) {
186 			res = -EINVAL;
187 		} else {
188 			res = __omap_dm_timer_set_source(timer->fclk, src);
189 			if (IS_ERR_VALUE(res))
190 				pr_warning("%s: timer%i cannot set source\n",
191 						__func__, gptimer_id);
192 			clk_put(src);
193 		}
194 	}
195 	__omap_dm_timer_init_regs(timer);
196 	__omap_dm_timer_reset(timer, 1, 1);
197 	timer->posted = 1;
198 
199 	timer->rate = clk_get_rate(timer->fclk);
200 
201 	timer->reserved = 1;
202 
203 	return res;
204 }
205 
206 static void __init omap2_gp_clockevent_init(int gptimer_id,
207 						const char *fck_source)
208 {
209 	int res;
210 
211 	res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
212 	BUG_ON(res);
213 
214 	omap2_gp_timer_irq.dev_id = (void *)&clkev;
215 	setup_irq(clkev.irq, &omap2_gp_timer_irq);
216 
217 	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
218 
219 	clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
220 				     clockevent_gpt.shift);
221 	clockevent_gpt.max_delta_ns =
222 		clockevent_delta2ns(0xffffffff, &clockevent_gpt);
223 	clockevent_gpt.min_delta_ns =
224 		clockevent_delta2ns(3, &clockevent_gpt);
225 		/* Timer internal resynch latency. */
226 
227 	clockevent_gpt.cpumask = cpu_possible_mask;
228 	clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
229 	clockevents_register_device(&clockevent_gpt);
230 
231 	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
232 		gptimer_id, clkev.rate);
233 }
234 
235 /* Clocksource code */
236 static struct omap_dm_timer clksrc;
237 static bool use_gptimer_clksrc;
238 
239 /*
240  * clocksource
241  */
242 static cycle_t clocksource_read_cycles(struct clocksource *cs)
243 {
244 	return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
245 }
246 
247 static struct clocksource clocksource_gpt = {
248 	.name		= "gp_timer",
249 	.rating		= 300,
250 	.read		= clocksource_read_cycles,
251 	.mask		= CLOCKSOURCE_MASK(32),
252 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
253 };
254 
255 static u32 notrace dmtimer_read_sched_clock(void)
256 {
257 	if (clksrc.reserved)
258 		return __omap_dm_timer_read_counter(&clksrc, 1);
259 
260 	return 0;
261 }
262 
263 /* Setup free-running counter for clocksource */
264 static int __init omap2_sync32k_clocksource_init(void)
265 {
266 	int ret;
267 	struct omap_hwmod *oh;
268 	void __iomem *vbase;
269 	const char *oh_name = "counter_32k";
270 
271 	/*
272 	 * First check hwmod data is available for sync32k counter
273 	 */
274 	oh = omap_hwmod_lookup(oh_name);
275 	if (!oh || oh->slaves_cnt == 0)
276 		return -ENODEV;
277 
278 	omap_hwmod_setup_one(oh_name);
279 
280 	vbase = omap_hwmod_get_mpu_rt_va(oh);
281 	if (!vbase) {
282 		pr_warn("%s: failed to get counter_32k resource\n", __func__);
283 		return -ENXIO;
284 	}
285 
286 	ret = omap_hwmod_enable(oh);
287 	if (ret) {
288 		pr_warn("%s: failed to enable counter_32k module (%d)\n",
289 							__func__, ret);
290 		return ret;
291 	}
292 
293 	ret = omap_init_clocksource_32k(vbase);
294 	if (ret) {
295 		pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
296 							__func__, ret);
297 		omap_hwmod_idle(oh);
298 	}
299 
300 	return ret;
301 }
302 
303 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
304 						const char *fck_source)
305 {
306 	int res;
307 
308 	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
309 	BUG_ON(res);
310 
311 	__omap_dm_timer_load_start(&clksrc,
312 			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
313 	setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
314 
315 	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
316 		pr_err("Could not register clocksource %s\n",
317 			clocksource_gpt.name);
318 	else
319 		pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
320 			gptimer_id, clksrc.rate);
321 }
322 
323 static void __init omap2_clocksource_init(int gptimer_id,
324 						const char *fck_source)
325 {
326 	/*
327 	 * First give preference to kernel parameter configuration
328 	 * by user (clocksource="gp_timer").
329 	 *
330 	 * In case of missing kernel parameter for clocksource,
331 	 * first check for availability for 32k-sync timer, in case
332 	 * of failure in finding 32k_counter module or registering
333 	 * it as clocksource, execution will fallback to gp-timer.
334 	 */
335 	if (use_gptimer_clksrc == true)
336 		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
337 	else if (omap2_sync32k_clocksource_init())
338 		/* Fall back to gp-timer code */
339 		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
340 }
341 
342 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
343 				clksrc_nr, clksrc_src)			\
344 static void __init omap##name##_timer_init(void)			\
345 {									\
346 	omap2_gp_clockevent_init((clkev_nr), clkev_src);		\
347 	omap2_clocksource_init((clksrc_nr), clksrc_src);		\
348 }
349 
350 #define OMAP_SYS_TIMER(name)						\
351 struct sys_timer omap##name##_timer = {					\
352 	.init	= omap##name##_timer_init,				\
353 };
354 
355 #ifdef CONFIG_ARCH_OMAP2
356 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
357 OMAP_SYS_TIMER(2)
358 #endif
359 
360 #ifdef CONFIG_ARCH_OMAP3
361 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
362 OMAP_SYS_TIMER(3)
363 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
364 			2, OMAP3_MPU_SOURCE)
365 OMAP_SYS_TIMER(3_secure)
366 #endif
367 
368 #ifdef CONFIG_SOC_AM33XX
369 OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
370 OMAP_SYS_TIMER(3_am33xx)
371 #endif
372 
373 #ifdef CONFIG_ARCH_OMAP4
374 #ifdef CONFIG_LOCAL_TIMERS
375 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
376 			      OMAP44XX_LOCAL_TWD_BASE,
377 			      OMAP44XX_IRQ_LOCALTIMER);
378 #endif
379 
380 static void __init omap4_timer_init(void)
381 {
382 	omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
383 	omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
384 #ifdef CONFIG_LOCAL_TIMERS
385 	/* Local timers are not supprted on OMAP4430 ES1.0 */
386 	if (omap_rev() != OMAP4430_REV_ES1_0) {
387 		int err;
388 
389 		err = twd_local_timer_register(&twd_local_timer);
390 		if (err)
391 			pr_err("twd_local_timer_register failed %d\n", err);
392 	}
393 #endif
394 }
395 OMAP_SYS_TIMER(4)
396 #endif
397 
398 #ifdef CONFIG_SOC_OMAP5
399 OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
400 OMAP_SYS_TIMER(5)
401 #endif
402 
403 /**
404  * omap_timer_init - build and register timer device with an
405  * associated timer hwmod
406  * @oh:	timer hwmod pointer to be used to build timer device
407  * @user:	parameter that can be passed from calling hwmod API
408  *
409  * Called by omap_hwmod_for_each_by_class to register each of the timer
410  * devices present in the system. The number of timer devices is known
411  * by parsing through the hwmod database for a given class name. At the
412  * end of function call memory is allocated for timer device and it is
413  * registered to the framework ready to be proved by the driver.
414  */
415 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
416 {
417 	int id;
418 	int ret = 0;
419 	char *name = "omap_timer";
420 	struct dmtimer_platform_data *pdata;
421 	struct platform_device *pdev;
422 	struct omap_timer_capability_dev_attr *timer_dev_attr;
423 
424 	pr_debug("%s: %s\n", __func__, oh->name);
425 
426 	/* on secure device, do not register secure timer */
427 	timer_dev_attr = oh->dev_attr;
428 	if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
429 		if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
430 			return ret;
431 
432 	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
433 	if (!pdata) {
434 		pr_err("%s: No memory for [%s]\n", __func__, oh->name);
435 		return -ENOMEM;
436 	}
437 
438 	/*
439 	 * Extract the IDs from name field in hwmod database
440 	 * and use the same for constructing ids' for the
441 	 * timer devices. In a way, we are avoiding usage of
442 	 * static variable witin the function to do the same.
443 	 * CAUTION: We have to be careful and make sure the
444 	 * name in hwmod database does not change in which case
445 	 * we might either make corresponding change here or
446 	 * switch back static variable mechanism.
447 	 */
448 	sscanf(oh->name, "timer%2d", &id);
449 
450 	if (timer_dev_attr)
451 		pdata->timer_capability = timer_dev_attr->timer_capability;
452 
453 	pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
454 				 NULL, 0, 0);
455 
456 	if (IS_ERR(pdev)) {
457 		pr_err("%s: Can't build omap_device for %s: %s.\n",
458 			__func__, name, oh->name);
459 		ret = -EINVAL;
460 	}
461 
462 	kfree(pdata);
463 
464 	return ret;
465 }
466 
467 /**
468  * omap2_dm_timer_init - top level regular device initialization
469  *
470  * Uses dedicated hwmod api to parse through hwmod database for
471  * given class name and then build and register the timer device.
472  */
473 static int __init omap2_dm_timer_init(void)
474 {
475 	int ret;
476 
477 	ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
478 	if (unlikely(ret)) {
479 		pr_err("%s: device registration failed.\n", __func__);
480 		return -EINVAL;
481 	}
482 
483 	return 0;
484 }
485 arch_initcall(omap2_dm_timer_init);
486 
487 /**
488  * omap2_override_clocksource - clocksource override with user configuration
489  *
490  * Allows user to override default clocksource, using kernel parameter
491  *   clocksource="gp_timer"	(For all OMAP2PLUS architectures)
492  *
493  * Note that, here we are using same standard kernel parameter "clocksource=",
494  * and not introducing any OMAP specific interface.
495  */
496 static int __init omap2_override_clocksource(char *str)
497 {
498 	if (!str)
499 		return 0;
500 	/*
501 	 * For OMAP architecture, we only have two options
502 	 *    - sync_32k (default)
503 	 *    - gp_timer (sys_clk based)
504 	 */
505 	if (!strcmp(str, "gp_timer"))
506 		use_gptimer_clksrc = true;
507 
508 	return 0;
509 }
510 early_param("clocksource", omap2_override_clocksource);
511