1 /* 2 * linux/arch/arm/mach-omap2/timer.c 3 * 4 * OMAP2 GP timer support. 5 * 6 * Copyright (C) 2009 Nokia Corporation 7 * 8 * Update to use new clocksource/clockevent layers 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 10 * Copyright (C) 2007 MontaVista Software, Inc. 11 * 12 * Original driver: 13 * Copyright (C) 2005 Nokia Corporation 14 * Author: Paul Mundt <paul.mundt@nokia.com> 15 * Juha Yrjölä <juha.yrjola@nokia.com> 16 * OMAP Dual-mode timer framework support by Timo Teras 17 * 18 * Some parts based off of TI's 24xx code: 19 * 20 * Copyright (C) 2004-2009 Texas Instruments, Inc. 21 * 22 * Roughly modelled after the OMAP1 MPU timer code. 23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 24 * 25 * This file is subject to the terms and conditions of the GNU General Public 26 * License. See the file "COPYING" in the main directory of this archive 27 * for more details. 28 */ 29 #include <linux/init.h> 30 #include <linux/time.h> 31 #include <linux/interrupt.h> 32 #include <linux/err.h> 33 #include <linux/clk.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/clocksource.h> 37 #include <linux/clockchips.h> 38 #include <linux/slab.h> 39 #include <linux/of.h> 40 #include <linux/of_address.h> 41 #include <linux/of_irq.h> 42 #include <linux/platform_device.h> 43 #include <linux/platform_data/dmtimer-omap.h> 44 45 #include <asm/mach/time.h> 46 #include <asm/smp_twd.h> 47 #include <asm/sched_clock.h> 48 49 #include <asm/arch_timer.h> 50 #include "omap_hwmod.h" 51 #include "omap_device.h" 52 #include <plat/counter-32k.h> 53 #include <plat/dmtimer.h> 54 #include "omap-pm.h" 55 56 #include "soc.h" 57 #include "common.h" 58 #include "powerdomain.h" 59 60 /* Parent clocks, eventually these will come from the clock framework */ 61 62 #define OMAP2_MPU_SOURCE "sys_ck" 63 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE 64 #define OMAP4_MPU_SOURCE "sys_clkin_ck" 65 #define OMAP2_32K_SOURCE "func_32k_ck" 66 #define OMAP3_32K_SOURCE "omap_32k_fck" 67 #define OMAP4_32K_SOURCE "sys_32k_ck" 68 69 #define REALTIME_COUNTER_BASE 0x48243200 70 #define INCREMENTER_NUMERATOR_OFFSET 0x10 71 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 72 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 73 74 /* Clockevent code */ 75 76 static struct omap_dm_timer clkev; 77 static struct clock_event_device clockevent_gpt; 78 79 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 80 { 81 struct clock_event_device *evt = &clockevent_gpt; 82 83 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); 84 85 evt->event_handler(evt); 86 return IRQ_HANDLED; 87 } 88 89 static struct irqaction omap2_gp_timer_irq = { 90 .name = "gp_timer", 91 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 92 .handler = omap2_gp_timer_interrupt, 93 }; 94 95 static int omap2_gp_timer_set_next_event(unsigned long cycles, 96 struct clock_event_device *evt) 97 { 98 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 99 0xffffffff - cycles, OMAP_TIMER_POSTED); 100 101 return 0; 102 } 103 104 static void omap2_gp_timer_set_mode(enum clock_event_mode mode, 105 struct clock_event_device *evt) 106 { 107 u32 period; 108 109 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); 110 111 switch (mode) { 112 case CLOCK_EVT_MODE_PERIODIC: 113 period = clkev.rate / HZ; 114 period -= 1; 115 /* Looks like we need to first set the load value separately */ 116 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 117 0xffffffff - period, OMAP_TIMER_POSTED); 118 __omap_dm_timer_load_start(&clkev, 119 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 120 0xffffffff - period, OMAP_TIMER_POSTED); 121 break; 122 case CLOCK_EVT_MODE_ONESHOT: 123 break; 124 case CLOCK_EVT_MODE_UNUSED: 125 case CLOCK_EVT_MODE_SHUTDOWN: 126 case CLOCK_EVT_MODE_RESUME: 127 break; 128 } 129 } 130 131 static struct clock_event_device clockevent_gpt = { 132 .name = "gp_timer", 133 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 134 .rating = 300, 135 .set_next_event = omap2_gp_timer_set_next_event, 136 .set_mode = omap2_gp_timer_set_mode, 137 }; 138 139 static struct property device_disabled = { 140 .name = "status", 141 .length = sizeof("disabled"), 142 .value = "disabled", 143 }; 144 145 static struct of_device_id omap_timer_match[] __initdata = { 146 { .compatible = "ti,omap2-timer", }, 147 { } 148 }; 149 150 /** 151 * omap_get_timer_dt - get a timer using device-tree 152 * @match - device-tree match structure for matching a device type 153 * @property - optional timer property to match 154 * 155 * Helper function to get a timer during early boot using device-tree for use 156 * as kernel system timer. Optionally, the property argument can be used to 157 * select a timer with a specific property. Once a timer is found then mark 158 * the timer node in device-tree as disabled, to prevent the kernel from 159 * registering this timer as a platform device and so no one else can use it. 160 */ 161 static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, 162 const char *property) 163 { 164 struct device_node *np; 165 166 for_each_matching_node(np, match) { 167 if (!of_device_is_available(np)) 168 continue; 169 170 if (property && !of_get_property(np, property, NULL)) 171 continue; 172 173 of_add_property(np, &device_disabled); 174 return np; 175 } 176 177 return NULL; 178 } 179 180 /** 181 * omap_dmtimer_init - initialisation function when device tree is used 182 * 183 * For secure OMAP3 devices, timers with device type "timer-secure" cannot 184 * be used by the kernel as they are reserved. Therefore, to prevent the 185 * kernel registering these devices remove them dynamically from the device 186 * tree on boot. 187 */ 188 static void __init omap_dmtimer_init(void) 189 { 190 struct device_node *np; 191 192 if (!cpu_is_omap34xx()) 193 return; 194 195 /* If we are a secure device, remove any secure timer nodes */ 196 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { 197 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); 198 if (np) 199 of_node_put(np); 200 } 201 } 202 203 /** 204 * omap_dm_timer_get_errata - get errata flags for a timer 205 * 206 * Get the timer errata flags that are specific to the OMAP device being used. 207 */ 208 static u32 __init omap_dm_timer_get_errata(void) 209 { 210 if (cpu_is_omap24xx()) 211 return 0; 212 213 return OMAP_TIMER_ERRATA_I103_I767; 214 } 215 216 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 217 int gptimer_id, 218 const char *fck_source, 219 const char *property, 220 int posted) 221 { 222 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 223 const char *oh_name; 224 struct device_node *np; 225 struct omap_hwmod *oh; 226 struct resource irq, mem; 227 int r = 0; 228 229 if (of_have_populated_dt()) { 230 np = omap_get_timer_dt(omap_timer_match, property); 231 if (!np) 232 return -ENODEV; 233 234 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 235 if (!oh_name) 236 return -ENODEV; 237 238 timer->irq = irq_of_parse_and_map(np, 0); 239 if (!timer->irq) 240 return -ENXIO; 241 242 timer->io_base = of_iomap(np, 0); 243 244 of_node_put(np); 245 } else { 246 if (omap_dm_timer_reserve_systimer(gptimer_id)) 247 return -ENODEV; 248 249 sprintf(name, "timer%d", gptimer_id); 250 oh_name = name; 251 } 252 253 oh = omap_hwmod_lookup(oh_name); 254 if (!oh) 255 return -ENODEV; 256 257 if (!of_have_populated_dt()) { 258 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, 259 &irq); 260 if (r) 261 return -ENXIO; 262 timer->irq = irq.start; 263 264 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, 265 &mem); 266 if (r) 267 return -ENXIO; 268 269 /* Static mapping, never released */ 270 timer->io_base = ioremap(mem.start, mem.end - mem.start); 271 } 272 273 if (!timer->io_base) 274 return -ENXIO; 275 276 /* After the dmtimer is using hwmod these clocks won't be needed */ 277 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); 278 if (IS_ERR(timer->fclk)) 279 return -ENODEV; 280 281 /* FIXME: Need to remove hard-coded test on timer ID */ 282 if (gptimer_id != 12) { 283 struct clk *src; 284 285 src = clk_get(NULL, fck_source); 286 if (IS_ERR(src)) { 287 r = -EINVAL; 288 } else { 289 r = clk_set_parent(timer->fclk, src); 290 if (IS_ERR_VALUE(r)) 291 pr_warn("%s: %s cannot set source\n", 292 __func__, oh->name); 293 clk_put(src); 294 } 295 } 296 297 omap_hwmod_setup_one(oh_name); 298 omap_hwmod_enable(oh); 299 __omap_dm_timer_init_regs(timer); 300 301 if (posted) 302 __omap_dm_timer_enable_posted(timer); 303 304 /* Check that the intended posted configuration matches the actual */ 305 if (posted != timer->posted) 306 return -EINVAL; 307 308 timer->rate = clk_get_rate(timer->fclk); 309 timer->reserved = 1; 310 311 return r; 312 } 313 314 static void __init omap2_gp_clockevent_init(int gptimer_id, 315 const char *fck_source, 316 const char *property) 317 { 318 int res; 319 320 clkev.errata = omap_dm_timer_get_errata(); 321 322 /* 323 * For clock-event timers we never read the timer counter and 324 * so we are not impacted by errata i103 and i767. Therefore, 325 * we can safely ignore this errata for clock-event timers. 326 */ 327 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); 328 329 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property, 330 OMAP_TIMER_POSTED); 331 BUG_ON(res); 332 333 omap2_gp_timer_irq.dev_id = &clkev; 334 setup_irq(clkev.irq, &omap2_gp_timer_irq); 335 336 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 337 338 clockevent_gpt.cpumask = cpu_possible_mask; 339 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); 340 clockevents_config_and_register(&clockevent_gpt, clkev.rate, 341 3, /* Timer internal resynch latency */ 342 0xffffffff); 343 344 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", 345 gptimer_id, clkev.rate); 346 } 347 348 /* Clocksource code */ 349 static struct omap_dm_timer clksrc; 350 static bool use_gptimer_clksrc; 351 352 /* 353 * clocksource 354 */ 355 static cycle_t clocksource_read_cycles(struct clocksource *cs) 356 { 357 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 358 OMAP_TIMER_NONPOSTED); 359 } 360 361 static struct clocksource clocksource_gpt = { 362 .name = "gp_timer", 363 .rating = 300, 364 .read = clocksource_read_cycles, 365 .mask = CLOCKSOURCE_MASK(32), 366 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 367 }; 368 369 static u32 notrace dmtimer_read_sched_clock(void) 370 { 371 if (clksrc.reserved) 372 return __omap_dm_timer_read_counter(&clksrc, 373 OMAP_TIMER_NONPOSTED); 374 375 return 0; 376 } 377 378 static struct of_device_id omap_counter_match[] __initdata = { 379 { .compatible = "ti,omap-counter32k", }, 380 { } 381 }; 382 383 /* Setup free-running counter for clocksource */ 384 static int __init __maybe_unused omap2_sync32k_clocksource_init(void) 385 { 386 int ret; 387 struct device_node *np = NULL; 388 struct omap_hwmod *oh; 389 void __iomem *vbase; 390 const char *oh_name = "counter_32k"; 391 392 /* 393 * If device-tree is present, then search the DT blob 394 * to see if the 32kHz counter is supported. 395 */ 396 if (of_have_populated_dt()) { 397 np = omap_get_timer_dt(omap_counter_match, NULL); 398 if (!np) 399 return -ENODEV; 400 401 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 402 if (!oh_name) 403 return -ENODEV; 404 } 405 406 /* 407 * First check hwmod data is available for sync32k counter 408 */ 409 oh = omap_hwmod_lookup(oh_name); 410 if (!oh || oh->slaves_cnt == 0) 411 return -ENODEV; 412 413 omap_hwmod_setup_one(oh_name); 414 415 if (np) { 416 vbase = of_iomap(np, 0); 417 of_node_put(np); 418 } else { 419 vbase = omap_hwmod_get_mpu_rt_va(oh); 420 } 421 422 if (!vbase) { 423 pr_warn("%s: failed to get counter_32k resource\n", __func__); 424 return -ENXIO; 425 } 426 427 ret = omap_hwmod_enable(oh); 428 if (ret) { 429 pr_warn("%s: failed to enable counter_32k module (%d)\n", 430 __func__, ret); 431 return ret; 432 } 433 434 ret = omap_init_clocksource_32k(vbase); 435 if (ret) { 436 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", 437 __func__, ret); 438 omap_hwmod_idle(oh); 439 } 440 441 return ret; 442 } 443 444 static void __init omap2_gptimer_clocksource_init(int gptimer_id, 445 const char *fck_source) 446 { 447 int res; 448 449 clksrc.errata = omap_dm_timer_get_errata(); 450 451 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL, 452 OMAP_TIMER_NONPOSTED); 453 BUG_ON(res); 454 455 __omap_dm_timer_load_start(&clksrc, 456 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 457 OMAP_TIMER_NONPOSTED); 458 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); 459 460 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 461 pr_err("Could not register clocksource %s\n", 462 clocksource_gpt.name); 463 else 464 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", 465 gptimer_id, clksrc.rate); 466 } 467 468 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 469 /* 470 * The realtime counter also called master counter, is a free-running 471 * counter, which is related to real time. It produces the count used 472 * by the CPU local timer peripherals in the MPU cluster. The timer counts 473 * at a rate of 6.144 MHz. Because the device operates on different clocks 474 * in different power modes, the master counter shifts operation between 475 * clocks, adjusting the increment per clock in hardware accordingly to 476 * maintain a constant count rate. 477 */ 478 static void __init realtime_counter_init(void) 479 { 480 void __iomem *base; 481 static struct clk *sys_clk; 482 unsigned long rate; 483 unsigned int reg, num, den; 484 485 base = ioremap(REALTIME_COUNTER_BASE, SZ_32); 486 if (!base) { 487 pr_err("%s: ioremap failed\n", __func__); 488 return; 489 } 490 sys_clk = clk_get(NULL, "sys_clkin_ck"); 491 if (IS_ERR(sys_clk)) { 492 pr_err("%s: failed to get system clock handle\n", __func__); 493 iounmap(base); 494 return; 495 } 496 497 rate = clk_get_rate(sys_clk); 498 /* Numerator/denumerator values refer TRM Realtime Counter section */ 499 switch (rate) { 500 case 1200000: 501 num = 64; 502 den = 125; 503 break; 504 case 1300000: 505 num = 768; 506 den = 1625; 507 break; 508 case 19200000: 509 num = 8; 510 den = 25; 511 break; 512 case 2600000: 513 num = 384; 514 den = 1625; 515 break; 516 case 2700000: 517 num = 256; 518 den = 1125; 519 break; 520 case 38400000: 521 default: 522 /* Program it for 38.4 MHz */ 523 num = 4; 524 den = 25; 525 break; 526 } 527 528 /* Program numerator and denumerator registers */ 529 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & 530 NUMERATOR_DENUMERATOR_MASK; 531 reg |= num; 532 __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); 533 534 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & 535 NUMERATOR_DENUMERATOR_MASK; 536 reg |= den; 537 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 538 539 iounmap(base); 540 } 541 #else 542 static inline void __init realtime_counter_init(void) 543 {} 544 #endif 545 546 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ 547 clksrc_nr, clksrc_src) \ 548 void __init omap##name##_gptimer_timer_init(void) \ 549 { \ 550 omap_dmtimer_init(); \ 551 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 552 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \ 553 } 554 555 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ 556 clksrc_nr, clksrc_src) \ 557 void __init omap##name##_sync32k_timer_init(void) \ 558 { \ 559 omap_dmtimer_init(); \ 560 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 561 /* Enable the use of clocksource="gp_timer" kernel parameter */ \ 562 if (use_gptimer_clksrc) \ 563 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\ 564 else \ 565 omap2_sync32k_clocksource_init(); \ 566 } 567 568 #ifdef CONFIG_ARCH_OMAP2 569 OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon", 570 2, OMAP2_MPU_SOURCE); 571 #endif /* CONFIG_ARCH_OMAP2 */ 572 573 #ifdef CONFIG_ARCH_OMAP3 574 OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon", 575 2, OMAP3_MPU_SOURCE); 576 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure", 577 2, OMAP3_MPU_SOURCE); 578 OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon", 579 2, OMAP3_MPU_SOURCE); 580 #endif /* CONFIG_ARCH_OMAP3 */ 581 582 #ifdef CONFIG_SOC_AM33XX 583 OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon", 584 2, OMAP4_MPU_SOURCE); 585 #endif /* CONFIG_SOC_AM33XX */ 586 587 #ifdef CONFIG_ARCH_OMAP4 588 OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", 589 2, OMAP4_MPU_SOURCE); 590 #ifdef CONFIG_LOCAL_TIMERS 591 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); 592 void __init omap4_local_timer_init(void) 593 { 594 omap4_sync32k_timer_init(); 595 /* Local timers are not supprted on OMAP4430 ES1.0 */ 596 if (omap_rev() != OMAP4430_REV_ES1_0) { 597 int err; 598 599 if (of_have_populated_dt()) { 600 twd_local_timer_of_register(); 601 return; 602 } 603 604 err = twd_local_timer_register(&twd_local_timer); 605 if (err) 606 pr_err("twd_local_timer_register failed %d\n", err); 607 } 608 } 609 #else /* CONFIG_LOCAL_TIMERS */ 610 void __init omap4_local_timer_init(void) 611 { 612 omap4_sync32k_timer_init(); 613 } 614 #endif /* CONFIG_LOCAL_TIMERS */ 615 #endif /* CONFIG_ARCH_OMAP4 */ 616 617 #ifdef CONFIG_SOC_OMAP5 618 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", 619 2, OMAP4_MPU_SOURCE); 620 void __init omap5_realtime_timer_init(void) 621 { 622 int err; 623 624 omap5_sync32k_timer_init(); 625 realtime_counter_init(); 626 627 err = arch_timer_of_register(); 628 if (err) 629 pr_err("%s: arch_timer_register failed %d\n", __func__, err); 630 } 631 #endif /* CONFIG_SOC_OMAP5 */ 632 633 /** 634 * omap_timer_init - build and register timer device with an 635 * associated timer hwmod 636 * @oh: timer hwmod pointer to be used to build timer device 637 * @user: parameter that can be passed from calling hwmod API 638 * 639 * Called by omap_hwmod_for_each_by_class to register each of the timer 640 * devices present in the system. The number of timer devices is known 641 * by parsing through the hwmod database for a given class name. At the 642 * end of function call memory is allocated for timer device and it is 643 * registered to the framework ready to be proved by the driver. 644 */ 645 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) 646 { 647 int id; 648 int ret = 0; 649 char *name = "omap_timer"; 650 struct dmtimer_platform_data *pdata; 651 struct platform_device *pdev; 652 struct omap_timer_capability_dev_attr *timer_dev_attr; 653 654 pr_debug("%s: %s\n", __func__, oh->name); 655 656 /* on secure device, do not register secure timer */ 657 timer_dev_attr = oh->dev_attr; 658 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) 659 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) 660 return ret; 661 662 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 663 if (!pdata) { 664 pr_err("%s: No memory for [%s]\n", __func__, oh->name); 665 return -ENOMEM; 666 } 667 668 /* 669 * Extract the IDs from name field in hwmod database 670 * and use the same for constructing ids' for the 671 * timer devices. In a way, we are avoiding usage of 672 * static variable witin the function to do the same. 673 * CAUTION: We have to be careful and make sure the 674 * name in hwmod database does not change in which case 675 * we might either make corresponding change here or 676 * switch back static variable mechanism. 677 */ 678 sscanf(oh->name, "timer%2d", &id); 679 680 if (timer_dev_attr) 681 pdata->timer_capability = timer_dev_attr->timer_capability; 682 683 pdata->timer_errata = omap_dm_timer_get_errata(); 684 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 685 686 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata)); 687 688 if (IS_ERR(pdev)) { 689 pr_err("%s: Can't build omap_device for %s: %s.\n", 690 __func__, name, oh->name); 691 ret = -EINVAL; 692 } 693 694 kfree(pdata); 695 696 return ret; 697 } 698 699 /** 700 * omap2_dm_timer_init - top level regular device initialization 701 * 702 * Uses dedicated hwmod api to parse through hwmod database for 703 * given class name and then build and register the timer device. 704 */ 705 static int __init omap2_dm_timer_init(void) 706 { 707 int ret; 708 709 /* If dtb is there, the devices will be created dynamically */ 710 if (of_have_populated_dt()) 711 return -ENODEV; 712 713 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); 714 if (unlikely(ret)) { 715 pr_err("%s: device registration failed.\n", __func__); 716 return -EINVAL; 717 } 718 719 return 0; 720 } 721 omap_arch_initcall(omap2_dm_timer_init); 722 723 /** 724 * omap2_override_clocksource - clocksource override with user configuration 725 * 726 * Allows user to override default clocksource, using kernel parameter 727 * clocksource="gp_timer" (For all OMAP2PLUS architectures) 728 * 729 * Note that, here we are using same standard kernel parameter "clocksource=", 730 * and not introducing any OMAP specific interface. 731 */ 732 static int __init omap2_override_clocksource(char *str) 733 { 734 if (!str) 735 return 0; 736 /* 737 * For OMAP architecture, we only have two options 738 * - sync_32k (default) 739 * - gp_timer (sys_clk based) 740 */ 741 if (!strcmp(str, "gp_timer")) 742 use_gptimer_clksrc = true; 743 744 return 0; 745 } 746 early_param("clocksource", omap2_override_clocksource); 747