1 /* 2 * linux/arch/arm/mach-omap2/timer.c 3 * 4 * OMAP2 GP timer support. 5 * 6 * Copyright (C) 2009 Nokia Corporation 7 * 8 * Update to use new clocksource/clockevent layers 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 10 * Copyright (C) 2007 MontaVista Software, Inc. 11 * 12 * Original driver: 13 * Copyright (C) 2005 Nokia Corporation 14 * Author: Paul Mundt <paul.mundt@nokia.com> 15 * Juha Yrjölä <juha.yrjola@nokia.com> 16 * OMAP Dual-mode timer framework support by Timo Teras 17 * 18 * Some parts based off of TI's 24xx code: 19 * 20 * Copyright (C) 2004-2009 Texas Instruments, Inc. 21 * 22 * Roughly modelled after the OMAP1 MPU timer code. 23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 24 * 25 * This file is subject to the terms and conditions of the GNU General Public 26 * License. See the file "COPYING" in the main directory of this archive 27 * for more details. 28 */ 29 #include <linux/init.h> 30 #include <linux/time.h> 31 #include <linux/interrupt.h> 32 #include <linux/err.h> 33 #include <linux/clk.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/clocksource.h> 37 #include <linux/clockchips.h> 38 #include <linux/slab.h> 39 #include <linux/of.h> 40 #include <linux/of_address.h> 41 #include <linux/of_irq.h> 42 #include <linux/platform_device.h> 43 #include <linux/platform_data/dmtimer-omap.h> 44 #include <linux/sched_clock.h> 45 46 #include <asm/mach/time.h> 47 #include <asm/smp_twd.h> 48 49 #include "omap_hwmod.h" 50 #include "omap_device.h" 51 #include <plat/counter-32k.h> 52 #include <plat/dmtimer.h> 53 #include "omap-pm.h" 54 55 #include "soc.h" 56 #include "common.h" 57 #include "control.h" 58 #include "powerdomain.h" 59 #include "omap-secure.h" 60 61 #define REALTIME_COUNTER_BASE 0x48243200 62 #define INCREMENTER_NUMERATOR_OFFSET 0x10 63 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 64 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 65 66 /* Clockevent code */ 67 68 static struct omap_dm_timer clkev; 69 static struct clock_event_device clockevent_gpt; 70 71 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 72 static unsigned long arch_timer_freq; 73 74 void set_cntfreq(void) 75 { 76 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); 77 } 78 #endif 79 80 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 81 { 82 struct clock_event_device *evt = &clockevent_gpt; 83 84 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); 85 86 evt->event_handler(evt); 87 return IRQ_HANDLED; 88 } 89 90 static struct irqaction omap2_gp_timer_irq = { 91 .name = "gp_timer", 92 .flags = IRQF_TIMER | IRQF_IRQPOLL, 93 .handler = omap2_gp_timer_interrupt, 94 }; 95 96 static int omap2_gp_timer_set_next_event(unsigned long cycles, 97 struct clock_event_device *evt) 98 { 99 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 100 0xffffffff - cycles, OMAP_TIMER_POSTED); 101 102 return 0; 103 } 104 105 static void omap2_gp_timer_set_mode(enum clock_event_mode mode, 106 struct clock_event_device *evt) 107 { 108 u32 period; 109 110 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); 111 112 switch (mode) { 113 case CLOCK_EVT_MODE_PERIODIC: 114 period = clkev.rate / HZ; 115 period -= 1; 116 /* Looks like we need to first set the load value separately */ 117 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 118 0xffffffff - period, OMAP_TIMER_POSTED); 119 __omap_dm_timer_load_start(&clkev, 120 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 121 0xffffffff - period, OMAP_TIMER_POSTED); 122 break; 123 case CLOCK_EVT_MODE_ONESHOT: 124 break; 125 case CLOCK_EVT_MODE_UNUSED: 126 case CLOCK_EVT_MODE_SHUTDOWN: 127 case CLOCK_EVT_MODE_RESUME: 128 break; 129 } 130 } 131 132 static struct clock_event_device clockevent_gpt = { 133 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 134 .rating = 300, 135 .set_next_event = omap2_gp_timer_set_next_event, 136 .set_mode = omap2_gp_timer_set_mode, 137 }; 138 139 static struct property device_disabled = { 140 .name = "status", 141 .length = sizeof("disabled"), 142 .value = "disabled", 143 }; 144 145 static const struct of_device_id omap_timer_match[] __initconst = { 146 { .compatible = "ti,omap2420-timer", }, 147 { .compatible = "ti,omap3430-timer", }, 148 { .compatible = "ti,omap4430-timer", }, 149 { .compatible = "ti,omap5430-timer", }, 150 { .compatible = "ti,dm814-timer", }, 151 { .compatible = "ti,dm816-timer", }, 152 { .compatible = "ti,am335x-timer", }, 153 { .compatible = "ti,am335x-timer-1ms", }, 154 { } 155 }; 156 157 /** 158 * omap_get_timer_dt - get a timer using device-tree 159 * @match - device-tree match structure for matching a device type 160 * @property - optional timer property to match 161 * 162 * Helper function to get a timer during early boot using device-tree for use 163 * as kernel system timer. Optionally, the property argument can be used to 164 * select a timer with a specific property. Once a timer is found then mark 165 * the timer node in device-tree as disabled, to prevent the kernel from 166 * registering this timer as a platform device and so no one else can use it. 167 */ 168 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, 169 const char *property) 170 { 171 struct device_node *np; 172 173 for_each_matching_node(np, match) { 174 if (!of_device_is_available(np)) 175 continue; 176 177 if (property && !of_get_property(np, property, NULL)) 178 continue; 179 180 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || 181 of_get_property(np, "ti,timer-dsp", NULL) || 182 of_get_property(np, "ti,timer-pwm", NULL) || 183 of_get_property(np, "ti,timer-secure", NULL))) 184 continue; 185 186 of_add_property(np, &device_disabled); 187 return np; 188 } 189 190 return NULL; 191 } 192 193 /** 194 * omap_dmtimer_init - initialisation function when device tree is used 195 * 196 * For secure OMAP3 devices, timers with device type "timer-secure" cannot 197 * be used by the kernel as they are reserved. Therefore, to prevent the 198 * kernel registering these devices remove them dynamically from the device 199 * tree on boot. 200 */ 201 static void __init omap_dmtimer_init(void) 202 { 203 struct device_node *np; 204 205 if (!cpu_is_omap34xx()) 206 return; 207 208 /* If we are a secure device, remove any secure timer nodes */ 209 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { 210 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); 211 if (np) 212 of_node_put(np); 213 } 214 } 215 216 /** 217 * omap_dm_timer_get_errata - get errata flags for a timer 218 * 219 * Get the timer errata flags that are specific to the OMAP device being used. 220 */ 221 static u32 __init omap_dm_timer_get_errata(void) 222 { 223 if (cpu_is_omap24xx()) 224 return 0; 225 226 return OMAP_TIMER_ERRATA_I103_I767; 227 } 228 229 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 230 const char *fck_source, 231 const char *property, 232 const char **timer_name, 233 int posted) 234 { 235 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 236 const char *oh_name = NULL; 237 struct device_node *np; 238 struct omap_hwmod *oh; 239 struct resource irq, mem; 240 struct clk *src; 241 int r = 0; 242 243 if (of_have_populated_dt()) { 244 np = omap_get_timer_dt(omap_timer_match, property); 245 if (!np) 246 return -ENODEV; 247 248 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 249 if (!oh_name) 250 return -ENODEV; 251 252 timer->irq = irq_of_parse_and_map(np, 0); 253 if (!timer->irq) 254 return -ENXIO; 255 256 timer->io_base = of_iomap(np, 0); 257 258 of_node_put(np); 259 } else { 260 if (omap_dm_timer_reserve_systimer(timer->id)) 261 return -ENODEV; 262 263 sprintf(name, "timer%d", timer->id); 264 oh_name = name; 265 } 266 267 oh = omap_hwmod_lookup(oh_name); 268 if (!oh) 269 return -ENODEV; 270 271 *timer_name = oh->name; 272 273 if (!of_have_populated_dt()) { 274 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, 275 &irq); 276 if (r) 277 return -ENXIO; 278 timer->irq = irq.start; 279 280 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, 281 &mem); 282 if (r) 283 return -ENXIO; 284 285 /* Static mapping, never released */ 286 timer->io_base = ioremap(mem.start, mem.end - mem.start); 287 } 288 289 if (!timer->io_base) 290 return -ENXIO; 291 292 /* After the dmtimer is using hwmod these clocks won't be needed */ 293 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); 294 if (IS_ERR(timer->fclk)) 295 return PTR_ERR(timer->fclk); 296 297 src = clk_get(NULL, fck_source); 298 if (IS_ERR(src)) 299 return PTR_ERR(src); 300 301 if (clk_get_parent(timer->fclk) != src) { 302 r = clk_set_parent(timer->fclk, src); 303 if (r < 0) { 304 pr_warn("%s: %s cannot set source\n", __func__, 305 oh->name); 306 clk_put(src); 307 return r; 308 } 309 } 310 311 clk_put(src); 312 313 omap_hwmod_setup_one(oh_name); 314 omap_hwmod_enable(oh); 315 __omap_dm_timer_init_regs(timer); 316 317 if (posted) 318 __omap_dm_timer_enable_posted(timer); 319 320 /* Check that the intended posted configuration matches the actual */ 321 if (posted != timer->posted) 322 return -EINVAL; 323 324 timer->rate = clk_get_rate(timer->fclk); 325 timer->reserved = 1; 326 327 return r; 328 } 329 330 static void __init omap2_gp_clockevent_init(int gptimer_id, 331 const char *fck_source, 332 const char *property) 333 { 334 int res; 335 336 clkev.id = gptimer_id; 337 clkev.errata = omap_dm_timer_get_errata(); 338 339 /* 340 * For clock-event timers we never read the timer counter and 341 * so we are not impacted by errata i103 and i767. Therefore, 342 * we can safely ignore this errata for clock-event timers. 343 */ 344 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); 345 346 res = omap_dm_timer_init_one(&clkev, fck_source, property, 347 &clockevent_gpt.name, OMAP_TIMER_POSTED); 348 BUG_ON(res); 349 350 omap2_gp_timer_irq.dev_id = &clkev; 351 setup_irq(clkev.irq, &omap2_gp_timer_irq); 352 353 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 354 355 clockevent_gpt.cpumask = cpu_possible_mask; 356 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); 357 clockevents_config_and_register(&clockevent_gpt, clkev.rate, 358 3, /* Timer internal resynch latency */ 359 0xffffffff); 360 361 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, 362 clkev.rate); 363 } 364 365 /* Clocksource code */ 366 static struct omap_dm_timer clksrc; 367 static bool use_gptimer_clksrc __initdata; 368 369 /* 370 * clocksource 371 */ 372 static cycle_t clocksource_read_cycles(struct clocksource *cs) 373 { 374 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 375 OMAP_TIMER_NONPOSTED); 376 } 377 378 static struct clocksource clocksource_gpt = { 379 .rating = 300, 380 .read = clocksource_read_cycles, 381 .mask = CLOCKSOURCE_MASK(32), 382 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 383 }; 384 385 static u64 notrace dmtimer_read_sched_clock(void) 386 { 387 if (clksrc.reserved) 388 return __omap_dm_timer_read_counter(&clksrc, 389 OMAP_TIMER_NONPOSTED); 390 391 return 0; 392 } 393 394 static const struct of_device_id omap_counter_match[] __initconst = { 395 { .compatible = "ti,omap-counter32k", }, 396 { } 397 }; 398 399 /* Setup free-running counter for clocksource */ 400 static int __init __maybe_unused omap2_sync32k_clocksource_init(void) 401 { 402 int ret; 403 struct device_node *np = NULL; 404 struct omap_hwmod *oh; 405 void __iomem *vbase; 406 const char *oh_name = "counter_32k"; 407 408 /* 409 * If device-tree is present, then search the DT blob 410 * to see if the 32kHz counter is supported. 411 */ 412 if (of_have_populated_dt()) { 413 np = omap_get_timer_dt(omap_counter_match, NULL); 414 if (!np) 415 return -ENODEV; 416 417 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); 418 if (!oh_name) 419 return -ENODEV; 420 } 421 422 /* 423 * First check hwmod data is available for sync32k counter 424 */ 425 oh = omap_hwmod_lookup(oh_name); 426 if (!oh || oh->slaves_cnt == 0) 427 return -ENODEV; 428 429 omap_hwmod_setup_one(oh_name); 430 431 if (np) { 432 vbase = of_iomap(np, 0); 433 of_node_put(np); 434 } else { 435 vbase = omap_hwmod_get_mpu_rt_va(oh); 436 } 437 438 if (!vbase) { 439 pr_warn("%s: failed to get counter_32k resource\n", __func__); 440 return -ENXIO; 441 } 442 443 ret = omap_hwmod_enable(oh); 444 if (ret) { 445 pr_warn("%s: failed to enable counter_32k module (%d)\n", 446 __func__, ret); 447 return ret; 448 } 449 450 ret = omap_init_clocksource_32k(vbase); 451 if (ret) { 452 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", 453 __func__, ret); 454 omap_hwmod_idle(oh); 455 } 456 457 return ret; 458 } 459 460 static void __init omap2_gptimer_clocksource_init(int gptimer_id, 461 const char *fck_source, 462 const char *property) 463 { 464 int res; 465 466 clksrc.id = gptimer_id; 467 clksrc.errata = omap_dm_timer_get_errata(); 468 469 res = omap_dm_timer_init_one(&clksrc, fck_source, property, 470 &clocksource_gpt.name, 471 OMAP_TIMER_NONPOSTED); 472 BUG_ON(res); 473 474 __omap_dm_timer_load_start(&clksrc, 475 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 476 OMAP_TIMER_NONPOSTED); 477 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate); 478 479 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 480 pr_err("Could not register clocksource %s\n", 481 clocksource_gpt.name); 482 else 483 pr_info("OMAP clocksource: %s at %lu Hz\n", 484 clocksource_gpt.name, clksrc.rate); 485 } 486 487 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 488 /* 489 * The realtime counter also called master counter, is a free-running 490 * counter, which is related to real time. It produces the count used 491 * by the CPU local timer peripherals in the MPU cluster. The timer counts 492 * at a rate of 6.144 MHz. Because the device operates on different clocks 493 * in different power modes, the master counter shifts operation between 494 * clocks, adjusting the increment per clock in hardware accordingly to 495 * maintain a constant count rate. 496 */ 497 static void __init realtime_counter_init(void) 498 { 499 void __iomem *base; 500 static struct clk *sys_clk; 501 unsigned long rate; 502 unsigned int reg; 503 unsigned long long num, den; 504 505 base = ioremap(REALTIME_COUNTER_BASE, SZ_32); 506 if (!base) { 507 pr_err("%s: ioremap failed\n", __func__); 508 return; 509 } 510 sys_clk = clk_get(NULL, "sys_clkin"); 511 if (IS_ERR(sys_clk)) { 512 pr_err("%s: failed to get system clock handle\n", __func__); 513 iounmap(base); 514 return; 515 } 516 517 rate = clk_get_rate(sys_clk); 518 519 if (soc_is_dra7xx()) { 520 /* 521 * Errata i856 says the 32.768KHz crystal does not start at 522 * power on, so the CPU falls back to an emulated 32KHz clock 523 * based on sysclk / 610 instead. This causes the master counter 524 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 525 * (OR sysclk * 75 / 244) 526 * 527 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions. 528 * Of course any board built without a populated 32.768KHz 529 * crystal would also need this fix even if the CPU is fixed 530 * later. 531 * 532 * Either case can be detected by using the two speedselect bits 533 * If they are not 0, then the 32.768KHz clock driving the 534 * coarse counter that corrects the fine counter every time it 535 * ticks is actually rate/610 rather than 32.768KHz and we 536 * should compensate to avoid the 570ppm (at 20MHz, much worse 537 * at other rates) too fast system time. 538 */ 539 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); 540 if (reg & DRA7_SPEEDSELECT_MASK) { 541 num = 75; 542 den = 244; 543 goto sysclk1_based; 544 } 545 } 546 547 /* Numerator/denumerator values refer TRM Realtime Counter section */ 548 switch (rate) { 549 case 12000000: 550 num = 64; 551 den = 125; 552 break; 553 case 13000000: 554 num = 768; 555 den = 1625; 556 break; 557 case 19200000: 558 num = 8; 559 den = 25; 560 break; 561 case 20000000: 562 num = 192; 563 den = 625; 564 break; 565 case 26000000: 566 num = 384; 567 den = 1625; 568 break; 569 case 27000000: 570 num = 256; 571 den = 1125; 572 break; 573 case 38400000: 574 default: 575 /* Program it for 38.4 MHz */ 576 num = 4; 577 den = 25; 578 break; 579 } 580 581 sysclk1_based: 582 /* Program numerator and denumerator registers */ 583 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & 584 NUMERATOR_DENUMERATOR_MASK; 585 reg |= num; 586 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); 587 588 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & 589 NUMERATOR_DENUMERATOR_MASK; 590 reg |= den; 591 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 592 593 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); 594 set_cntfreq(); 595 596 iounmap(base); 597 } 598 #else 599 static inline void __init realtime_counter_init(void) 600 {} 601 #endif 602 603 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ 604 clksrc_nr, clksrc_src, clksrc_prop) \ 605 void __init omap##name##_gptimer_timer_init(void) \ 606 { \ 607 omap_clk_init(); \ 608 omap_dmtimer_init(); \ 609 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 610 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ 611 clksrc_prop); \ 612 } 613 614 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ 615 clksrc_nr, clksrc_src, clksrc_prop) \ 616 void __init omap##name##_sync32k_timer_init(void) \ 617 { \ 618 omap_clk_init(); \ 619 omap_dmtimer_init(); \ 620 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 621 /* Enable the use of clocksource="gp_timer" kernel parameter */ \ 622 if (use_gptimer_clksrc) \ 623 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ 624 clksrc_prop); \ 625 else \ 626 omap2_sync32k_clocksource_init(); \ 627 } 628 629 #ifdef CONFIG_ARCH_OMAP2 630 OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon", 631 2, "timer_sys_ck", NULL); 632 #endif /* CONFIG_ARCH_OMAP2 */ 633 634 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) 635 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon", 636 2, "timer_sys_ck", NULL); 637 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", 638 2, "timer_sys_ck", NULL); 639 #endif /* CONFIG_ARCH_OMAP3 */ 640 641 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \ 642 defined(CONFIG_SOC_AM43XX) 643 OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, 644 1, "timer_sys_ck", "ti,timer-alwon"); 645 #endif 646 647 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 648 defined(CONFIG_SOC_DRA7XX) 649 static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", 650 2, "sys_clkin_ck", NULL); 651 #endif 652 653 #ifdef CONFIG_ARCH_OMAP4 654 #ifdef CONFIG_HAVE_ARM_TWD 655 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); 656 void __init omap4_local_timer_init(void) 657 { 658 omap4_sync32k_timer_init(); 659 /* Local timers are not supprted on OMAP4430 ES1.0 */ 660 if (omap_rev() != OMAP4430_REV_ES1_0) { 661 int err; 662 663 if (of_have_populated_dt()) { 664 clocksource_of_init(); 665 return; 666 } 667 668 err = twd_local_timer_register(&twd_local_timer); 669 if (err) 670 pr_err("twd_local_timer_register failed %d\n", err); 671 } 672 } 673 #else 674 void __init omap4_local_timer_init(void) 675 { 676 omap4_sync32k_timer_init(); 677 } 678 #endif /* CONFIG_HAVE_ARM_TWD */ 679 #endif /* CONFIG_ARCH_OMAP4 */ 680 681 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 682 void __init omap5_realtime_timer_init(void) 683 { 684 omap4_sync32k_timer_init(); 685 realtime_counter_init(); 686 687 clocksource_of_init(); 688 } 689 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ 690 691 /** 692 * omap_timer_init - build and register timer device with an 693 * associated timer hwmod 694 * @oh: timer hwmod pointer to be used to build timer device 695 * @user: parameter that can be passed from calling hwmod API 696 * 697 * Called by omap_hwmod_for_each_by_class to register each of the timer 698 * devices present in the system. The number of timer devices is known 699 * by parsing through the hwmod database for a given class name. At the 700 * end of function call memory is allocated for timer device and it is 701 * registered to the framework ready to be proved by the driver. 702 */ 703 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) 704 { 705 int id; 706 int ret = 0; 707 char *name = "omap_timer"; 708 struct dmtimer_platform_data *pdata; 709 struct platform_device *pdev; 710 struct omap_timer_capability_dev_attr *timer_dev_attr; 711 712 pr_debug("%s: %s\n", __func__, oh->name); 713 714 /* on secure device, do not register secure timer */ 715 timer_dev_attr = oh->dev_attr; 716 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) 717 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) 718 return ret; 719 720 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 721 if (!pdata) { 722 pr_err("%s: No memory for [%s]\n", __func__, oh->name); 723 return -ENOMEM; 724 } 725 726 /* 727 * Extract the IDs from name field in hwmod database 728 * and use the same for constructing ids' for the 729 * timer devices. In a way, we are avoiding usage of 730 * static variable witin the function to do the same. 731 * CAUTION: We have to be careful and make sure the 732 * name in hwmod database does not change in which case 733 * we might either make corresponding change here or 734 * switch back static variable mechanism. 735 */ 736 sscanf(oh->name, "timer%2d", &id); 737 738 if (timer_dev_attr) 739 pdata->timer_capability = timer_dev_attr->timer_capability; 740 741 pdata->timer_errata = omap_dm_timer_get_errata(); 742 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 743 744 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata)); 745 746 if (IS_ERR(pdev)) { 747 pr_err("%s: Can't build omap_device for %s: %s.\n", 748 __func__, name, oh->name); 749 ret = -EINVAL; 750 } 751 752 kfree(pdata); 753 754 return ret; 755 } 756 757 /** 758 * omap2_dm_timer_init - top level regular device initialization 759 * 760 * Uses dedicated hwmod api to parse through hwmod database for 761 * given class name and then build and register the timer device. 762 */ 763 static int __init omap2_dm_timer_init(void) 764 { 765 int ret; 766 767 /* If dtb is there, the devices will be created dynamically */ 768 if (of_have_populated_dt()) 769 return -ENODEV; 770 771 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); 772 if (unlikely(ret)) { 773 pr_err("%s: device registration failed.\n", __func__); 774 return -EINVAL; 775 } 776 777 return 0; 778 } 779 omap_arch_initcall(omap2_dm_timer_init); 780 781 /** 782 * omap2_override_clocksource - clocksource override with user configuration 783 * 784 * Allows user to override default clocksource, using kernel parameter 785 * clocksource="gp_timer" (For all OMAP2PLUS architectures) 786 * 787 * Note that, here we are using same standard kernel parameter "clocksource=", 788 * and not introducing any OMAP specific interface. 789 */ 790 static int __init omap2_override_clocksource(char *str) 791 { 792 if (!str) 793 return 0; 794 /* 795 * For OMAP architecture, we only have two options 796 * - sync_32k (default) 797 * - gp_timer (sys_clk based) 798 */ 799 if (!strcmp(str, "gp_timer")) 800 use_gptimer_clksrc = true; 801 802 return 0; 803 } 804 early_param("clocksource", omap2_override_clocksource); 805