1 /* 2 * linux/arch/arm/mach-omap2/timer.c 3 * 4 * OMAP2 GP timer support. 5 * 6 * Copyright (C) 2009 Nokia Corporation 7 * 8 * Update to use new clocksource/clockevent layers 9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> 10 * Copyright (C) 2007 MontaVista Software, Inc. 11 * 12 * Original driver: 13 * Copyright (C) 2005 Nokia Corporation 14 * Author: Paul Mundt <paul.mundt@nokia.com> 15 * Juha Yrjölä <juha.yrjola@nokia.com> 16 * OMAP Dual-mode timer framework support by Timo Teras 17 * 18 * Some parts based off of TI's 24xx code: 19 * 20 * Copyright (C) 2004-2009 Texas Instruments, Inc. 21 * 22 * Roughly modelled after the OMAP1 MPU timer code. 23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 24 * 25 * This file is subject to the terms and conditions of the GNU General Public 26 * License. See the file "COPYING" in the main directory of this archive 27 * for more details. 28 */ 29 #include <linux/init.h> 30 #include <linux/time.h> 31 #include <linux/interrupt.h> 32 #include <linux/err.h> 33 #include <linux/clk.h> 34 #include <linux/delay.h> 35 #include <linux/irq.h> 36 #include <linux/clocksource.h> 37 #include <linux/clockchips.h> 38 #include <linux/slab.h> 39 #include <linux/of.h> 40 41 #include <asm/mach/time.h> 42 #include <asm/smp_twd.h> 43 #include <asm/sched_clock.h> 44 45 #include <asm/arch_timer.h> 46 #include <plat/omap_hwmod.h> 47 #include <plat/omap_device.h> 48 #include <plat/dmtimer.h> 49 #include <plat/omap-pm.h> 50 51 #include "soc.h" 52 #include "common.h" 53 #include "powerdomain.h" 54 55 /* Parent clocks, eventually these will come from the clock framework */ 56 57 #define OMAP2_MPU_SOURCE "sys_ck" 58 #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE 59 #define OMAP4_MPU_SOURCE "sys_clkin_ck" 60 #define OMAP2_32K_SOURCE "func_32k_ck" 61 #define OMAP3_32K_SOURCE "omap_32k_fck" 62 #define OMAP4_32K_SOURCE "sys_32k_ck" 63 64 #ifdef CONFIG_OMAP_32K_TIMER 65 #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE 66 #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE 67 #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE 68 #define OMAP3_SECURE_TIMER 12 69 #else 70 #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE 71 #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE 72 #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE 73 #define OMAP3_SECURE_TIMER 1 74 #endif 75 76 #define REALTIME_COUNTER_BASE 0x48243200 77 #define INCREMENTER_NUMERATOR_OFFSET 0x10 78 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 79 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 80 81 /* Clockevent code */ 82 83 static struct omap_dm_timer clkev; 84 static struct clock_event_device clockevent_gpt; 85 86 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 87 { 88 struct clock_event_device *evt = &clockevent_gpt; 89 90 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); 91 92 evt->event_handler(evt); 93 return IRQ_HANDLED; 94 } 95 96 static struct irqaction omap2_gp_timer_irq = { 97 .name = "gp_timer", 98 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 99 .handler = omap2_gp_timer_interrupt, 100 }; 101 102 static int omap2_gp_timer_set_next_event(unsigned long cycles, 103 struct clock_event_device *evt) 104 { 105 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 106 0xffffffff - cycles, 1); 107 108 return 0; 109 } 110 111 static void omap2_gp_timer_set_mode(enum clock_event_mode mode, 112 struct clock_event_device *evt) 113 { 114 u32 period; 115 116 __omap_dm_timer_stop(&clkev, 1, clkev.rate); 117 118 switch (mode) { 119 case CLOCK_EVT_MODE_PERIODIC: 120 period = clkev.rate / HZ; 121 period -= 1; 122 /* Looks like we need to first set the load value separately */ 123 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 124 0xffffffff - period, 1); 125 __omap_dm_timer_load_start(&clkev, 126 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 127 0xffffffff - period, 1); 128 break; 129 case CLOCK_EVT_MODE_ONESHOT: 130 break; 131 case CLOCK_EVT_MODE_UNUSED: 132 case CLOCK_EVT_MODE_SHUTDOWN: 133 case CLOCK_EVT_MODE_RESUME: 134 break; 135 } 136 } 137 138 static struct clock_event_device clockevent_gpt = { 139 .name = "gp_timer", 140 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 141 .shift = 32, 142 .rating = 300, 143 .set_next_event = omap2_gp_timer_set_next_event, 144 .set_mode = omap2_gp_timer_set_mode, 145 }; 146 147 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 148 int gptimer_id, 149 const char *fck_source) 150 { 151 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 152 struct omap_hwmod *oh; 153 struct resource irq_rsrc, mem_rsrc; 154 size_t size; 155 int res = 0; 156 int r; 157 158 sprintf(name, "timer%d", gptimer_id); 159 omap_hwmod_setup_one(name); 160 oh = omap_hwmod_lookup(name); 161 if (!oh) 162 return -ENODEV; 163 164 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); 165 if (r) 166 return -ENXIO; 167 timer->irq = irq_rsrc.start; 168 169 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); 170 if (r) 171 return -ENXIO; 172 timer->phys_base = mem_rsrc.start; 173 size = mem_rsrc.end - mem_rsrc.start; 174 175 /* Static mapping, never released */ 176 timer->io_base = ioremap(timer->phys_base, size); 177 if (!timer->io_base) 178 return -ENXIO; 179 180 /* After the dmtimer is using hwmod these clocks won't be needed */ 181 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); 182 if (IS_ERR(timer->fclk)) 183 return -ENODEV; 184 185 omap_hwmod_enable(oh); 186 187 if (omap_dm_timer_reserve_systimer(gptimer_id)) 188 return -ENODEV; 189 190 if (gptimer_id != 12) { 191 struct clk *src; 192 193 src = clk_get(NULL, fck_source); 194 if (IS_ERR(src)) { 195 res = -EINVAL; 196 } else { 197 res = __omap_dm_timer_set_source(timer->fclk, src); 198 if (IS_ERR_VALUE(res)) 199 pr_warning("%s: timer%i cannot set source\n", 200 __func__, gptimer_id); 201 clk_put(src); 202 } 203 } 204 __omap_dm_timer_init_regs(timer); 205 __omap_dm_timer_reset(timer, 1, 1); 206 timer->posted = 1; 207 208 timer->rate = clk_get_rate(timer->fclk); 209 210 timer->reserved = 1; 211 212 return res; 213 } 214 215 static void __init omap2_gp_clockevent_init(int gptimer_id, 216 const char *fck_source) 217 { 218 int res; 219 220 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); 221 BUG_ON(res); 222 223 omap2_gp_timer_irq.dev_id = &clkev; 224 setup_irq(clkev.irq, &omap2_gp_timer_irq); 225 226 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 227 228 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, 229 clockevent_gpt.shift); 230 clockevent_gpt.max_delta_ns = 231 clockevent_delta2ns(0xffffffff, &clockevent_gpt); 232 clockevent_gpt.min_delta_ns = 233 clockevent_delta2ns(3, &clockevent_gpt); 234 /* Timer internal resynch latency. */ 235 236 clockevent_gpt.cpumask = cpu_possible_mask; 237 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); 238 clockevents_register_device(&clockevent_gpt); 239 240 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", 241 gptimer_id, clkev.rate); 242 } 243 244 /* Clocksource code */ 245 static struct omap_dm_timer clksrc; 246 static bool use_gptimer_clksrc; 247 248 /* 249 * clocksource 250 */ 251 static cycle_t clocksource_read_cycles(struct clocksource *cs) 252 { 253 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); 254 } 255 256 static struct clocksource clocksource_gpt = { 257 .name = "gp_timer", 258 .rating = 300, 259 .read = clocksource_read_cycles, 260 .mask = CLOCKSOURCE_MASK(32), 261 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 262 }; 263 264 static u32 notrace dmtimer_read_sched_clock(void) 265 { 266 if (clksrc.reserved) 267 return __omap_dm_timer_read_counter(&clksrc, 1); 268 269 return 0; 270 } 271 272 #ifdef CONFIG_OMAP_32K_TIMER 273 /* Setup free-running counter for clocksource */ 274 static int __init omap2_sync32k_clocksource_init(void) 275 { 276 int ret; 277 struct omap_hwmod *oh; 278 void __iomem *vbase; 279 const char *oh_name = "counter_32k"; 280 281 /* 282 * First check hwmod data is available for sync32k counter 283 */ 284 oh = omap_hwmod_lookup(oh_name); 285 if (!oh || oh->slaves_cnt == 0) 286 return -ENODEV; 287 288 omap_hwmod_setup_one(oh_name); 289 290 vbase = omap_hwmod_get_mpu_rt_va(oh); 291 if (!vbase) { 292 pr_warn("%s: failed to get counter_32k resource\n", __func__); 293 return -ENXIO; 294 } 295 296 ret = omap_hwmod_enable(oh); 297 if (ret) { 298 pr_warn("%s: failed to enable counter_32k module (%d)\n", 299 __func__, ret); 300 return ret; 301 } 302 303 ret = omap_init_clocksource_32k(vbase); 304 if (ret) { 305 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", 306 __func__, ret); 307 omap_hwmod_idle(oh); 308 } 309 310 return ret; 311 } 312 #else 313 static inline int omap2_sync32k_clocksource_init(void) 314 { 315 return -ENODEV; 316 } 317 #endif 318 319 static void __init omap2_gptimer_clocksource_init(int gptimer_id, 320 const char *fck_source) 321 { 322 int res; 323 324 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source); 325 BUG_ON(res); 326 327 __omap_dm_timer_load_start(&clksrc, 328 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); 329 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); 330 331 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 332 pr_err("Could not register clocksource %s\n", 333 clocksource_gpt.name); 334 else 335 pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", 336 gptimer_id, clksrc.rate); 337 } 338 339 static void __init omap2_clocksource_init(int gptimer_id, 340 const char *fck_source) 341 { 342 /* 343 * First give preference to kernel parameter configuration 344 * by user (clocksource="gp_timer"). 345 * 346 * In case of missing kernel parameter for clocksource, 347 * first check for availability for 32k-sync timer, in case 348 * of failure in finding 32k_counter module or registering 349 * it as clocksource, execution will fallback to gp-timer. 350 */ 351 if (use_gptimer_clksrc == true) 352 omap2_gptimer_clocksource_init(gptimer_id, fck_source); 353 else if (omap2_sync32k_clocksource_init()) 354 /* Fall back to gp-timer code */ 355 omap2_gptimer_clocksource_init(gptimer_id, fck_source); 356 } 357 358 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 359 /* 360 * The realtime counter also called master counter, is a free-running 361 * counter, which is related to real time. It produces the count used 362 * by the CPU local timer peripherals in the MPU cluster. The timer counts 363 * at a rate of 6.144 MHz. Because the device operates on different clocks 364 * in different power modes, the master counter shifts operation between 365 * clocks, adjusting the increment per clock in hardware accordingly to 366 * maintain a constant count rate. 367 */ 368 static void __init realtime_counter_init(void) 369 { 370 void __iomem *base; 371 static struct clk *sys_clk; 372 unsigned long rate; 373 unsigned int reg, num, den; 374 375 base = ioremap(REALTIME_COUNTER_BASE, SZ_32); 376 if (!base) { 377 pr_err("%s: ioremap failed\n", __func__); 378 return; 379 } 380 sys_clk = clk_get(NULL, "sys_clkin_ck"); 381 if (IS_ERR(sys_clk)) { 382 pr_err("%s: failed to get system clock handle\n", __func__); 383 iounmap(base); 384 return; 385 } 386 387 rate = clk_get_rate(sys_clk); 388 /* Numerator/denumerator values refer TRM Realtime Counter section */ 389 switch (rate) { 390 case 1200000: 391 num = 64; 392 den = 125; 393 break; 394 case 1300000: 395 num = 768; 396 den = 1625; 397 break; 398 case 19200000: 399 num = 8; 400 den = 25; 401 break; 402 case 2600000: 403 num = 384; 404 den = 1625; 405 break; 406 case 2700000: 407 num = 256; 408 den = 1125; 409 break; 410 case 38400000: 411 default: 412 /* Program it for 38.4 MHz */ 413 num = 4; 414 den = 25; 415 break; 416 } 417 418 /* Program numerator and denumerator registers */ 419 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & 420 NUMERATOR_DENUMERATOR_MASK; 421 reg |= num; 422 __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); 423 424 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & 425 NUMERATOR_DENUMERATOR_MASK; 426 reg |= den; 427 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 428 429 iounmap(base); 430 } 431 #else 432 static inline void __init realtime_counter_init(void) 433 {} 434 #endif 435 436 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ 437 clksrc_nr, clksrc_src) \ 438 static void __init omap##name##_timer_init(void) \ 439 { \ 440 omap2_gp_clockevent_init((clkev_nr), clkev_src); \ 441 omap2_clocksource_init((clksrc_nr), clksrc_src); \ 442 } 443 444 #define OMAP_SYS_TIMER(name) \ 445 struct sys_timer omap##name##_timer = { \ 446 .init = omap##name##_timer_init, \ 447 }; 448 449 #ifdef CONFIG_ARCH_OMAP2 450 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE) 451 OMAP_SYS_TIMER(2) 452 #endif 453 454 #ifdef CONFIG_ARCH_OMAP3 455 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE) 456 OMAP_SYS_TIMER(3) 457 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, 458 2, OMAP3_MPU_SOURCE) 459 OMAP_SYS_TIMER(3_secure) 460 #endif 461 462 #ifdef CONFIG_SOC_AM33XX 463 OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) 464 OMAP_SYS_TIMER(3_am33xx) 465 #endif 466 467 #ifdef CONFIG_ARCH_OMAP4 468 #ifdef CONFIG_LOCAL_TIMERS 469 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 470 OMAP44XX_LOCAL_TWD_BASE, 29); 471 #endif 472 473 static void __init omap4_timer_init(void) 474 { 475 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); 476 omap2_clocksource_init(2, OMAP4_MPU_SOURCE); 477 #ifdef CONFIG_LOCAL_TIMERS 478 /* Local timers are not supprted on OMAP4430 ES1.0 */ 479 if (omap_rev() != OMAP4430_REV_ES1_0) { 480 int err; 481 482 if (of_have_populated_dt()) { 483 twd_local_timer_of_register(); 484 return; 485 } 486 487 err = twd_local_timer_register(&twd_local_timer); 488 if (err) 489 pr_err("twd_local_timer_register failed %d\n", err); 490 } 491 #endif 492 } 493 OMAP_SYS_TIMER(4) 494 #endif 495 496 #ifdef CONFIG_SOC_OMAP5 497 static void __init omap5_timer_init(void) 498 { 499 int err; 500 501 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); 502 omap2_clocksource_init(2, OMAP4_MPU_SOURCE); 503 realtime_counter_init(); 504 505 err = arch_timer_of_register(); 506 if (err) 507 pr_err("%s: arch_timer_register failed %d\n", __func__, err); 508 } 509 OMAP_SYS_TIMER(5) 510 #endif 511 512 /** 513 * omap_timer_init - build and register timer device with an 514 * associated timer hwmod 515 * @oh: timer hwmod pointer to be used to build timer device 516 * @user: parameter that can be passed from calling hwmod API 517 * 518 * Called by omap_hwmod_for_each_by_class to register each of the timer 519 * devices present in the system. The number of timer devices is known 520 * by parsing through the hwmod database for a given class name. At the 521 * end of function call memory is allocated for timer device and it is 522 * registered to the framework ready to be proved by the driver. 523 */ 524 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) 525 { 526 int id; 527 int ret = 0; 528 char *name = "omap_timer"; 529 struct dmtimer_platform_data *pdata; 530 struct platform_device *pdev; 531 struct omap_timer_capability_dev_attr *timer_dev_attr; 532 533 pr_debug("%s: %s\n", __func__, oh->name); 534 535 /* on secure device, do not register secure timer */ 536 timer_dev_attr = oh->dev_attr; 537 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) 538 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) 539 return ret; 540 541 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 542 if (!pdata) { 543 pr_err("%s: No memory for [%s]\n", __func__, oh->name); 544 return -ENOMEM; 545 } 546 547 /* 548 * Extract the IDs from name field in hwmod database 549 * and use the same for constructing ids' for the 550 * timer devices. In a way, we are avoiding usage of 551 * static variable witin the function to do the same. 552 * CAUTION: We have to be careful and make sure the 553 * name in hwmod database does not change in which case 554 * we might either make corresponding change here or 555 * switch back static variable mechanism. 556 */ 557 sscanf(oh->name, "timer%2d", &id); 558 559 if (timer_dev_attr) 560 pdata->timer_capability = timer_dev_attr->timer_capability; 561 562 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 563 NULL, 0, 0); 564 565 if (IS_ERR(pdev)) { 566 pr_err("%s: Can't build omap_device for %s: %s.\n", 567 __func__, name, oh->name); 568 ret = -EINVAL; 569 } 570 571 kfree(pdata); 572 573 return ret; 574 } 575 576 /** 577 * omap2_dm_timer_init - top level regular device initialization 578 * 579 * Uses dedicated hwmod api to parse through hwmod database for 580 * given class name and then build and register the timer device. 581 */ 582 static int __init omap2_dm_timer_init(void) 583 { 584 int ret; 585 586 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); 587 if (unlikely(ret)) { 588 pr_err("%s: device registration failed.\n", __func__); 589 return -EINVAL; 590 } 591 592 return 0; 593 } 594 arch_initcall(omap2_dm_timer_init); 595 596 /** 597 * omap2_override_clocksource - clocksource override with user configuration 598 * 599 * Allows user to override default clocksource, using kernel parameter 600 * clocksource="gp_timer" (For all OMAP2PLUS architectures) 601 * 602 * Note that, here we are using same standard kernel parameter "clocksource=", 603 * and not introducing any OMAP specific interface. 604 */ 605 static int __init omap2_override_clocksource(char *str) 606 { 607 if (!str) 608 return 0; 609 /* 610 * For OMAP architecture, we only have two options 611 * - sync_32k (default) 612 * - gp_timer (sys_clk based) 613 */ 614 if (!strcmp(str, "gp_timer")) 615 use_gptimer_clksrc = true; 616 617 return 0; 618 } 619 early_param("clocksource", omap2_override_clocksource); 620