xref: /openbmc/linux/arch/arm/mach-omap2/sram243x.S (revision 95e9fd10) 
1/*
2 * linux/arch/arm/mach-omap2/sram243x.S
3 *
4 * Omap2 specific functions that need to be run in internal SRAM
5 *
6 * (C) Copyright 2004
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 * Richard Woodruff notes that any changes to this code must be carefully
26 * audited and tested to ensure that they don't cause a TLB miss while
27 * the SDRAM is inaccessible.  Such a situation will crash the system
28 * since it will cause the ARM MMU to attempt to walk the page tables.
29 * These crashes may be intermittent.
30 */
31#include <linux/linkage.h>
32
33#include <asm/assembler.h>
34
35#include <mach/hardware.h>
36
37#include "iomap.h"
38#include "prm2xxx_3xxx.h"
39#include "cm2xxx_3xxx.h"
40#include "sdrc.h"
41
42	.text
43
44	.align	3
45ENTRY(omap243x_sram_ddr_init)
46	stmfd	sp!, {r0 - r12, lr}	@ save registers on stack
47
48	mov	r12, r2			@ capture CS1 vs CS0
49	mov	r8, r3			@ capture force parameter
50
51	/* frequency shift down */
52	ldr	r2, omap243x_sdi_cm_clksel2_pll	@ get address of dpllout reg
53	mov	r3, #0x1		@ value for 1x operation
54	str	r3, [r2]		@ go to L1-freq operation
55
56	/* voltage shift down */
57	mov r9, #0x1			@ set up for L1 voltage call
58	bl voltage_shift		@ go drop voltage
59
60	/* dll lock mode */
61	ldr	r11, omap243x_sdi_sdrc_dlla_ctrl	@ addr of dlla ctrl
62	ldr	r10, [r11]		@ get current val
63	cmp	r12, #0x1		@ cs1 base (2422 es2.05/1)
64	addeq	r11, r11, #0x8		@ if cs1 base, move to DLLB
65	mvn	r9, #0x4		@ mask to get clear bit2
66	and	r10, r10, r9		@ clear bit2 for lock mode.
67	orr	r10, r10, #0x8		@ make sure DLL on (es2 bit pos)
68	orr	r10, r10, #0x2		@ 90 degree phase for all below 133Mhz
69	str	r10, [r11]		@ commit to DLLA_CTRL
70	bl	i_dll_wait		@ wait for dll to lock
71
72	/* get dll value */
73	add	r11, r11, #0x4		@ get addr of status reg
74	ldr	r10, [r11]		@ get locked value
75
76	/* voltage shift up */
77	mov r9, #0x0			@ shift back to L0-voltage
78	bl voltage_shift		@ go raise voltage
79
80	/* frequency shift up */
81	mov	r3, #0x2		@ value for 2x operation
82	str	r3, [r2]		@ go to L0-freq operation
83
84	/* reset entry mode for dllctrl */
85	sub	r11, r11, #0x4		@ move from status to ctrl
86	cmp	r12, #0x1		@ normalize if cs1 based
87	subeq	r11, r11, #0x8		@ possibly back to DLLA
88	cmp	r8, #0x1		@ if forced unlock exit
89	orreq	r1, r1, #0x4		@ make sure exit with unlocked value
90	str	r1, [r11]		@ restore DLLA_CTRL high value
91	add	r11, r11, #0x8		@ move to DLLB_CTRL addr
92	str	r1, [r11]		@ set value DLLB_CTRL
93	bl	i_dll_wait		@ wait for possible lock
94
95	/* set up for return, DDR should be good */
96	str r10, [r0]			@ write dll_status and return counter
97	ldmfd	sp!, {r0 - r12, pc}	@ restore regs and return
98
99	/* ensure the DLL has relocked */
100i_dll_wait:
101	mov	r4, #0x800		@ delay DLL relock, min 0x400 L3 clocks
102i_dll_delay:
103	subs	r4, r4, #0x1
104	bne	i_dll_delay
105	mov	pc, lr
106
107	/*
108	 * shift up or down voltage, use R9 as input to tell level.
109	 * wait for it to finish, use 32k sync counter, 1tick=31uS.
110	 */
111voltage_shift:
112	ldr	r4, omap243x_sdi_prcm_voltctrl	@ get addr of volt ctrl.
113	ldr	r5, [r4]		@ get value.
114	ldr	r6, prcm_mask_val	@ get value of mask
115	and	r5, r5, r6		@ apply mask to clear bits
116	orr	r5, r5, r9		@ bulld value for L0/L1-volt operation.
117	str	r5, [r4]		@ set up for change.
118	mov	r3, #0x4000		@ get val for force
119	orr	r5, r5, r3		@ build value for force
120	str	r5, [r4]		@ Force transition to L1
121
122	ldr	r3, omap243x_sdi_timer_32ksynct_cr	@ get addr of counter
123	ldr	r5, [r3]		@ get value
124	add	r5, r5, #0x3		@ give it at most 93uS
125volt_delay:
126	ldr	r7, [r3]		@ get timer value
127	cmp	r5, r7			@ time up?
128	bhi	volt_delay		@ not yet->branch
129	mov	pc, lr			@ back to caller.
130
131omap243x_sdi_cm_clksel2_pll:
132	.word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
133omap243x_sdi_sdrc_dlla_ctrl:
134	.word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
135omap243x_sdi_prcm_voltctrl:
136	.word OMAP2430_PRCM_VOLTCTRL
137prcm_mask_val:
138	.word 0xFFFF3FFC
139omap243x_sdi_timer_32ksynct_cr:
140	.word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
141ENTRY(omap243x_sram_ddr_init_sz)
142	.word	. - omap243x_sram_ddr_init
143
144/*
145 * Reprograms memory timings.
146 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
147 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
148 */
149	.align	3
150ENTRY(omap243x_sram_reprogram_sdrc)
151	stmfd	sp!, {r0 - r10, lr}	@ save registers on stack
152	mov	r3, #0x0		@ clear for mrc call
153	mcr	p15, 0, r3, c7, c10, 4	@ memory barrier, finish ARM SDR/DDR
154	nop
155	nop
156	ldr	r6, omap243x_srs_sdrc_rfr_ctrl	@ get addr of refresh reg
157	ldr	r5, [r6]		@ get value
158	mov	r5, r5, lsr #8		@ isolate rfr field and drop burst
159
160	cmp	r0, #0x1		@ going to half speed?
161	movne	r9, #0x0		@ if up set flag up for pre up, hi volt
162
163	blne	voltage_shift_c		@ adjust voltage
164
165	cmp	r0, #0x1		@ going to half speed (post branch link)
166	moveq	r5, r5, lsr #1		@ divide by 2 if to half
167	movne	r5, r5, lsl #1		@ mult by 2 if to full
168	mov	r5, r5, lsl #8		@ put rfr field back into place
169	add	r5, r5, #0x1		@ turn on burst of 1
170	ldr	r4, omap243x_srs_cm_clksel2_pll	@ get address of out reg
171	ldr	r3, [r4]		@ get curr value
172	orr	r3, r3, #0x3
173	bic	r3, r3, #0x3		@ clear lower bits
174	orr	r3, r3, r0		@ new state value
175	str	r3, [r4]		@ set new state (pll/x, x=1 or 2)
176	nop
177	nop
178
179	moveq	r9, #0x1		@ if speed down, post down, drop volt
180	bleq	voltage_shift_c
181
182	mcr	p15, 0, r3, c7, c10, 4	@ memory barrier
183	str	r5, [r6]		@ set new RFR_1 value
184	add	r6, r6, #0x30		@ get RFR_2 addr
185	str	r5, [r6]		@ set RFR_2
186	nop
187	cmp	r2, #0x1		@ (SDR or DDR) do we need to adjust DLL
188	bne	freq_out		@ leave if SDR, no DLL function
189
190	/* With DDR, we need to take care of the DLL for the frequency change */
191	ldr	r2, omap243x_srs_sdrc_dlla_ctrl	@ addr of dlla ctrl
192	str	r1, [r2]		@ write out new SDRC_DLLA_CTRL
193	add	r2, r2, #0x8		@ addr to SDRC_DLLB_CTRL
194	str	r1, [r2]		@ commit to SDRC_DLLB_CTRL
195	mov	r1, #0x2000		@ wait DLL relock, min 0x400 L3 clocks
196dll_wait:
197	subs	r1, r1, #0x1
198	bne	dll_wait
199freq_out:
200	ldmfd	sp!, {r0 - r10, pc}	@ restore regs and return
201
202    /*
203     * shift up or down voltage, use R9 as input to tell level.
204     *	wait for it to finish, use 32k sync counter, 1tick=31uS.
205     */
206voltage_shift_c:
207	ldr	r10, omap243x_srs_prcm_voltctrl	@ get addr of volt ctrl
208	ldr	r8, [r10]		@ get value
209	ldr	r7, ddr_prcm_mask_val	@ get value of mask
210	and	r8, r8, r7		@ apply mask to clear bits
211	orr	r8, r8, r9		@ bulld value for L0/L1-volt operation.
212	str	r8, [r10]		@ set up for change.
213	mov	r7, #0x4000		@ get val for force
214	orr	r8, r8, r7		@ build value for force
215	str	r8, [r10]		@ Force transition to L1
216
217	ldr	r10, omap243x_srs_timer_32ksynct	@ get addr of counter
218	ldr	r8, [r10]		@ get value
219	add	r8, r8, #0x2		@ give it at most 62uS (min 31+)
220volt_delay_c:
221	ldr	r7, [r10]		@ get timer value
222	cmp	r8, r7			@ time up?
223	bhi	volt_delay_c		@ not yet->branch
224	mov	pc, lr			@ back to caller
225
226omap243x_srs_cm_clksel2_pll:
227	.word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
228omap243x_srs_sdrc_dlla_ctrl:
229	.word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
230omap243x_srs_sdrc_rfr_ctrl:
231	.word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
232omap243x_srs_prcm_voltctrl:
233	.word OMAP2430_PRCM_VOLTCTRL
234ddr_prcm_mask_val:
235	.word 0xFFFF3FFC
236omap243x_srs_timer_32ksynct:
237	.word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
238
239ENTRY(omap243x_sram_reprogram_sdrc_sz)
240	.word	. - omap243x_sram_reprogram_sdrc
241
242/*
243 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
244 */
245	.align	3
246ENTRY(omap243x_sram_set_prcm)
247	stmfd	sp!, {r0-r12, lr}	@ regs to stack
248	adr	r4, pbegin		@ addr of preload start
249	adr	r8, pend		@ addr of preload end
250	mcrr	p15, 1, r8, r4, c12	@ preload into icache
251pbegin:
252	/* move into fast relock bypass */
253	ldr	r8, omap243x_ssp_pll_ctl	@ get addr
254	ldr	r5, [r8]		@ get val
255	mvn	r6, #0x3		@ clear mask
256	and	r5, r5, r6		@ clear field
257	orr	r7, r5, #0x2		@ fast relock val
258	str	r7, [r8]		@ go to fast relock
259	ldr	r4, omap243x_ssp_pll_stat	@ addr of stat
260block:
261	/* wait for bypass */
262	ldr	r8, [r4]		@ stat value
263	and	r8, r8, #0x3		@ mask for stat
264	cmp	r8, #0x1		@ there yet
265	bne	block			@ loop if not
266
267	/* set new dpll dividers _after_ in bypass */
268	ldr	r4, omap243x_ssp_pll_div	@ get addr
269	str	r0, [r4]		@ set dpll ctrl val
270
271	ldr	r4, omap243x_ssp_set_config	@ get addr
272	mov	r8, #1			@ valid cfg msk
273	str	r8, [r4]		@ make dividers take
274
275	mov	r4, #100		@ dead spin a bit
276wait_a_bit:
277	subs	r4, r4, #1		@ dec loop
278	bne	wait_a_bit		@ delay done?
279
280	/* check if staying in bypass */
281	cmp	r2, #0x1		@ stay in bypass?
282	beq	pend			@ jump over dpll relock
283
284	/* relock DPLL with new vals */
285	ldr	r5, omap243x_ssp_pll_stat	@ get addr
286	ldr	r4, omap243x_ssp_pll_ctl	@ get addr
287	orr	r8, r7, #0x3		@ val for lock dpll
288	str	r8, [r4]		@ set val
289	mov	r0, #1000		@ dead spin a bit
290wait_more:
291	subs	r0, r0, #1		@ dec loop
292	bne	wait_more		@ delay done?
293wait_lock:
294	ldr	r8, [r5]		@ get lock val
295	and	r8, r8, #3		@ isolate field
296	cmp	r8, #2			@ locked?
297	bne	wait_lock		@ wait if not
298pend:
299	/* update memory timings & briefly lock dll */
300	ldr	r4, omap243x_ssp_sdrc_rfr	@ get addr
301	str	r1, [r4]		@ update refresh timing
302	ldr	r11, omap243x_ssp_dlla_ctrl	@ get addr of DLLA ctrl
303	ldr	r10, [r11]		@ get current val
304	mvn	r9, #0x4		@ mask to get clear bit2
305	and	r10, r10, r9		@ clear bit2 for lock mode
306	orr	r10, r10, #0x8		@ make sure DLL on (es2 bit pos)
307	str	r10, [r11]		@ commit to DLLA_CTRL
308	add	r11, r11, #0x8		@ move to dllb
309	str	r10, [r11]		@ hit DLLB also
310
311	mov	r4, #0x800		@ relock time (min 0x400 L3 clocks)
312wait_dll_lock:
313	subs	r4, r4, #0x1
314	bne	wait_dll_lock
315	nop
316	ldmfd	sp!, {r0-r12, pc}	@ restore regs and return
317
318omap243x_ssp_set_config:
319	.word OMAP2430_PRCM_CLKCFG_CTRL
320omap243x_ssp_pll_ctl:
321	.word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
322omap243x_ssp_pll_stat:
323	.word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
324omap243x_ssp_pll_div:
325	.word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
326omap243x_ssp_sdrc_rfr:
327	.word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
328omap243x_ssp_dlla_ctrl:
329	.word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
330
331ENTRY(omap243x_sram_set_prcm_sz)
332	.word	. - omap243x_sram_set_prcm
333