1 /* 2 * 3 * OMAP SRAM detection and management 4 * 5 * Copyright (C) 2005 Nokia Corporation 6 * Written by Tony Lindgren <tony@atomide.com> 7 * 8 * Copyright (C) 2009-2012 Texas Instruments 9 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 21 #include <asm/fncpy.h> 22 #include <asm/tlb.h> 23 #include <asm/cacheflush.h> 24 25 #include <asm/mach/map.h> 26 27 #include "soc.h" 28 #include "iomap.h" 29 #include "prm2xxx_3xxx.h" 30 #include "sdrc.h" 31 #include "sram.h" 32 33 #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800) 34 #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000) 35 36 #define SRAM_BOOTLOADER_SZ 0x00 37 38 #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048) 39 #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050) 40 #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058) 41 42 #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848) 43 #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850) 44 #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858) 45 #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880) 46 #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048) 47 48 #define GP_DEVICE 0x300 49 50 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) 51 52 static unsigned long omap_sram_start; 53 static unsigned long omap_sram_skip; 54 static unsigned long omap_sram_size; 55 56 /* 57 * Depending on the target RAMFS firewall setup, the public usable amount of 58 * SRAM varies. The default accessible size for all device types is 2k. A GP 59 * device allows ARM11 but not other initiators for full size. This 60 * functionality seems ok until some nice security API happens. 61 */ 62 static int is_sram_locked(void) 63 { 64 if (OMAP2_DEVICE_TYPE_GP == omap_type()) { 65 /* RAMFW: R/W access to all initiators for all qualifier sets */ 66 if (cpu_is_omap242x()) { 67 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ 68 writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ 69 writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */ 70 } 71 if (cpu_is_omap34xx()) { 72 writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */ 73 writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */ 74 writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */ 75 writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2); 76 writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0); 77 } 78 return 0; 79 } else 80 return 1; /* assume locked with no PPA or security driver */ 81 } 82 83 /* 84 * The amount of SRAM depends on the core type. 85 * Note that we cannot try to test for SRAM here because writes 86 * to secure SRAM will hang the system. Also the SRAM is not 87 * yet mapped at this point. 88 */ 89 static void __init omap_detect_sram(void) 90 { 91 omap_sram_skip = SRAM_BOOTLOADER_SZ; 92 if (is_sram_locked()) { 93 if (cpu_is_omap34xx()) { 94 omap_sram_start = OMAP3_SRAM_PUB_PA; 95 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || 96 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { 97 omap_sram_size = 0x7000; /* 28K */ 98 omap_sram_skip += SZ_16K; 99 } else { 100 omap_sram_size = 0x8000; /* 32K */ 101 } 102 } else { 103 omap_sram_start = OMAP2_SRAM_PUB_PA; 104 omap_sram_size = 0x800; /* 2K */ 105 } 106 } else { 107 if (cpu_is_omap34xx()) { 108 omap_sram_start = OMAP3_SRAM_PA; 109 omap_sram_size = 0x10000; /* 64K */ 110 } else { 111 omap_sram_start = OMAP2_SRAM_PA; 112 if (cpu_is_omap242x()) 113 omap_sram_size = 0xa0000; /* 640K */ 114 else if (cpu_is_omap243x()) 115 omap_sram_size = 0x10000; /* 64K */ 116 } 117 } 118 } 119 120 /* 121 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early. 122 */ 123 static void __init omap2_map_sram(void) 124 { 125 int cached = 1; 126 127 if (cpu_is_omap34xx()) { 128 /* 129 * SRAM must be marked as non-cached on OMAP3 since the 130 * CORE DPLL M2 divider change code (in SRAM) runs with the 131 * SDRAM controller disabled, and if it is marked cached, 132 * the ARM may attempt to write cache lines back to SDRAM 133 * which will cause the system to hang. 134 */ 135 cached = 0; 136 } 137 138 omap_map_sram(omap_sram_start, omap_sram_size, 139 omap_sram_skip, cached); 140 } 141 142 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 143 u32 base_cs, u32 force_unlock); 144 145 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 146 u32 base_cs, u32 force_unlock) 147 { 148 BUG_ON(!_omap2_sram_ddr_init); 149 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl, 150 base_cs, force_unlock); 151 } 152 153 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val, 154 u32 mem_type); 155 156 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type) 157 { 158 BUG_ON(!_omap2_sram_reprogram_sdrc); 159 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type); 160 } 161 162 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 163 164 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) 165 { 166 BUG_ON(!_omap2_set_prcm); 167 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); 168 } 169 170 #ifdef CONFIG_SOC_OMAP2420 171 static int __init omap242x_sram_init(void) 172 { 173 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init, 174 omap242x_sram_ddr_init_sz); 175 176 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc, 177 omap242x_sram_reprogram_sdrc_sz); 178 179 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm, 180 omap242x_sram_set_prcm_sz); 181 182 return 0; 183 } 184 #else 185 static inline int omap242x_sram_init(void) 186 { 187 return 0; 188 } 189 #endif 190 191 #ifdef CONFIG_SOC_OMAP2430 192 static int __init omap243x_sram_init(void) 193 { 194 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init, 195 omap243x_sram_ddr_init_sz); 196 197 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc, 198 omap243x_sram_reprogram_sdrc_sz); 199 200 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm, 201 omap243x_sram_set_prcm_sz); 202 203 return 0; 204 } 205 #else 206 static inline int omap243x_sram_init(void) 207 { 208 return 0; 209 } 210 #endif 211 212 #ifdef CONFIG_ARCH_OMAP3 213 214 void omap3_sram_restore_context(void) 215 { 216 omap_sram_reset(); 217 218 omap_push_sram_idle(); 219 } 220 221 static inline int omap34xx_sram_init(void) 222 { 223 omap3_sram_restore_context(); 224 return 0; 225 } 226 #else 227 static inline int omap34xx_sram_init(void) 228 { 229 return 0; 230 } 231 #endif /* CONFIG_ARCH_OMAP3 */ 232 233 int __init omap_sram_init(void) 234 { 235 omap_detect_sram(); 236 omap2_map_sram(); 237 238 if (cpu_is_omap242x()) 239 omap242x_sram_init(); 240 else if (cpu_is_omap2430()) 241 omap243x_sram_init(); 242 else if (cpu_is_omap34xx()) 243 omap34xx_sram_init(); 244 245 return 0; 246 } 247