18bd22949SKevin Hilman/* 28bd22949SKevin Hilman * linux/arch/arm/mach-omap2/sleep.S 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * (C) Copyright 2007 58bd22949SKevin Hilman * Texas Instruments 68bd22949SKevin Hilman * Karthik Dasu <karthik-dp@ti.com> 78bd22949SKevin Hilman * 88bd22949SKevin Hilman * (C) Copyright 2004 98bd22949SKevin Hilman * Texas Instruments, <www.ti.com> 108bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 118bd22949SKevin Hilman * 128bd22949SKevin Hilman * This program is free software; you can redistribute it and/or 138bd22949SKevin Hilman * modify it under the terms of the GNU General Public License as 148bd22949SKevin Hilman * published by the Free Software Foundation; either version 2 of 158bd22949SKevin Hilman * the License, or (at your option) any later version. 168bd22949SKevin Hilman * 178bd22949SKevin Hilman * This program is distributed in the hope that it will be useful, 188bd22949SKevin Hilman * but WITHOUT ANY WARRANTY; without even the implied warranty of 198bd22949SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 208bd22949SKevin Hilman * GNU General Public License for more details. 218bd22949SKevin Hilman * 228bd22949SKevin Hilman * You should have received a copy of the GNU General Public License 238bd22949SKevin Hilman * along with this program; if not, write to the Free Software 248bd22949SKevin Hilman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 258bd22949SKevin Hilman * MA 02111-1307 USA 268bd22949SKevin Hilman */ 278bd22949SKevin Hilman#include <linux/linkage.h> 288bd22949SKevin Hilman#include <asm/assembler.h> 29b4b36fd9SJean Pihet#include <plat/sram.h> 308bd22949SKevin Hilman#include <mach/io.h> 318bd22949SKevin Hilman 3289139dceSPeter 'p2' De Schrijver#include "cm.h" 338bd22949SKevin Hilman#include "prm.h" 348bd22949SKevin Hilman#include "sdrc.h" 354814ced5SPaul Walmsley#include "control.h" 368bd22949SKevin Hilman 37fe360e1cSJean Pihet/* 38fe360e1cSJean Pihet * Registers access definitions 39fe360e1cSJean Pihet */ 40fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_OFFS 0xc 41fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ 42fe360e1cSJean Pihet (SDRC_SCRATCHPAD_SEM_OFFS) 43fe360e1cSJean Pihet#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ 44fe360e1cSJean Pihet OMAP3430_PM_PREPWSTST 4537903009SAbhijit Pagare#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 4689139dceSPeter 'p2' De Schrijver#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 479d93b8a2SPeter 'p2' De Schrijver#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) 48fe360e1cSJean Pihet#define SRAM_BASE_P OMAP3_SRAM_PA 49fe360e1cSJean Pihet#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS 50fe360e1cSJean Pihet#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ 51fe360e1cSJean Pihet OMAP36XX_CONTROL_MEM_RTA_CTRL) 52fe360e1cSJean Pihet 53fe360e1cSJean Pihet/* Move this as correct place is available */ 54fe360e1cSJean Pihet#define SCRATCHPAD_MEM_OFFS 0x310 55fe360e1cSJean Pihet#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ 56fe360e1cSJean Pihet OMAP343X_CONTROL_MEM_WKUP +\ 57fe360e1cSJean Pihet SCRATCHPAD_MEM_OFFS) 588bd22949SKevin Hilman#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 590795a75aSTero Kristo#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 600795a75aSTero Kristo#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 610795a75aSTero Kristo#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) 620795a75aSTero Kristo#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) 630795a75aSTero Kristo#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) 640795a75aSTero Kristo#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) 650795a75aSTero Kristo#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) 6689139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 6789139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 688bd22949SKevin Hilman 69a89b6f00SRajendra Nayak 70d3cdfd2aSJean Pihet/* 71d3cdfd2aSJean Pihet * API functions 72d3cdfd2aSJean Pihet */ 73a89b6f00SRajendra Nayak 74a89b6f00SRajendra Nayak .text 758bd22949SKevin Hilman/* Function call to get the restore pointer for resume from OFF */ 768bd22949SKevin HilmanENTRY(get_restore_pointer) 778bd22949SKevin Hilman stmfd sp!, {lr} @ save registers on stack 788bd22949SKevin Hilman adr r0, restore 798bd22949SKevin Hilman ldmfd sp!, {pc} @ restore regs and return 808bd22949SKevin HilmanENTRY(get_restore_pointer_sz) 810795a75aSTero Kristo .word . - get_restore_pointer 82458e999eSNishanth Menon .text 83458e999eSNishanth Menon/* Function call to get the restore pointer for 3630 resume from OFF */ 84458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer) 85458e999eSNishanth Menon stmfd sp!, {lr} @ save registers on stack 86458e999eSNishanth Menon adr r0, restore_3630 87458e999eSNishanth Menon ldmfd sp!, {pc} @ restore regs and return 88458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer_sz) 89458e999eSNishanth Menon .word . - get_omap3630_restore_pointer 900795a75aSTero Kristo 910795a75aSTero Kristo .text 92c4236d2eSPeter 'p2' De Schrijver/* 93c4236d2eSPeter 'p2' De Schrijver * L2 cache needs to be toggled for stable OFF mode functionality on 3630. 94c4236d2eSPeter 'p2' De Schrijver * This function sets up a fflag that will allow for this toggling to take 95c4236d2eSPeter 'p2' De Schrijver * place on 3630. Hopefully some version in the future maynot need this 96c4236d2eSPeter 'p2' De Schrijver */ 97c4236d2eSPeter 'p2' De SchrijverENTRY(enable_omap3630_toggle_l2_on_restore) 98c4236d2eSPeter 'p2' De Schrijver stmfd sp!, {lr} @ save registers on stack 99c4236d2eSPeter 'p2' De Schrijver /* Setup so that we will disable and enable l2 */ 100c4236d2eSPeter 'p2' De Schrijver mov r1, #0x1 101c4236d2eSPeter 'p2' De Schrijver str r1, l2dis_3630 102c4236d2eSPeter 'p2' De Schrijver ldmfd sp!, {pc} @ restore regs and return 103c4236d2eSPeter 'p2' De Schrijver 104c4236d2eSPeter 'p2' De Schrijver .text 1050795a75aSTero Kristo/* Function call to get the restore pointer for for ES3 to resume from OFF */ 1060795a75aSTero KristoENTRY(get_es3_restore_pointer) 1070795a75aSTero Kristo stmfd sp!, {lr} @ save registers on stack 1080795a75aSTero Kristo adr r0, restore_es3 1090795a75aSTero Kristo ldmfd sp!, {pc} @ restore regs and return 1100795a75aSTero KristoENTRY(get_es3_restore_pointer_sz) 1110795a75aSTero Kristo .word . - get_es3_restore_pointer 1120795a75aSTero Kristo 1130795a75aSTero KristoENTRY(es3_sdrc_fix) 1140795a75aSTero Kristo ldr r4, sdrc_syscfg @ get config addr 1150795a75aSTero Kristo ldr r5, [r4] @ get value 1160795a75aSTero Kristo tst r5, #0x100 @ is part access blocked 1170795a75aSTero Kristo it eq 1180795a75aSTero Kristo biceq r5, r5, #0x100 @ clear bit if set 1190795a75aSTero Kristo str r5, [r4] @ write back change 1200795a75aSTero Kristo ldr r4, sdrc_mr_0 @ get config addr 1210795a75aSTero Kristo ldr r5, [r4] @ get value 1220795a75aSTero Kristo str r5, [r4] @ write back change 1230795a75aSTero Kristo ldr r4, sdrc_emr2_0 @ get config addr 1240795a75aSTero Kristo ldr r5, [r4] @ get value 1250795a75aSTero Kristo str r5, [r4] @ write back change 1260795a75aSTero Kristo ldr r4, sdrc_manual_0 @ get config addr 1270795a75aSTero Kristo mov r5, #0x2 @ autorefresh command 1280795a75aSTero Kristo str r5, [r4] @ kick off refreshes 1290795a75aSTero Kristo ldr r4, sdrc_mr_1 @ get config addr 1300795a75aSTero Kristo ldr r5, [r4] @ get value 1310795a75aSTero Kristo str r5, [r4] @ write back change 1320795a75aSTero Kristo ldr r4, sdrc_emr2_1 @ get config addr 1330795a75aSTero Kristo ldr r5, [r4] @ get value 1340795a75aSTero Kristo str r5, [r4] @ write back change 1350795a75aSTero Kristo ldr r4, sdrc_manual_1 @ get config addr 1360795a75aSTero Kristo mov r5, #0x2 @ autorefresh command 1370795a75aSTero Kristo str r5, [r4] @ kick off refreshes 1380795a75aSTero Kristo bx lr 1390795a75aSTero Kristosdrc_syscfg: 1400795a75aSTero Kristo .word SDRC_SYSCONFIG_P 1410795a75aSTero Kristosdrc_mr_0: 1420795a75aSTero Kristo .word SDRC_MR_0_P 1430795a75aSTero Kristosdrc_emr2_0: 1440795a75aSTero Kristo .word SDRC_EMR2_0_P 1450795a75aSTero Kristosdrc_manual_0: 1460795a75aSTero Kristo .word SDRC_MANUAL_0_P 1470795a75aSTero Kristosdrc_mr_1: 1480795a75aSTero Kristo .word SDRC_MR_1_P 1490795a75aSTero Kristosdrc_emr2_1: 1500795a75aSTero Kristo .word SDRC_EMR2_1_P 1510795a75aSTero Kristosdrc_manual_1: 1520795a75aSTero Kristo .word SDRC_MANUAL_1_P 1530795a75aSTero KristoENTRY(es3_sdrc_fix_sz) 1540795a75aSTero Kristo .word . - es3_sdrc_fix 15527d59a4aSTero Kristo 15627d59a4aSTero Kristo/* Function to call rom code to save secure ram context */ 15727d59a4aSTero KristoENTRY(save_secure_ram_context) 15827d59a4aSTero Kristo stmfd sp!, {r1-r12, lr} @ save registers on stack 159d3cdfd2aSJean Pihet 16027d59a4aSTero Kristo adr r3, api_params @ r3 points to parameters 16127d59a4aSTero Kristo str r0, [r3,#0x4] @ r0 has sdram address 16227d59a4aSTero Kristo ldr r12, high_mask 16327d59a4aSTero Kristo and r3, r3, r12 16427d59a4aSTero Kristo ldr r12, sram_phy_addr_mask 16527d59a4aSTero Kristo orr r3, r3, r12 16627d59a4aSTero Kristo mov r0, #25 @ set service ID for PPA 16727d59a4aSTero Kristo mov r12, r0 @ copy secure service ID in r12 16827d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 169ba50ea7eSKalle Jokiniemi mov r2, #4 @ set some flags in r2, r6 17027d59a4aSTero Kristo mov r6, #0xff 17127d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 17227d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 17327d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 17427d59a4aSTero Kristo nop 17527d59a4aSTero Kristo nop 17627d59a4aSTero Kristo nop 17727d59a4aSTero Kristo nop 17827d59a4aSTero Kristo ldmfd sp!, {r1-r12, pc} 17927d59a4aSTero Kristosram_phy_addr_mask: 18027d59a4aSTero Kristo .word SRAM_BASE_P 18127d59a4aSTero Kristohigh_mask: 18227d59a4aSTero Kristo .word 0xffff 18327d59a4aSTero Kristoapi_params: 18427d59a4aSTero Kristo .word 0x4, 0x0, 0x0, 0x1, 0x1 18527d59a4aSTero KristoENTRY(save_secure_ram_context_sz) 18627d59a4aSTero Kristo .word . - save_secure_ram_context 18727d59a4aSTero Kristo 1888bd22949SKevin Hilman/* 1898bd22949SKevin Hilman * Forces OMAP into idle state 1908bd22949SKevin Hilman * 1918bd22949SKevin Hilman * omap34xx_suspend() - This bit of code just executes the WFI 1928bd22949SKevin Hilman * for normal idles. 1938bd22949SKevin Hilman * 1948bd22949SKevin Hilman * Note: This code get's copied to internal SRAM at boot. When the OMAP 1958bd22949SKevin Hilman * wakes up it continues execution at the point it went to sleep. 1968bd22949SKevin Hilman */ 1978bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend) 1988bd22949SKevin Hilman stmfd sp!, {r0-r12, lr} @ save registers on stack 199d3cdfd2aSJean Pihet 2008bd22949SKevin Hilman /* r0 contains restore pointer in sdram */ 2018bd22949SKevin Hilman /* r1 contains information about saving context */ 2028bd22949SKevin Hilman ldr r4, sdrc_power @ read the SDRC_POWER register 2038bd22949SKevin Hilman ldr r5, [r4] @ read the contents of SDRC_POWER 2048bd22949SKevin Hilman orr r5, r5, #0x40 @ enable self refresh on idle req 2058bd22949SKevin Hilman str r5, [r4] @ write back to SDRC_POWER register 2068bd22949SKevin Hilman 2078bd22949SKevin Hilman cmp r1, #0x0 2088bd22949SKevin Hilman /* If context save is required, do that and execute wfi */ 2098bd22949SKevin Hilman bne save_context_wfi 2108bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 2118bd22949SKevin Hilman mov r1, #0 2128bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 4 2138bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 5 2148bd22949SKevin Hilman 2158bd22949SKevin Hilman wfi @ wait for interrupt 2168bd22949SKevin Hilman 2178bd22949SKevin Hilman nop 2188bd22949SKevin Hilman nop 2198bd22949SKevin Hilman nop 2208bd22949SKevin Hilman nop 2218bd22949SKevin Hilman nop 2228bd22949SKevin Hilman nop 2238bd22949SKevin Hilman nop 2248bd22949SKevin Hilman nop 2258bd22949SKevin Hilman nop 2268bd22949SKevin Hilman nop 22789139dceSPeter 'p2' De Schrijver bl wait_sdrc_ok 2288bd22949SKevin Hilman 2298bd22949SKevin Hilman ldmfd sp!, {r0-r12, pc} @ restore regs and return 2300795a75aSTero Kristorestore_es3: 2310795a75aSTero Kristo ldr r5, pm_prepwstst_core_p 2320795a75aSTero Kristo ldr r4, [r5] 2330795a75aSTero Kristo and r4, r4, #0x3 2340795a75aSTero Kristo cmp r4, #0x0 @ Check if previous power state of CORE is OFF 2350795a75aSTero Kristo bne restore 2360795a75aSTero Kristo adr r0, es3_sdrc_fix 2370795a75aSTero Kristo ldr r1, sram_base 2380795a75aSTero Kristo ldr r2, es3_sdrc_fix_sz 2390795a75aSTero Kristo mov r2, r2, ror #2 2400795a75aSTero Kristocopy_to_sram: 2410795a75aSTero Kristo ldmia r0!, {r3} @ val = *src 2420795a75aSTero Kristo stmia r1!, {r3} @ *dst = val 2430795a75aSTero Kristo subs r2, r2, #0x1 @ num_words-- 2440795a75aSTero Kristo bne copy_to_sram 2450795a75aSTero Kristo ldr r1, sram_base 2460795a75aSTero Kristo blx r1 247458e999eSNishanth Menon b restore 248458e999eSNishanth Menon 249458e999eSNishanth Menonrestore_3630: 250458e999eSNishanth Menon ldr r1, pm_prepwstst_core_p 251458e999eSNishanth Menon ldr r2, [r1] 252458e999eSNishanth Menon and r2, r2, #0x3 253458e999eSNishanth Menon cmp r2, #0x0 @ Check if previous power state of CORE is OFF 254458e999eSNishanth Menon bne restore 255458e999eSNishanth Menon /* Disable RTA before giving control */ 256458e999eSNishanth Menon ldr r1, control_mem_rta 257458e999eSNishanth Menon mov r2, #OMAP36XX_RTA_DISABLE 258458e999eSNishanth Menon str r2, [r1] 259458e999eSNishanth Menon /* Fall thru for the remaining logic */ 2608bd22949SKevin Hilmanrestore: 2618bd22949SKevin Hilman /* Check what was the reason for mpu reset and store the reason in r9*/ 2628bd22949SKevin Hilman /* 1 - Only L1 and logic lost */ 2638bd22949SKevin Hilman /* 2 - Only L2 lost - In this case, we wont be here */ 2648bd22949SKevin Hilman /* 3 - Both L1 and L2 lost */ 2658bd22949SKevin Hilman ldr r1, pm_pwstctrl_mpu 2668bd22949SKevin Hilman ldr r2, [r1] 2678bd22949SKevin Hilman and r2, r2, #0x3 2688bd22949SKevin Hilman cmp r2, #0x0 @ Check if target power state was OFF or RET 2698bd22949SKevin Hilman moveq r9, #0x3 @ MPU OFF => L1 and L2 lost 2708bd22949SKevin Hilman movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation 2718bd22949SKevin Hilman bne logic_l1_restore 272c4236d2eSPeter 'p2' De Schrijver 273c4236d2eSPeter 'p2' De Schrijver ldr r0, l2dis_3630 274c4236d2eSPeter 'p2' De Schrijver cmp r0, #0x1 @ should we disable L2 on 3630? 275c4236d2eSPeter 'p2' De Schrijver bne skipl2dis 276c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r0, c1, c0, 1 277c4236d2eSPeter 'p2' De Schrijver bic r0, r0, #2 @ disable L2 cache 278c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r0, c1, c0, 1 279c4236d2eSPeter 'p2' De Schrijverskipl2dis: 28027d59a4aSTero Kristo ldr r0, control_stat 28127d59a4aSTero Kristo ldr r1, [r0] 28227d59a4aSTero Kristo and r1, #0x700 28327d59a4aSTero Kristo cmp r1, #0x300 28427d59a4aSTero Kristo beq l2_inv_gp 28527d59a4aSTero Kristo mov r0, #40 @ set service ID for PPA 28627d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 28727d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 28827d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 28927d59a4aSTero Kristo mov r6, #0xff 29027d59a4aSTero Kristo adr r3, l2_inv_api_params @ r3 points to dummy parameters 29127d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 29227d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 29327d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 29427d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 29527d59a4aSTero Kristo mov r0, #42 @ set service ID for PPA 29627d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 29727d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 29827d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 29927d59a4aSTero Kristo mov r6, #0xff 300a087cad9STero Kristo ldr r4, scratchpad_base 301a087cad9STero Kristo ldr r3, [r4, #0xBC] @ r3 points to parameters 30227d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 30327d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 30427d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 30527d59a4aSTero Kristo 30679dcfdd4STero Kristo#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 30779dcfdd4STero Kristo /* Restore L2 aux control register */ 30879dcfdd4STero Kristo @ set service ID for PPA 30979dcfdd4STero Kristo mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 31079dcfdd4STero Kristo mov r12, r0 @ copy service ID in r12 31179dcfdd4STero Kristo mov r1, #0 @ set task ID for ROM code in r1 31279dcfdd4STero Kristo mov r2, #4 @ set some flags in r2, r6 31379dcfdd4STero Kristo mov r6, #0xff 31479dcfdd4STero Kristo ldr r4, scratchpad_base 31579dcfdd4STero Kristo ldr r3, [r4, #0xBC] 31679dcfdd4STero Kristo adds r3, r3, #8 @ r3 points to parameters 31779dcfdd4STero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 31879dcfdd4STero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 31979dcfdd4STero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 32079dcfdd4STero Kristo#endif 32127d59a4aSTero Kristo b logic_l1_restore 32227d59a4aSTero Kristol2_inv_api_params: 32327d59a4aSTero Kristo .word 0x1, 0x00 32427d59a4aSTero Kristol2_inv_gp: 3258bd22949SKevin Hilman /* Execute smi to invalidate L2 cache */ 3268bd22949SKevin Hilman mov r12, #0x1 @ set up to invalide L2 3278bd22949SKevin Hilmansmi: .word 0xE1600070 @ Call SMI monitor (smieq) 32827d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 329a087cad9STero Kristo ldr r4, scratchpad_base 330a087cad9STero Kristo ldr r3, [r4,#0xBC] 331a087cad9STero Kristo ldr r0, [r3,#4] 33227d59a4aSTero Kristo mov r12, #0x3 33327d59a4aSTero Kristo .word 0xE1600070 @ Call SMI monitor (smieq) 33479dcfdd4STero Kristo ldr r4, scratchpad_base 33579dcfdd4STero Kristo ldr r3, [r4,#0xBC] 33679dcfdd4STero Kristo ldr r0, [r3,#12] 33779dcfdd4STero Kristo mov r12, #0x2 33879dcfdd4STero Kristo .word 0xE1600070 @ Call SMI monitor (smieq) 3398bd22949SKevin Hilmanlogic_l1_restore: 340c4236d2eSPeter 'p2' De Schrijver ldr r1, l2dis_3630 341c4236d2eSPeter 'p2' De Schrijver cmp r1, #0x1 @ Do we need to re-enable L2 on 3630? 342c4236d2eSPeter 'p2' De Schrijver bne skipl2reen 343c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r1, c1, c0, 1 344c4236d2eSPeter 'p2' De Schrijver orr r1, r1, #2 @ re-enable L2 cache 345c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r1, c1, c0, 1 346c4236d2eSPeter 'p2' De Schrijverskipl2reen: 3478bd22949SKevin Hilman mov r1, #0 3488bd22949SKevin Hilman /* Invalidate all instruction caches to PoU 3498bd22949SKevin Hilman * and flush branch target cache */ 3508bd22949SKevin Hilman mcr p15, 0, r1, c7, c5, 0 3518bd22949SKevin Hilman 3528bd22949SKevin Hilman ldr r4, scratchpad_base 3538bd22949SKevin Hilman ldr r3, [r4,#0xBC] 35479dcfdd4STero Kristo adds r3, r3, #16 3558bd22949SKevin Hilman ldmia r3!, {r4-r6} 3568bd22949SKevin Hilman mov sp, r4 3578bd22949SKevin Hilman msr spsr_cxsf, r5 3588bd22949SKevin Hilman mov lr, r6 3598bd22949SKevin Hilman 3608bd22949SKevin Hilman ldmia r3!, {r4-r9} 3618bd22949SKevin Hilman /* Coprocessor access Control Register */ 3628bd22949SKevin Hilman mcr p15, 0, r4, c1, c0, 2 3638bd22949SKevin Hilman 3648bd22949SKevin Hilman /* TTBR0 */ 3658bd22949SKevin Hilman MCR p15, 0, r5, c2, c0, 0 3668bd22949SKevin Hilman /* TTBR1 */ 3678bd22949SKevin Hilman MCR p15, 0, r6, c2, c0, 1 3688bd22949SKevin Hilman /* Translation table base control register */ 3698bd22949SKevin Hilman MCR p15, 0, r7, c2, c0, 2 3708bd22949SKevin Hilman /*domain access Control Register */ 3718bd22949SKevin Hilman MCR p15, 0, r8, c3, c0, 0 3728bd22949SKevin Hilman /* data fault status Register */ 3738bd22949SKevin Hilman MCR p15, 0, r9, c5, c0, 0 3748bd22949SKevin Hilman 3758bd22949SKevin Hilman ldmia r3!,{r4-r8} 3768bd22949SKevin Hilman /* instruction fault status Register */ 3778bd22949SKevin Hilman MCR p15, 0, r4, c5, c0, 1 3788bd22949SKevin Hilman /*Data Auxiliary Fault Status Register */ 3798bd22949SKevin Hilman MCR p15, 0, r5, c5, c1, 0 3808bd22949SKevin Hilman /*Instruction Auxiliary Fault Status Register*/ 3818bd22949SKevin Hilman MCR p15, 0, r6, c5, c1, 1 3828bd22949SKevin Hilman /*Data Fault Address Register */ 3838bd22949SKevin Hilman MCR p15, 0, r7, c6, c0, 0 3848bd22949SKevin Hilman /*Instruction Fault Address Register*/ 3858bd22949SKevin Hilman MCR p15, 0, r8, c6, c0, 2 3868bd22949SKevin Hilman ldmia r3!,{r4-r7} 3878bd22949SKevin Hilman 3888bd22949SKevin Hilman /* user r/w thread and process ID */ 3898bd22949SKevin Hilman MCR p15, 0, r4, c13, c0, 2 3908bd22949SKevin Hilman /* user ro thread and process ID */ 3918bd22949SKevin Hilman MCR p15, 0, r5, c13, c0, 3 3928bd22949SKevin Hilman /*Privileged only thread and process ID */ 3938bd22949SKevin Hilman MCR p15, 0, r6, c13, c0, 4 3948bd22949SKevin Hilman /* cache size selection */ 3958bd22949SKevin Hilman MCR p15, 2, r7, c0, c0, 0 3968bd22949SKevin Hilman ldmia r3!,{r4-r8} 3978bd22949SKevin Hilman /* Data TLB lockdown registers */ 3988bd22949SKevin Hilman MCR p15, 0, r4, c10, c0, 0 3998bd22949SKevin Hilman /* Instruction TLB lockdown registers */ 4008bd22949SKevin Hilman MCR p15, 0, r5, c10, c0, 1 4018bd22949SKevin Hilman /* Secure or Nonsecure Vector Base Address */ 4028bd22949SKevin Hilman MCR p15, 0, r6, c12, c0, 0 4038bd22949SKevin Hilman /* FCSE PID */ 4048bd22949SKevin Hilman MCR p15, 0, r7, c13, c0, 0 4058bd22949SKevin Hilman /* Context PID */ 4068bd22949SKevin Hilman MCR p15, 0, r8, c13, c0, 1 4078bd22949SKevin Hilman 4088bd22949SKevin Hilman ldmia r3!,{r4-r5} 4098bd22949SKevin Hilman /* primary memory remap register */ 4108bd22949SKevin Hilman MCR p15, 0, r4, c10, c2, 0 4118bd22949SKevin Hilman /*normal memory remap register */ 4128bd22949SKevin Hilman MCR p15, 0, r5, c10, c2, 1 4138bd22949SKevin Hilman 4148bd22949SKevin Hilman /* Restore cpsr */ 4158bd22949SKevin Hilman ldmia r3!,{r4} /*load CPSR from SDRAM*/ 4168bd22949SKevin Hilman msr cpsr, r4 /*store cpsr */ 4178bd22949SKevin Hilman 4188bd22949SKevin Hilman /* Enabling MMU here */ 4198bd22949SKevin Hilman mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */ 4208bd22949SKevin Hilman /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/ 4218bd22949SKevin Hilman and r7, #0x7 4228bd22949SKevin Hilman cmp r7, #0x0 4238bd22949SKevin Hilman beq usettbr0 4248bd22949SKevin Hilmanttbr_error: 4258bd22949SKevin Hilman /* More work needs to be done to support N[0:2] value other than 0 4268bd22949SKevin Hilman * So looping here so that the error can be detected 4278bd22949SKevin Hilman */ 4288bd22949SKevin Hilman b ttbr_error 4298bd22949SKevin Hilmanusettbr0: 4308bd22949SKevin Hilman mrc p15, 0, r2, c2, c0, 0 4318bd22949SKevin Hilman ldr r5, ttbrbit_mask 4328bd22949SKevin Hilman and r2, r5 4338bd22949SKevin Hilman mov r4, pc 4348bd22949SKevin Hilman ldr r5, table_index_mask 4358bd22949SKevin Hilman and r4, r5 /* r4 = 31 to 20 bits of pc */ 4368bd22949SKevin Hilman /* Extract the value to be written to table entry */ 4378bd22949SKevin Hilman ldr r1, table_entry 4388bd22949SKevin Hilman add r1, r1, r4 /* r1 has value to be written to table entry*/ 4398bd22949SKevin Hilman /* Getting the address of table entry to modify */ 4408bd22949SKevin Hilman lsr r4, #18 4418bd22949SKevin Hilman add r2, r4 /* r2 has the location which needs to be modified */ 4428bd22949SKevin Hilman /* Storing previous entry of location being modified */ 4438bd22949SKevin Hilman ldr r5, scratchpad_base 4448bd22949SKevin Hilman ldr r4, [r2] 4458bd22949SKevin Hilman str r4, [r5, #0xC0] 4468bd22949SKevin Hilman /* Modify the table entry */ 4478bd22949SKevin Hilman str r1, [r2] 4488bd22949SKevin Hilman /* Storing address of entry being modified 4498bd22949SKevin Hilman * - will be restored after enabling MMU */ 4508bd22949SKevin Hilman ldr r5, scratchpad_base 4518bd22949SKevin Hilman str r2, [r5, #0xC4] 4528bd22949SKevin Hilman 4538bd22949SKevin Hilman mov r0, #0 4548bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer 4558bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array 4568bd22949SKevin Hilman mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB 4578bd22949SKevin Hilman mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB 4588bd22949SKevin Hilman /* Restore control register but dont enable caches here*/ 4598bd22949SKevin Hilman /* Caches will be enabled after restoring MMU table entry */ 4608bd22949SKevin Hilman ldmia r3!, {r4} 4618bd22949SKevin Hilman /* Store previous value of control register in scratchpad */ 4628bd22949SKevin Hilman str r4, [r5, #0xC8] 4638bd22949SKevin Hilman ldr r2, cache_pred_disable_mask 4648bd22949SKevin Hilman and r4, r2 4658bd22949SKevin Hilman mcr p15, 0, r4, c1, c0, 0 4668bd22949SKevin Hilman 4678bd22949SKevin Hilman ldmfd sp!, {r0-r12, pc} @ restore regs and return 4688bd22949SKevin Hilmansave_context_wfi: 4698bd22949SKevin Hilman mov r8, r0 /* Store SDRAM address in r8 */ 470a087cad9STero Kristo mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register 471a087cad9STero Kristo mov r4, #0x1 @ Number of parameters for restore call 47279dcfdd4STero Kristo stmia r8!, {r4-r5} @ Push parameters for restore call 47379dcfdd4STero Kristo mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register 47479dcfdd4STero Kristo stmia r8!, {r4-r5} @ Push parameters for restore call 4758bd22949SKevin Hilman /* Check what that target sleep state is:stored in r1*/ 4768bd22949SKevin Hilman /* 1 - Only L1 and logic lost */ 4778bd22949SKevin Hilman /* 2 - Only L2 lost */ 4788bd22949SKevin Hilman /* 3 - Both L1 and L2 lost */ 4798bd22949SKevin Hilman cmp r1, #0x2 /* Only L2 lost */ 4808bd22949SKevin Hilman beq clean_l2 4818bd22949SKevin Hilman cmp r1, #0x1 /* L2 retained */ 4828bd22949SKevin Hilman /* r9 stores whether to clean L2 or not*/ 4838bd22949SKevin Hilman moveq r9, #0x0 /* Dont Clean L2 */ 4848bd22949SKevin Hilman movne r9, #0x1 /* Clean L2 */ 4858bd22949SKevin Hilmanl1_logic_lost: 4868bd22949SKevin Hilman /* Store sp and spsr to SDRAM */ 4878bd22949SKevin Hilman mov r4, sp 4888bd22949SKevin Hilman mrs r5, spsr 4898bd22949SKevin Hilman mov r6, lr 4908bd22949SKevin Hilman stmia r8!, {r4-r6} 4918bd22949SKevin Hilman /* Save all ARM registers */ 4928bd22949SKevin Hilman /* Coprocessor access control register */ 4938bd22949SKevin Hilman mrc p15, 0, r6, c1, c0, 2 4948bd22949SKevin Hilman stmia r8!, {r6} 4958bd22949SKevin Hilman /* TTBR0, TTBR1 and Translation table base control */ 4968bd22949SKevin Hilman mrc p15, 0, r4, c2, c0, 0 4978bd22949SKevin Hilman mrc p15, 0, r5, c2, c0, 1 4988bd22949SKevin Hilman mrc p15, 0, r6, c2, c0, 2 4998bd22949SKevin Hilman stmia r8!, {r4-r6} 5008bd22949SKevin Hilman /* Domain access control register, data fault status register, 5018bd22949SKevin Hilman and instruction fault status register */ 5028bd22949SKevin Hilman mrc p15, 0, r4, c3, c0, 0 5038bd22949SKevin Hilman mrc p15, 0, r5, c5, c0, 0 5048bd22949SKevin Hilman mrc p15, 0, r6, c5, c0, 1 5058bd22949SKevin Hilman stmia r8!, {r4-r6} 5068bd22949SKevin Hilman /* Data aux fault status register, instruction aux fault status, 5078bd22949SKevin Hilman datat fault address register and instruction fault address register*/ 5088bd22949SKevin Hilman mrc p15, 0, r4, c5, c1, 0 5098bd22949SKevin Hilman mrc p15, 0, r5, c5, c1, 1 5108bd22949SKevin Hilman mrc p15, 0, r6, c6, c0, 0 5118bd22949SKevin Hilman mrc p15, 0, r7, c6, c0, 2 5128bd22949SKevin Hilman stmia r8!, {r4-r7} 5138bd22949SKevin Hilman /* user r/w thread and process ID, user r/o thread and process ID, 5148bd22949SKevin Hilman priv only thread and process ID, cache size selection */ 5158bd22949SKevin Hilman mrc p15, 0, r4, c13, c0, 2 5168bd22949SKevin Hilman mrc p15, 0, r5, c13, c0, 3 5178bd22949SKevin Hilman mrc p15, 0, r6, c13, c0, 4 5188bd22949SKevin Hilman mrc p15, 2, r7, c0, c0, 0 5198bd22949SKevin Hilman stmia r8!, {r4-r7} 5208bd22949SKevin Hilman /* Data TLB lockdown, instruction TLB lockdown registers */ 5218bd22949SKevin Hilman mrc p15, 0, r5, c10, c0, 0 5228bd22949SKevin Hilman mrc p15, 0, r6, c10, c0, 1 5238bd22949SKevin Hilman stmia r8!, {r5-r6} 5248bd22949SKevin Hilman /* Secure or non secure vector base address, FCSE PID, Context PID*/ 5258bd22949SKevin Hilman mrc p15, 0, r4, c12, c0, 0 5268bd22949SKevin Hilman mrc p15, 0, r5, c13, c0, 0 5278bd22949SKevin Hilman mrc p15, 0, r6, c13, c0, 1 5288bd22949SKevin Hilman stmia r8!, {r4-r6} 5298bd22949SKevin Hilman /* Primary remap, normal remap registers */ 5308bd22949SKevin Hilman mrc p15, 0, r4, c10, c2, 0 5318bd22949SKevin Hilman mrc p15, 0, r5, c10, c2, 1 5328bd22949SKevin Hilman stmia r8!,{r4-r5} 5338bd22949SKevin Hilman 5348bd22949SKevin Hilman /* Store current cpsr*/ 5358bd22949SKevin Hilman mrs r2, cpsr 5368bd22949SKevin Hilman stmia r8!, {r2} 5378bd22949SKevin Hilman 5388bd22949SKevin Hilman mrc p15, 0, r4, c1, c0, 0 5398bd22949SKevin Hilman /* save control register */ 5408bd22949SKevin Hilman stmia r8!, {r4} 5418bd22949SKevin Hilmanclean_caches: 5428bd22949SKevin Hilman /* Clean Data or unified cache to POU*/ 5438bd22949SKevin Hilman /* How to invalidate only L1 cache???? - #FIX_ME# */ 5448bd22949SKevin Hilman /* mcr p15, 0, r11, c7, c11, 1 */ 5458bd22949SKevin Hilman cmp r9, #1 /* Check whether L2 inval is required or not*/ 5468bd22949SKevin Hilman bne skip_l2_inval 5478bd22949SKevin Hilmanclean_l2: 5480bd40535SRichard Woodruff /* 5490bd40535SRichard Woodruff * Jump out to kernel flush routine 5500bd40535SRichard Woodruff * - reuse that code is better 5510bd40535SRichard Woodruff * - it executes in a cached space so is faster than refetch per-block 5520bd40535SRichard Woodruff * - should be faster and will change with kernel 5530bd40535SRichard Woodruff * - 'might' have to copy address, load and jump to it 5540bd40535SRichard Woodruff * - lr is used since we are running in SRAM currently. 5550bd40535SRichard Woodruff */ 5560bd40535SRichard Woodruff ldr r1, kernel_flush 5570bd40535SRichard Woodruff mov lr, pc 5580bd40535SRichard Woodruff bx r1 5590bd40535SRichard Woodruff 5608bd22949SKevin Hilmanskip_l2_inval: 5618bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 5628bd22949SKevin Hilman mov r1, #0 5638bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 4 5648bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 5 5658bd22949SKevin Hilman 5668bd22949SKevin Hilman wfi @ wait for interrupt 5678bd22949SKevin Hilman nop 5688bd22949SKevin Hilman nop 5698bd22949SKevin Hilman nop 5708bd22949SKevin Hilman nop 5718bd22949SKevin Hilman nop 5728bd22949SKevin Hilman nop 5738bd22949SKevin Hilman nop 5748bd22949SKevin Hilman nop 5758bd22949SKevin Hilman nop 5768bd22949SKevin Hilman nop 57789139dceSPeter 'p2' De Schrijver bl wait_sdrc_ok 5788bd22949SKevin Hilman /* restore regs and return */ 5798bd22949SKevin Hilman ldmfd sp!, {r0-r12, pc} 5808bd22949SKevin Hilman 58189139dceSPeter 'p2' De Schrijver/* Make sure SDRC accesses are ok */ 58289139dceSPeter 'p2' De Schrijverwait_sdrc_ok: 5839d93b8a2SPeter 'p2' De Schrijver 5849d93b8a2SPeter 'p2' De Schrijver/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */ 5859d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest_ckgen 5869d93b8a2SPeter 'p2' De Schrijverwait_dpll3_lock: 58789139dceSPeter 'p2' De Schrijver ldr r5, [r4] 5889d93b8a2SPeter 'p2' De Schrijver tst r5, #1 5899d93b8a2SPeter 'p2' De Schrijver beq wait_dpll3_lock 5909d93b8a2SPeter 'p2' De Schrijver 5919d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest1_core 5929d93b8a2SPeter 'p2' De Schrijverwait_sdrc_ready: 5939d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 5949d93b8a2SPeter 'p2' De Schrijver tst r5, #0x2 5959d93b8a2SPeter 'p2' De Schrijver bne wait_sdrc_ready 5969d93b8a2SPeter 'p2' De Schrijver /* allow DLL powerdown upon hw idle req */ 5978bd22949SKevin Hilman ldr r4, sdrc_power 5988bd22949SKevin Hilman ldr r5, [r4] 5998bd22949SKevin Hilman bic r5, r5, #0x40 6008bd22949SKevin Hilman str r5, [r4] 6019d93b8a2SPeter 'p2' De Schrijveris_dll_in_lock_mode: 6029d93b8a2SPeter 'p2' De Schrijver 60389139dceSPeter 'p2' De Schrijver /* Is dll in lock mode? */ 60489139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 60589139dceSPeter 'p2' De Schrijver ldr r5, [r4] 60689139dceSPeter 'p2' De Schrijver tst r5, #0x4 60789139dceSPeter 'p2' De Schrijver bxne lr 60889139dceSPeter 'p2' De Schrijver /* wait till dll locks */ 6099d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_timed: 6109d93b8a2SPeter 'p2' De Schrijver ldr r4, wait_dll_lock_counter 6119d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 6129d93b8a2SPeter 'p2' De Schrijver str r4, wait_dll_lock_counter 61389139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_status 6149d93b8a2SPeter 'p2' De Schrijver mov r6, #8 /* Wait 20uS for lock */ 6159d93b8a2SPeter 'p2' De Schrijverwait_dll_lock: 6169d93b8a2SPeter 'p2' De Schrijver subs r6, r6, #0x1 6179d93b8a2SPeter 'p2' De Schrijver beq kick_dll 61889139dceSPeter 'p2' De Schrijver ldr r5, [r4] 61989139dceSPeter 'p2' De Schrijver and r5, r5, #0x4 62089139dceSPeter 'p2' De Schrijver cmp r5, #0x4 62189139dceSPeter 'p2' De Schrijver bne wait_dll_lock 6228bd22949SKevin Hilman bx lr 62389139dceSPeter 'p2' De Schrijver 6249d93b8a2SPeter 'p2' De Schrijver /* disable/reenable DLL if not locked */ 6259d93b8a2SPeter 'p2' De Schrijverkick_dll: 6269d93b8a2SPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 6279d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 6289d93b8a2SPeter 'p2' De Schrijver mov r6, r5 6299d93b8a2SPeter 'p2' De Schrijver bic r6, #(1<<3) /* disable dll */ 6309d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 6319d93b8a2SPeter 'p2' De Schrijver dsb 6329d93b8a2SPeter 'p2' De Schrijver orr r6, r6, #(1<<3) /* enable dll */ 6339d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 6349d93b8a2SPeter 'p2' De Schrijver dsb 6359d93b8a2SPeter 'p2' De Schrijver ldr r4, kick_counter 6369d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 6379d93b8a2SPeter 'p2' De Schrijver str r4, kick_counter 6389d93b8a2SPeter 'p2' De Schrijver b wait_dll_lock_timed 6399d93b8a2SPeter 'p2' De Schrijver 64089139dceSPeter 'p2' De Schrijvercm_idlest1_core: 64189139dceSPeter 'p2' De Schrijver .word CM_IDLEST1_CORE_V 6429d93b8a2SPeter 'p2' De Schrijvercm_idlest_ckgen: 6439d93b8a2SPeter 'p2' De Schrijver .word CM_IDLEST_CKGEN_V 64489139dceSPeter 'p2' De Schrijversdrc_dlla_status: 64589139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_STATUS_V 64689139dceSPeter 'p2' De Schrijversdrc_dlla_ctrl: 64789139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_CTRL_V 6480795a75aSTero Kristopm_prepwstst_core_p: 6490795a75aSTero Kristo .word PM_PREPWSTST_CORE_P 6508bd22949SKevin Hilmanpm_pwstctrl_mpu: 6518bd22949SKevin Hilman .word PM_PWSTCTRL_MPU_P 6528bd22949SKevin Hilmanscratchpad_base: 6538bd22949SKevin Hilman .word SCRATCHPAD_BASE_P 6540795a75aSTero Kristosram_base: 6550795a75aSTero Kristo .word SRAM_BASE_P + 0x8000 6568bd22949SKevin Hilmansdrc_power: 6578bd22949SKevin Hilman .word SDRC_POWER_V 6588bd22949SKevin Hilmanttbrbit_mask: 6598bd22949SKevin Hilman .word 0xFFFFC000 6608bd22949SKevin Hilmantable_index_mask: 6618bd22949SKevin Hilman .word 0xFFF00000 6628bd22949SKevin Hilmantable_entry: 6638bd22949SKevin Hilman .word 0x00000C02 6648bd22949SKevin Hilmancache_pred_disable_mask: 6658bd22949SKevin Hilman .word 0xFFFFE7FB 66627d59a4aSTero Kristocontrol_stat: 66727d59a4aSTero Kristo .word CONTROL_STAT 668458e999eSNishanth Menoncontrol_mem_rta: 669458e999eSNishanth Menon .word CONTROL_MEM_RTA_CTRL 6700bd40535SRichard Woodruffkernel_flush: 6710bd40535SRichard Woodruff .word v7_flush_dcache_all 672c4236d2eSPeter 'p2' De Schrijverl2dis_3630: 673c4236d2eSPeter 'p2' De Schrijver .word 0 6749d93b8a2SPeter 'p2' De Schrijver /* 6759d93b8a2SPeter 'p2' De Schrijver * When exporting to userspace while the counters are in SRAM, 6769d93b8a2SPeter 'p2' De Schrijver * these 2 words need to be at the end to facilitate retrival! 6779d93b8a2SPeter 'p2' De Schrijver */ 6789d93b8a2SPeter 'p2' De Schrijverkick_counter: 6799d93b8a2SPeter 'p2' De Schrijver .word 0 6809d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_counter: 6819d93b8a2SPeter 'p2' De Schrijver .word 0 6828bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend_sz) 6838bd22949SKevin Hilman .word . - omap34xx_cpu_suspend 684