18bd22949SKevin Hilman/* 28bd22949SKevin Hilman * (C) Copyright 2007 38bd22949SKevin Hilman * Texas Instruments 48bd22949SKevin Hilman * Karthik Dasu <karthik-dp@ti.com> 58bd22949SKevin Hilman * 68bd22949SKevin Hilman * (C) Copyright 2004 78bd22949SKevin Hilman * Texas Instruments, <www.ti.com> 88bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 98bd22949SKevin Hilman * 108bd22949SKevin Hilman * This program is free software; you can redistribute it and/or 118bd22949SKevin Hilman * modify it under the terms of the GNU General Public License as 128bd22949SKevin Hilman * published by the Free Software Foundation; either version 2 of 138bd22949SKevin Hilman * the License, or (at your option) any later version. 148bd22949SKevin Hilman * 158bd22949SKevin Hilman * This program is distributed in the hope that it will be useful, 168bd22949SKevin Hilman * but WITHOUT ANY WARRANTY; without even the implied warranty of 178bd22949SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 188bd22949SKevin Hilman * GNU General Public License for more details. 198bd22949SKevin Hilman * 208bd22949SKevin Hilman * You should have received a copy of the GNU General Public License 218bd22949SKevin Hilman * along with this program; if not, write to the Free Software 228bd22949SKevin Hilman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 238bd22949SKevin Hilman * MA 02111-1307 USA 248bd22949SKevin Hilman */ 258bd22949SKevin Hilman#include <linux/linkage.h> 268bd22949SKevin Hilman 27ee0839c2STony Lindgren#include <asm/assembler.h> 28ee0839c2STony Lindgren 29c49f34bcSTony Lindgren#include "omap34xx.h" 30ee0839c2STony Lindgren#include "iomap.h" 31ff4ae5d9SPaul Walmsley#include "cm3xxx.h" 32139563adSPaul Walmsley#include "prm3xxx.h" 338bd22949SKevin Hilman#include "sdrc.h" 34bf027ca1STony Lindgren#include "sram.h" 354814ced5SPaul Walmsley#include "control.h" 368bd22949SKevin Hilman 37fe360e1cSJean Pihet/* 38fe360e1cSJean Pihet * Registers access definitions 39fe360e1cSJean Pihet */ 40fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_OFFS 0xc 41fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ 42fe360e1cSJean Pihet (SDRC_SCRATCHPAD_SEM_OFFS) 43fe360e1cSJean Pihet#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ 44fe360e1cSJean Pihet OMAP3430_PM_PREPWSTST 4537903009SAbhijit Pagare#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 4689139dceSPeter 'p2' De Schrijver#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 479d93b8a2SPeter 'p2' De Schrijver#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) 48fe360e1cSJean Pihet#define SRAM_BASE_P OMAP3_SRAM_PA 49fe360e1cSJean Pihet#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS 50fe360e1cSJean Pihet#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ 51fe360e1cSJean Pihet OMAP36XX_CONTROL_MEM_RTA_CTRL) 52fe360e1cSJean Pihet 53fe360e1cSJean Pihet/* Move this as correct place is available */ 54fe360e1cSJean Pihet#define SCRATCHPAD_MEM_OFFS 0x310 55fe360e1cSJean Pihet#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ 56fe360e1cSJean Pihet OMAP343X_CONTROL_MEM_WKUP +\ 57fe360e1cSJean Pihet SCRATCHPAD_MEM_OFFS) 588bd22949SKevin Hilman#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 590795a75aSTero Kristo#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 600795a75aSTero Kristo#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 610795a75aSTero Kristo#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) 620795a75aSTero Kristo#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) 630795a75aSTero Kristo#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) 640795a75aSTero Kristo#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) 650795a75aSTero Kristo#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) 6689139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 6789139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 688bd22949SKevin Hilman 69dd313947SDave Martin/* 70dd313947SDave Martin * This file needs be built unconditionally as ARM to interoperate correctly 71dd313947SDave Martin * with non-Thumb-2-capable firmware. 72dd313947SDave Martin */ 73dd313947SDave Martin .arm 74a89b6f00SRajendra Nayak 75d3cdfd2aSJean Pihet/* 76d3cdfd2aSJean Pihet * API functions 77d3cdfd2aSJean Pihet */ 78a89b6f00SRajendra Nayak 791e81bc01SJean Pihet .text 80c4236d2eSPeter 'p2' De Schrijver/* 81c4236d2eSPeter 'p2' De Schrijver * L2 cache needs to be toggled for stable OFF mode functionality on 3630. 821e81bc01SJean Pihet * This function sets up a flag that will allow for this toggling to take 83f7dfe3d8SJean Pihet * place on 3630. Hopefully some version in the future may not need this. 84c4236d2eSPeter 'p2' De Schrijver */ 85c4236d2eSPeter 'p2' De SchrijverENTRY(enable_omap3630_toggle_l2_on_restore) 86c4236d2eSPeter 'p2' De Schrijver stmfd sp!, {lr} @ save registers on stack 87c4236d2eSPeter 'p2' De Schrijver /* Setup so that we will disable and enable l2 */ 88c4236d2eSPeter 'p2' De Schrijver mov r1, #0x1 89eeaf9646STony Lindgren adrl r3, l2dis_3630_offset @ may be too distant for plain adr 90eeaf9646STony Lindgren ldr r2, [r3] @ value for offset 91eeaf9646STony Lindgren str r1, [r2, r3] @ write to l2dis_3630 92c4236d2eSPeter 'p2' De Schrijver ldmfd sp!, {pc} @ restore regs and return 93dd313947SDave MartinENDPROC(enable_omap3630_toggle_l2_on_restore) 94c4236d2eSPeter 'p2' De Schrijver 95bb1c9034SJean Pihet .text 9627d59a4aSTero Kristo/* Function to call rom code to save secure ram context */ 97b6338bdcSJean Pihet .align 3 9827d59a4aSTero KristoENTRY(save_secure_ram_context) 99857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 10027d59a4aSTero Kristo adr r3, api_params @ r3 points to parameters 10127d59a4aSTero Kristo str r0, [r3,#0x4] @ r0 has sdram address 10227d59a4aSTero Kristo ldr r12, high_mask 10327d59a4aSTero Kristo and r3, r3, r12 10427d59a4aSTero Kristo ldr r12, sram_phy_addr_mask 10527d59a4aSTero Kristo orr r3, r3, r12 10627d59a4aSTero Kristo mov r0, #25 @ set service ID for PPA 10727d59a4aSTero Kristo mov r12, r0 @ copy secure service ID in r12 10827d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 109ba50ea7eSKalle Jokiniemi mov r2, #4 @ set some flags in r2, r6 11027d59a4aSTero Kristo mov r6, #0xff 1114444d712SSantosh Shilimkar dsb @ data write barrier 1124444d712SSantosh Shilimkar dmb @ data memory barrier 11376d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 11427d59a4aSTero Kristo nop 11527d59a4aSTero Kristo nop 11627d59a4aSTero Kristo nop 11727d59a4aSTero Kristo nop 118857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} 119dd313947SDave Martin .align 12027d59a4aSTero Kristosram_phy_addr_mask: 12127d59a4aSTero Kristo .word SRAM_BASE_P 12227d59a4aSTero Kristohigh_mask: 12327d59a4aSTero Kristo .word 0xffff 12427d59a4aSTero Kristoapi_params: 12527d59a4aSTero Kristo .word 0x4, 0x0, 0x0, 0x1, 0x1 126dd313947SDave MartinENDPROC(save_secure_ram_context) 12727d59a4aSTero KristoENTRY(save_secure_ram_context_sz) 12827d59a4aSTero Kristo .word . - save_secure_ram_context 12927d59a4aSTero Kristo 1308bd22949SKevin Hilman/* 131f7dfe3d8SJean Pihet * ====================== 132f7dfe3d8SJean Pihet * == Idle entry point == 133f7dfe3d8SJean Pihet * ====================== 134f7dfe3d8SJean Pihet */ 135f7dfe3d8SJean Pihet 136f7dfe3d8SJean Pihet/* 1378bd22949SKevin Hilman * Forces OMAP into idle state 1388bd22949SKevin Hilman * 139f7dfe3d8SJean Pihet * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed 140f7dfe3d8SJean Pihet * and executes the WFI instruction. Calling WFI effectively changes the 141f7dfe3d8SJean Pihet * power domains states to the desired target power states. 1428bd22949SKevin Hilman * 143f7dfe3d8SJean Pihet * 144f7dfe3d8SJean Pihet * Notes: 14546e130d2SJean Pihet * - only the minimum set of functions gets copied to internal SRAM at boot 14646e130d2SJean Pihet * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function 14746e130d2SJean Pihet * pointers in SDRAM or SRAM are called depending on the desired low power 14846e130d2SJean Pihet * target state. 149f7dfe3d8SJean Pihet * - when the OMAP wakes up it continues at different execution points 150f7dfe3d8SJean Pihet * depending on the low power mode (non-OFF vs OFF modes), 151f7dfe3d8SJean Pihet * cf. 'Resume path for xxx mode' comments. 1528bd22949SKevin Hilman */ 153b6338bdcSJean Pihet .align 3 1548bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend) 155857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 156d3cdfd2aSJean Pihet 157f7dfe3d8SJean Pihet /* 158cbe26349SRussell King * r0 contains information about saving context: 159f7dfe3d8SJean Pihet * 0 - No context lost 160f7dfe3d8SJean Pihet * 1 - Only L1 and logic lost 161c9749a35SSantosh Shilimkar * 2 - Only L2 lost (Even L1 is retained we clean it along with L2) 162c9749a35SSantosh Shilimkar * 3 - Both L1 and L2 lost and logic lost 163f7dfe3d8SJean Pihet */ 164f7dfe3d8SJean Pihet 16546e130d2SJean Pihet /* 16646e130d2SJean Pihet * For OFF mode: save context and jump to WFI in SDRAM (omap3_do_wfi) 16746e130d2SJean Pihet * For non-OFF modes: jump to the WFI code in SRAM (omap3_do_wfi_sram) 16846e130d2SJean Pihet */ 16946e130d2SJean Pihet ldr r4, omap3_do_wfi_sram_addr 17046e130d2SJean Pihet ldr r5, [r4] 171cbe26349SRussell King cmp r0, #0x0 @ If no context save required, 17246e130d2SJean Pihet bxeq r5 @ jump to the WFI code in SRAM 17346e130d2SJean Pihet 174f7dfe3d8SJean Pihet 175f7dfe3d8SJean Pihet /* Otherwise fall through to the save context code */ 176f7dfe3d8SJean Pihetsave_context_wfi: 177f7dfe3d8SJean Pihet /* 178f7dfe3d8SJean Pihet * jump out to kernel flush routine 179f7dfe3d8SJean Pihet * - reuse that code is better 180f7dfe3d8SJean Pihet * - it executes in a cached space so is faster than refetch per-block 181f7dfe3d8SJean Pihet * - should be faster and will change with kernel 182f7dfe3d8SJean Pihet * - 'might' have to copy address, load and jump to it 18390625110SSantosh Shilimkar * Flush all data from the L1 data cache before disabling 18490625110SSantosh Shilimkar * SCTLR.C bit. 185f7dfe3d8SJean Pihet */ 186f7dfe3d8SJean Pihet ldr r1, kernel_flush 187f7dfe3d8SJean Pihet mov lr, pc 188f7dfe3d8SJean Pihet bx r1 189f7dfe3d8SJean Pihet 19090625110SSantosh Shilimkar /* 19190625110SSantosh Shilimkar * Clear the SCTLR.C bit to prevent further data cache 19290625110SSantosh Shilimkar * allocation. Clearing SCTLR.C would make all the data accesses 19390625110SSantosh Shilimkar * strongly ordered and would not hit the cache. 19490625110SSantosh Shilimkar */ 19590625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 19690625110SSantosh Shilimkar bic r0, r0, #(1 << 2) @ Disable the C bit 19790625110SSantosh Shilimkar mcr p15, 0, r0, c1, c0, 0 19890625110SSantosh Shilimkar isb 19990625110SSantosh Shilimkar 20090625110SSantosh Shilimkar /* 20190625110SSantosh Shilimkar * Invalidate L1 data cache. Even though only invalidate is 20290625110SSantosh Shilimkar * necessary exported flush API is used here. Doing clean 20390625110SSantosh Shilimkar * on already clean cache would be almost NOP. 204f7dfe3d8SJean Pihet */ 205f7dfe3d8SJean Pihet ldr r1, kernel_flush 206dd313947SDave Martin blx r1 20746e130d2SJean Pihet b omap3_do_wfi 208d8a50941STony LindgrenENDPROC(omap34xx_cpu_suspend) 20946e130d2SJean Pihetomap3_do_wfi_sram_addr: 21046e130d2SJean Pihet .word omap3_do_wfi_sram 21146e130d2SJean Pihetkernel_flush: 21246e130d2SJean Pihet .word v7_flush_dcache_all 21346e130d2SJean Pihet 21446e130d2SJean Pihet/* =================================== 21546e130d2SJean Pihet * == WFI instruction => Enter idle == 21646e130d2SJean Pihet * =================================== 21746e130d2SJean Pihet */ 21846e130d2SJean Pihet 21946e130d2SJean Pihet/* 22046e130d2SJean Pihet * Do WFI instruction 22146e130d2SJean Pihet * Includes the resume path for non-OFF modes 22246e130d2SJean Pihet * 22346e130d2SJean Pihet * This code gets copied to internal SRAM and is accessible 22446e130d2SJean Pihet * from both SDRAM and SRAM: 22546e130d2SJean Pihet * - executed from SRAM for non-off modes (omap3_do_wfi_sram), 22646e130d2SJean Pihet * - executed from SDRAM for OFF mode (omap3_do_wfi). 22746e130d2SJean Pihet */ 22846e130d2SJean Pihet .align 3 22946e130d2SJean PihetENTRY(omap3_do_wfi) 2308bd22949SKevin Hilman ldr r4, sdrc_power @ read the SDRC_POWER register 2318bd22949SKevin Hilman ldr r5, [r4] @ read the contents of SDRC_POWER 2328bd22949SKevin Hilman orr r5, r5, #0x40 @ enable self refresh on idle req 2338bd22949SKevin Hilman str r5, [r4] @ write back to SDRC_POWER register 2348bd22949SKevin Hilman 2358bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 2364444d712SSantosh Shilimkar dsb 2374444d712SSantosh Shilimkar dmb 2388bd22949SKevin Hilman 239f7dfe3d8SJean Pihet/* 240f7dfe3d8SJean Pihet * =================================== 241f7dfe3d8SJean Pihet * == WFI instruction => Enter idle == 242f7dfe3d8SJean Pihet * =================================== 243f7dfe3d8SJean Pihet */ 2448bd22949SKevin Hilman wfi @ wait for interrupt 2458bd22949SKevin Hilman 246f7dfe3d8SJean Pihet/* 247f7dfe3d8SJean Pihet * =================================== 248f7dfe3d8SJean Pihet * == Resume path for non-OFF modes == 249f7dfe3d8SJean Pihet * =================================== 250f7dfe3d8SJean Pihet */ 2518bd22949SKevin Hilman nop 2528bd22949SKevin Hilman nop 2538bd22949SKevin Hilman nop 2548bd22949SKevin Hilman nop 2558bd22949SKevin Hilman nop 2568bd22949SKevin Hilman nop 2578bd22949SKevin Hilman nop 2588bd22949SKevin Hilman nop 2598bd22949SKevin Hilman nop 2608bd22949SKevin Hilman nop 2618bd22949SKevin Hilman 26246e130d2SJean Pihet/* 26346e130d2SJean Pihet * This function implements the erratum ID i581 WA: 26446e130d2SJean Pihet * SDRC state restore before accessing the SDRAM 26546e130d2SJean Pihet * 26646e130d2SJean Pihet * Only used at return from non-OFF mode. For OFF 26746e130d2SJean Pihet * mode the ROM code configures the SDRC and 26846e130d2SJean Pihet * the DPLL before calling the restore code directly 26946e130d2SJean Pihet * from DDR. 27046e130d2SJean Pihet */ 27146e130d2SJean Pihet 27246e130d2SJean Pihet/* Make sure SDRC accesses are ok */ 27346e130d2SJean Pihetwait_sdrc_ok: 27446e130d2SJean Pihet 27546e130d2SJean Pihet/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */ 27646e130d2SJean Pihet ldr r4, cm_idlest_ckgen 27746e130d2SJean Pihetwait_dpll3_lock: 27846e130d2SJean Pihet ldr r5, [r4] 27946e130d2SJean Pihet tst r5, #1 28046e130d2SJean Pihet beq wait_dpll3_lock 28146e130d2SJean Pihet 28246e130d2SJean Pihet ldr r4, cm_idlest1_core 28346e130d2SJean Pihetwait_sdrc_ready: 28446e130d2SJean Pihet ldr r5, [r4] 28546e130d2SJean Pihet tst r5, #0x2 28646e130d2SJean Pihet bne wait_sdrc_ready 28746e130d2SJean Pihet /* allow DLL powerdown upon hw idle req */ 28846e130d2SJean Pihet ldr r4, sdrc_power 28946e130d2SJean Pihet ldr r5, [r4] 29046e130d2SJean Pihet bic r5, r5, #0x40 29146e130d2SJean Pihet str r5, [r4] 29246e130d2SJean Pihet 29346e130d2SJean Pihetis_dll_in_lock_mode: 29446e130d2SJean Pihet /* Is dll in lock mode? */ 29546e130d2SJean Pihet ldr r4, sdrc_dlla_ctrl 29646e130d2SJean Pihet ldr r5, [r4] 29746e130d2SJean Pihet tst r5, #0x4 29846e130d2SJean Pihet bne exit_nonoff_modes @ Return if locked 29946e130d2SJean Pihet /* wait till dll locks */ 30046e130d2SJean Pihetwait_dll_lock_timed: 30146e130d2SJean Pihet ldr r4, sdrc_dlla_status 30246e130d2SJean Pihet /* Wait 20uS for lock */ 30346e130d2SJean Pihet mov r6, #8 30446e130d2SJean Pihetwait_dll_lock: 30546e130d2SJean Pihet subs r6, r6, #0x1 30646e130d2SJean Pihet beq kick_dll 30746e130d2SJean Pihet ldr r5, [r4] 30846e130d2SJean Pihet and r5, r5, #0x4 30946e130d2SJean Pihet cmp r5, #0x4 31046e130d2SJean Pihet bne wait_dll_lock 31146e130d2SJean Pihet b exit_nonoff_modes @ Return when locked 31246e130d2SJean Pihet 31346e130d2SJean Pihet /* disable/reenable DLL if not locked */ 31446e130d2SJean Pihetkick_dll: 31546e130d2SJean Pihet ldr r4, sdrc_dlla_ctrl 31646e130d2SJean Pihet ldr r5, [r4] 31746e130d2SJean Pihet mov r6, r5 31846e130d2SJean Pihet bic r6, #(1<<3) @ disable dll 31946e130d2SJean Pihet str r6, [r4] 32046e130d2SJean Pihet dsb 32146e130d2SJean Pihet orr r6, r6, #(1<<3) @ enable dll 32246e130d2SJean Pihet str r6, [r4] 32346e130d2SJean Pihet dsb 32446e130d2SJean Pihet b wait_dll_lock_timed 32546e130d2SJean Pihet 32646e130d2SJean Pihetexit_nonoff_modes: 32746e130d2SJean Pihet /* Re-enable C-bit if needed */ 32890625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 32990625110SSantosh Shilimkar tst r0, #(1 << 2) @ Check C bit enabled? 33090625110SSantosh Shilimkar orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared 33190625110SSantosh Shilimkar mcreq p15, 0, r0, c1, c0, 0 33290625110SSantosh Shilimkar isb 33390625110SSantosh Shilimkar 334f7dfe3d8SJean Pihet/* 335f7dfe3d8SJean Pihet * =================================== 336f7dfe3d8SJean Pihet * == Exit point from non-OFF modes == 337f7dfe3d8SJean Pihet * =================================== 338f7dfe3d8SJean Pihet */ 339857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} @ restore regs and return 340d8a50941STony LindgrenENDPROC(omap3_do_wfi) 34146e130d2SJean Pihetsdrc_power: 34246e130d2SJean Pihet .word SDRC_POWER_V 34346e130d2SJean Pihetcm_idlest1_core: 34446e130d2SJean Pihet .word CM_IDLEST1_CORE_V 34546e130d2SJean Pihetcm_idlest_ckgen: 34646e130d2SJean Pihet .word CM_IDLEST_CKGEN_V 34746e130d2SJean Pihetsdrc_dlla_status: 34846e130d2SJean Pihet .word SDRC_DLLA_STATUS_V 34946e130d2SJean Pihetsdrc_dlla_ctrl: 35046e130d2SJean Pihet .word SDRC_DLLA_CTRL_V 35146e130d2SJean PihetENTRY(omap3_do_wfi_sz) 35246e130d2SJean Pihet .word . - omap3_do_wfi 35346e130d2SJean Pihet 354f7dfe3d8SJean Pihet 355f7dfe3d8SJean Pihet/* 356f7dfe3d8SJean Pihet * ============================== 357f7dfe3d8SJean Pihet * == Resume path for OFF mode == 358f7dfe3d8SJean Pihet * ============================== 359f7dfe3d8SJean Pihet */ 360f7dfe3d8SJean Pihet 361f7dfe3d8SJean Pihet/* 362f7dfe3d8SJean Pihet * The restore_* functions are called by the ROM code 363f7dfe3d8SJean Pihet * when back from WFI in OFF mode. 364f7dfe3d8SJean Pihet * Cf. the get_*restore_pointer functions. 365f7dfe3d8SJean Pihet * 366f7dfe3d8SJean Pihet * restore_es3: applies to 34xx >= ES3.0 367f7dfe3d8SJean Pihet * restore_3630: applies to 36xx 368f7dfe3d8SJean Pihet * restore: common code for 3xxx 36946e130d2SJean Pihet * 37046e130d2SJean Pihet * Note: when back from CORE and MPU OFF mode we are running 37146e130d2SJean Pihet * from SDRAM, without MMU, without the caches and prediction. 37246e130d2SJean Pihet * Also the SRAM content has been cleared. 373f7dfe3d8SJean Pihet */ 37414c79bbeSKevin HilmanENTRY(omap3_restore_es3) 3750795a75aSTero Kristo ldr r5, pm_prepwstst_core_p 3760795a75aSTero Kristo ldr r4, [r5] 3770795a75aSTero Kristo and r4, r4, #0x3 3780795a75aSTero Kristo cmp r4, #0x0 @ Check if previous power state of CORE is OFF 37946e130d2SJean Pihet bne omap3_restore @ Fall through to OMAP3 common code 3800795a75aSTero Kristo adr r0, es3_sdrc_fix 3810795a75aSTero Kristo ldr r1, sram_base 3820795a75aSTero Kristo ldr r2, es3_sdrc_fix_sz 3830795a75aSTero Kristo mov r2, r2, ror #2 3840795a75aSTero Kristocopy_to_sram: 3850795a75aSTero Kristo ldmia r0!, {r3} @ val = *src 3860795a75aSTero Kristo stmia r1!, {r3} @ *dst = val 3870795a75aSTero Kristo subs r2, r2, #0x1 @ num_words-- 3880795a75aSTero Kristo bne copy_to_sram 3890795a75aSTero Kristo ldr r1, sram_base 3900795a75aSTero Kristo blx r1 39146e130d2SJean Pihet b omap3_restore @ Fall through to OMAP3 common code 39214c79bbeSKevin HilmanENDPROC(omap3_restore_es3) 393458e999eSNishanth Menon 39414c79bbeSKevin HilmanENTRY(omap3_restore_3630) 395458e999eSNishanth Menon ldr r1, pm_prepwstst_core_p 396458e999eSNishanth Menon ldr r2, [r1] 397458e999eSNishanth Menon and r2, r2, #0x3 398458e999eSNishanth Menon cmp r2, #0x0 @ Check if previous power state of CORE is OFF 39946e130d2SJean Pihet bne omap3_restore @ Fall through to OMAP3 common code 400458e999eSNishanth Menon /* Disable RTA before giving control */ 401458e999eSNishanth Menon ldr r1, control_mem_rta 402458e999eSNishanth Menon mov r2, #OMAP36XX_RTA_DISABLE 403458e999eSNishanth Menon str r2, [r1] 40414c79bbeSKevin HilmanENDPROC(omap3_restore_3630) 405f7dfe3d8SJean Pihet 406f7dfe3d8SJean Pihet /* Fall through to common code for the remaining logic */ 407f7dfe3d8SJean Pihet 40814c79bbeSKevin HilmanENTRY(omap3_restore) 409f7dfe3d8SJean Pihet /* 4102637ce30SRussell King * Read the pwstctrl register to check the reason for mpu reset. 4112637ce30SRussell King * This tells us what was lost. 412f7dfe3d8SJean Pihet */ 4138bd22949SKevin Hilman ldr r1, pm_pwstctrl_mpu 4148bd22949SKevin Hilman ldr r2, [r1] 4158bd22949SKevin Hilman and r2, r2, #0x3 4168bd22949SKevin Hilman cmp r2, #0x0 @ Check if target power state was OFF or RET 4178bd22949SKevin Hilman bne logic_l1_restore 418c4236d2eSPeter 'p2' De Schrijver 419eeaf9646STony Lindgren adr r1, l2dis_3630_offset @ address for offset 420eeaf9646STony Lindgren ldr r0, [r1] @ value for offset 421eeaf9646STony Lindgren ldr r0, [r1, r0] @ value at l2dis_3630 422c4236d2eSPeter 'p2' De Schrijver cmp r0, #0x1 @ should we disable L2 on 3630? 423c4236d2eSPeter 'p2' De Schrijver bne skipl2dis 424c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r0, c1, c0, 1 425c4236d2eSPeter 'p2' De Schrijver bic r0, r0, #2 @ disable L2 cache 426c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r0, c1, c0, 1 427c4236d2eSPeter 'p2' De Schrijverskipl2dis: 42827d59a4aSTero Kristo ldr r0, control_stat 42927d59a4aSTero Kristo ldr r1, [r0] 43027d59a4aSTero Kristo and r1, #0x700 43127d59a4aSTero Kristo cmp r1, #0x300 43227d59a4aSTero Kristo beq l2_inv_gp 43327d59a4aSTero Kristo mov r0, #40 @ set service ID for PPA 43427d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 43527d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 43627d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 43727d59a4aSTero Kristo mov r6, #0xff 43827d59a4aSTero Kristo adr r3, l2_inv_api_params @ r3 points to dummy parameters 4394444d712SSantosh Shilimkar dsb @ data write barrier 4404444d712SSantosh Shilimkar dmb @ data memory barrier 44176d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 44227d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 44327d59a4aSTero Kristo mov r0, #42 @ set service ID for PPA 44427d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 44527d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 44627d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 44727d59a4aSTero Kristo mov r6, #0xff 448a087cad9STero Kristo ldr r4, scratchpad_base 449a087cad9STero Kristo ldr r3, [r4, #0xBC] @ r3 points to parameters 4504444d712SSantosh Shilimkar dsb @ data write barrier 4514444d712SSantosh Shilimkar dmb @ data memory barrier 45276d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 45327d59a4aSTero Kristo 45479dcfdd4STero Kristo#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 45579dcfdd4STero Kristo /* Restore L2 aux control register */ 45679dcfdd4STero Kristo @ set service ID for PPA 45779dcfdd4STero Kristo mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 45879dcfdd4STero Kristo mov r12, r0 @ copy service ID in r12 45979dcfdd4STero Kristo mov r1, #0 @ set task ID for ROM code in r1 46079dcfdd4STero Kristo mov r2, #4 @ set some flags in r2, r6 46179dcfdd4STero Kristo mov r6, #0xff 46279dcfdd4STero Kristo ldr r4, scratchpad_base 46379dcfdd4STero Kristo ldr r3, [r4, #0xBC] 46479dcfdd4STero Kristo adds r3, r3, #8 @ r3 points to parameters 4654444d712SSantosh Shilimkar dsb @ data write barrier 4664444d712SSantosh Shilimkar dmb @ data memory barrier 46776d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 46879dcfdd4STero Kristo#endif 46927d59a4aSTero Kristo b logic_l1_restore 470bb1c9034SJean Pihet 471dd313947SDave Martin .align 47227d59a4aSTero Kristol2_inv_api_params: 47327d59a4aSTero Kristo .word 0x1, 0x00 47427d59a4aSTero Kristol2_inv_gp: 4758bd22949SKevin Hilman /* Execute smi to invalidate L2 cache */ 476bb1c9034SJean Pihet mov r12, #0x1 @ set up to invalidate L2 47776d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 47827d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 479a087cad9STero Kristo ldr r4, scratchpad_base 480a087cad9STero Kristo ldr r3, [r4,#0xBC] 481a087cad9STero Kristo ldr r0, [r3,#4] 48227d59a4aSTero Kristo mov r12, #0x3 48376d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 48479dcfdd4STero Kristo ldr r4, scratchpad_base 48579dcfdd4STero Kristo ldr r3, [r4,#0xBC] 48679dcfdd4STero Kristo ldr r0, [r3,#12] 48779dcfdd4STero Kristo mov r12, #0x2 48876d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 4898bd22949SKevin Hilmanlogic_l1_restore: 490eeaf9646STony Lindgren adr r0, l2dis_3630_offset @ adress for offset 491eeaf9646STony Lindgren ldr r1, [r0] @ value for offset 492eeaf9646STony Lindgren ldr r1, [r0, r1] @ value at l2dis_3630 493bb1c9034SJean Pihet cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 494c4236d2eSPeter 'p2' De Schrijver bne skipl2reen 495c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r1, c1, c0, 1 496c4236d2eSPeter 'p2' De Schrijver orr r1, r1, #2 @ re-enable L2 cache 497c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r1, c1, c0, 1 498c4236d2eSPeter 'p2' De Schrijverskipl2reen: 4998bd22949SKevin Hilman 500076f2cc4SRussell King /* Now branch to the common CPU resume function */ 501076f2cc4SRussell King b cpu_resume 50214c79bbeSKevin HilmanENDPROC(omap3_restore) 50346f557cbSSantosh Shilimkar 504076f2cc4SRussell King .ltorg 5051e81bc01SJean Pihet 5061e81bc01SJean Pihet/* 50746e130d2SJean Pihet * Local variables 50846e130d2SJean Pihet */ 50946e130d2SJean Pihetpm_prepwstst_core_p: 51046e130d2SJean Pihet .word PM_PREPWSTST_CORE_P 51146e130d2SJean Pihetpm_pwstctrl_mpu: 51246e130d2SJean Pihet .word PM_PWSTCTRL_MPU_P 51346e130d2SJean Pihetscratchpad_base: 51446e130d2SJean Pihet .word SCRATCHPAD_BASE_P 51546e130d2SJean Pihetsram_base: 51646e130d2SJean Pihet .word SRAM_BASE_P + 0x8000 51746e130d2SJean Pihetcontrol_stat: 51846e130d2SJean Pihet .word CONTROL_STAT 51946e130d2SJean Pihetcontrol_mem_rta: 52046e130d2SJean Pihet .word CONTROL_MEM_RTA_CTRL 521eeaf9646STony Lindgrenl2dis_3630_offset: 522eeaf9646STony Lindgren .long l2dis_3630 - . 523eeaf9646STony Lindgren 524eeaf9646STony Lindgren .data 52546e130d2SJean Pihetl2dis_3630: 52646e130d2SJean Pihet .word 0 52746e130d2SJean Pihet 52846e130d2SJean Pihet/* 5291e81bc01SJean Pihet * Internal functions 5301e81bc01SJean Pihet */ 5311e81bc01SJean Pihet 53246e130d2SJean Pihet/* 53346e130d2SJean Pihet * This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 53446e130d2SJean Pihet * Copied to and run from SRAM in order to reconfigure the SDRC parameters. 53546e130d2SJean Pihet */ 5361e81bc01SJean Pihet .text 537dd313947SDave Martin .align 3 5381e81bc01SJean PihetENTRY(es3_sdrc_fix) 5391e81bc01SJean Pihet ldr r4, sdrc_syscfg @ get config addr 5401e81bc01SJean Pihet ldr r5, [r4] @ get value 5411e81bc01SJean Pihet tst r5, #0x100 @ is part access blocked 5421e81bc01SJean Pihet it eq 5431e81bc01SJean Pihet biceq r5, r5, #0x100 @ clear bit if set 5441e81bc01SJean Pihet str r5, [r4] @ write back change 5451e81bc01SJean Pihet ldr r4, sdrc_mr_0 @ get config addr 5461e81bc01SJean Pihet ldr r5, [r4] @ get value 5471e81bc01SJean Pihet str r5, [r4] @ write back change 5481e81bc01SJean Pihet ldr r4, sdrc_emr2_0 @ get config addr 5491e81bc01SJean Pihet ldr r5, [r4] @ get value 5501e81bc01SJean Pihet str r5, [r4] @ write back change 5511e81bc01SJean Pihet ldr r4, sdrc_manual_0 @ get config addr 5521e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 5531e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 5541e81bc01SJean Pihet ldr r4, sdrc_mr_1 @ get config addr 5551e81bc01SJean Pihet ldr r5, [r4] @ get value 5561e81bc01SJean Pihet str r5, [r4] @ write back change 5571e81bc01SJean Pihet ldr r4, sdrc_emr2_1 @ get config addr 5581e81bc01SJean Pihet ldr r5, [r4] @ get value 5591e81bc01SJean Pihet str r5, [r4] @ write back change 5601e81bc01SJean Pihet ldr r4, sdrc_manual_1 @ get config addr 5611e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 5621e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 5631e81bc01SJean Pihet bx lr 5641e81bc01SJean Pihet 56546e130d2SJean Pihet/* 56646e130d2SJean Pihet * Local variables 56746e130d2SJean Pihet */ 568dd313947SDave Martin .align 5691e81bc01SJean Pihetsdrc_syscfg: 5701e81bc01SJean Pihet .word SDRC_SYSCONFIG_P 5711e81bc01SJean Pihetsdrc_mr_0: 5721e81bc01SJean Pihet .word SDRC_MR_0_P 5731e81bc01SJean Pihetsdrc_emr2_0: 5741e81bc01SJean Pihet .word SDRC_EMR2_0_P 5751e81bc01SJean Pihetsdrc_manual_0: 5761e81bc01SJean Pihet .word SDRC_MANUAL_0_P 5771e81bc01SJean Pihetsdrc_mr_1: 5781e81bc01SJean Pihet .word SDRC_MR_1_P 5791e81bc01SJean Pihetsdrc_emr2_1: 5801e81bc01SJean Pihet .word SDRC_EMR2_1_P 5811e81bc01SJean Pihetsdrc_manual_1: 5821e81bc01SJean Pihet .word SDRC_MANUAL_1_P 583dd313947SDave MartinENDPROC(es3_sdrc_fix) 5841e81bc01SJean PihetENTRY(es3_sdrc_fix_sz) 5851e81bc01SJean Pihet .word . - es3_sdrc_fix 586