18bd22949SKevin Hilman/* 28bd22949SKevin Hilman * linux/arch/arm/mach-omap2/sleep.S 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * (C) Copyright 2007 58bd22949SKevin Hilman * Texas Instruments 68bd22949SKevin Hilman * Karthik Dasu <karthik-dp@ti.com> 78bd22949SKevin Hilman * 88bd22949SKevin Hilman * (C) Copyright 2004 98bd22949SKevin Hilman * Texas Instruments, <www.ti.com> 108bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 118bd22949SKevin Hilman * 128bd22949SKevin Hilman * This program is free software; you can redistribute it and/or 138bd22949SKevin Hilman * modify it under the terms of the GNU General Public License as 148bd22949SKevin Hilman * published by the Free Software Foundation; either version 2 of 158bd22949SKevin Hilman * the License, or (at your option) any later version. 168bd22949SKevin Hilman * 178bd22949SKevin Hilman * This program is distributed in the hope that it will be useful, 188bd22949SKevin Hilman * but WITHOUT ANY WARRANTY; without even the implied warranty of 198bd22949SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 208bd22949SKevin Hilman * GNU General Public License for more details. 218bd22949SKevin Hilman * 228bd22949SKevin Hilman * You should have received a copy of the GNU General Public License 238bd22949SKevin Hilman * along with this program; if not, write to the Free Software 248bd22949SKevin Hilman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 258bd22949SKevin Hilman * MA 02111-1307 USA 268bd22949SKevin Hilman */ 278bd22949SKevin Hilman#include <linux/linkage.h> 288bd22949SKevin Hilman#include <asm/assembler.h> 298bd22949SKevin Hilman#include <mach/io.h> 308bd22949SKevin Hilman 3189139dceSPeter 'p2' De Schrijver#include "cm.h" 328bd22949SKevin Hilman#include "prm.h" 338bd22949SKevin Hilman#include "sdrc.h" 344814ced5SPaul Walmsley#include "control.h" 358bd22949SKevin Hilman 36a89b6f00SRajendra Nayak#define SDRC_SCRATCHPAD_SEM_V 0xfa00291c 37a89b6f00SRajendra Nayak 388bd22949SKevin Hilman#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ 398bd22949SKevin Hilman OMAP3430_PM_PREPWSTST) 400795a75aSTero Kristo#define PM_PREPWSTST_CORE_P 0x48306AE8 418bd22949SKevin Hilman#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ 428bd22949SKevin Hilman OMAP3430_PM_PREPWSTST) 4337903009SAbhijit Pagare#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 4489139dceSPeter 'p2' De Schrijver#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 459d93b8a2SPeter 'p2' De Schrijver#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) 4627d59a4aSTero Kristo#define SRAM_BASE_P 0x40200000 4727d59a4aSTero Kristo#define CONTROL_STAT 0x480022F0 488bd22949SKevin Hilman#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is 498bd22949SKevin Hilman * available */ 5061255ab9SRajendra Nayak#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\ 5161255ab9SRajendra Nayak + SCRATCHPAD_MEM_OFFS) 528bd22949SKevin Hilman#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 530795a75aSTero Kristo#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 540795a75aSTero Kristo#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 550795a75aSTero Kristo#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) 560795a75aSTero Kristo#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) 570795a75aSTero Kristo#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) 580795a75aSTero Kristo#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) 590795a75aSTero Kristo#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) 6089139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 6189139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 628bd22949SKevin Hilman 638bd22949SKevin Hilman .text 6446cd09a7SUwe Kleine-König/* Function to acquire the semaphore in scratchpad */ 65a89b6f00SRajendra NayakENTRY(lock_scratchpad_sem) 66a89b6f00SRajendra Nayak stmfd sp!, {lr} @ save registers on stack 67a89b6f00SRajendra Nayakwait_sem: 68a89b6f00SRajendra Nayak mov r0,#1 69a89b6f00SRajendra Nayak ldr r1, sdrc_scratchpad_sem 70a89b6f00SRajendra Nayakwait_loop: 71a89b6f00SRajendra Nayak ldr r2, [r1] @ load the lock value 72a89b6f00SRajendra Nayak cmp r2, r0 @ is the lock free ? 73a89b6f00SRajendra Nayak beq wait_loop @ not free... 74a89b6f00SRajendra Nayak swp r2, r0, [r1] @ semaphore free so lock it and proceed 75a89b6f00SRajendra Nayak cmp r2, r0 @ did we succeed ? 76a89b6f00SRajendra Nayak beq wait_sem @ no - try again 77a89b6f00SRajendra Nayak ldmfd sp!, {pc} @ restore regs and return 78a89b6f00SRajendra Nayaksdrc_scratchpad_sem: 79a89b6f00SRajendra Nayak .word SDRC_SCRATCHPAD_SEM_V 80a89b6f00SRajendra NayakENTRY(lock_scratchpad_sem_sz) 81a89b6f00SRajendra Nayak .word . - lock_scratchpad_sem 82a89b6f00SRajendra Nayak 83a89b6f00SRajendra Nayak .text 84a89b6f00SRajendra Nayak/* Function to release the scratchpad semaphore */ 85a89b6f00SRajendra NayakENTRY(unlock_scratchpad_sem) 86a89b6f00SRajendra Nayak stmfd sp!, {lr} @ save registers on stack 87a89b6f00SRajendra Nayak ldr r3, sdrc_scratchpad_sem 88a89b6f00SRajendra Nayak mov r2,#0 89a89b6f00SRajendra Nayak str r2,[r3] 90a89b6f00SRajendra Nayak ldmfd sp!, {pc} @ restore regs and return 91a89b6f00SRajendra NayakENTRY(unlock_scratchpad_sem_sz) 92a89b6f00SRajendra Nayak .word . - unlock_scratchpad_sem 93a89b6f00SRajendra Nayak 94a89b6f00SRajendra Nayak .text 958bd22949SKevin Hilman/* Function call to get the restore pointer for resume from OFF */ 968bd22949SKevin HilmanENTRY(get_restore_pointer) 978bd22949SKevin Hilman stmfd sp!, {lr} @ save registers on stack 988bd22949SKevin Hilman adr r0, restore 998bd22949SKevin Hilman ldmfd sp!, {pc} @ restore regs and return 1008bd22949SKevin HilmanENTRY(get_restore_pointer_sz) 1010795a75aSTero Kristo .word . - get_restore_pointer 1020795a75aSTero Kristo 1030795a75aSTero Kristo .text 1040795a75aSTero Kristo/* Function call to get the restore pointer for for ES3 to resume from OFF */ 1050795a75aSTero KristoENTRY(get_es3_restore_pointer) 1060795a75aSTero Kristo stmfd sp!, {lr} @ save registers on stack 1070795a75aSTero Kristo adr r0, restore_es3 1080795a75aSTero Kristo ldmfd sp!, {pc} @ restore regs and return 1090795a75aSTero KristoENTRY(get_es3_restore_pointer_sz) 1100795a75aSTero Kristo .word . - get_es3_restore_pointer 1110795a75aSTero Kristo 1120795a75aSTero KristoENTRY(es3_sdrc_fix) 1130795a75aSTero Kristo ldr r4, sdrc_syscfg @ get config addr 1140795a75aSTero Kristo ldr r5, [r4] @ get value 1150795a75aSTero Kristo tst r5, #0x100 @ is part access blocked 1160795a75aSTero Kristo it eq 1170795a75aSTero Kristo biceq r5, r5, #0x100 @ clear bit if set 1180795a75aSTero Kristo str r5, [r4] @ write back change 1190795a75aSTero Kristo ldr r4, sdrc_mr_0 @ get config addr 1200795a75aSTero Kristo ldr r5, [r4] @ get value 1210795a75aSTero Kristo str r5, [r4] @ write back change 1220795a75aSTero Kristo ldr r4, sdrc_emr2_0 @ get config addr 1230795a75aSTero Kristo ldr r5, [r4] @ get value 1240795a75aSTero Kristo str r5, [r4] @ write back change 1250795a75aSTero Kristo ldr r4, sdrc_manual_0 @ get config addr 1260795a75aSTero Kristo mov r5, #0x2 @ autorefresh command 1270795a75aSTero Kristo str r5, [r4] @ kick off refreshes 1280795a75aSTero Kristo ldr r4, sdrc_mr_1 @ get config addr 1290795a75aSTero Kristo ldr r5, [r4] @ get value 1300795a75aSTero Kristo str r5, [r4] @ write back change 1310795a75aSTero Kristo ldr r4, sdrc_emr2_1 @ get config addr 1320795a75aSTero Kristo ldr r5, [r4] @ get value 1330795a75aSTero Kristo str r5, [r4] @ write back change 1340795a75aSTero Kristo ldr r4, sdrc_manual_1 @ get config addr 1350795a75aSTero Kristo mov r5, #0x2 @ autorefresh command 1360795a75aSTero Kristo str r5, [r4] @ kick off refreshes 1370795a75aSTero Kristo bx lr 1380795a75aSTero Kristosdrc_syscfg: 1390795a75aSTero Kristo .word SDRC_SYSCONFIG_P 1400795a75aSTero Kristosdrc_mr_0: 1410795a75aSTero Kristo .word SDRC_MR_0_P 1420795a75aSTero Kristosdrc_emr2_0: 1430795a75aSTero Kristo .word SDRC_EMR2_0_P 1440795a75aSTero Kristosdrc_manual_0: 1450795a75aSTero Kristo .word SDRC_MANUAL_0_P 1460795a75aSTero Kristosdrc_mr_1: 1470795a75aSTero Kristo .word SDRC_MR_1_P 1480795a75aSTero Kristosdrc_emr2_1: 1490795a75aSTero Kristo .word SDRC_EMR2_1_P 1500795a75aSTero Kristosdrc_manual_1: 1510795a75aSTero Kristo .word SDRC_MANUAL_1_P 1520795a75aSTero KristoENTRY(es3_sdrc_fix_sz) 1530795a75aSTero Kristo .word . - es3_sdrc_fix 15427d59a4aSTero Kristo 15527d59a4aSTero Kristo/* Function to call rom code to save secure ram context */ 15627d59a4aSTero KristoENTRY(save_secure_ram_context) 15727d59a4aSTero Kristo stmfd sp!, {r1-r12, lr} @ save registers on stack 15827d59a4aSTero Kristosave_secure_ram_debug: 15927d59a4aSTero Kristo /* b save_secure_ram_debug */ @ enable to debug save code 16027d59a4aSTero Kristo adr r3, api_params @ r3 points to parameters 16127d59a4aSTero Kristo str r0, [r3,#0x4] @ r0 has sdram address 16227d59a4aSTero Kristo ldr r12, high_mask 16327d59a4aSTero Kristo and r3, r3, r12 16427d59a4aSTero Kristo ldr r12, sram_phy_addr_mask 16527d59a4aSTero Kristo orr r3, r3, r12 16627d59a4aSTero Kristo mov r0, #25 @ set service ID for PPA 16727d59a4aSTero Kristo mov r12, r0 @ copy secure service ID in r12 16827d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 169ba50ea7eSKalle Jokiniemi mov r2, #4 @ set some flags in r2, r6 17027d59a4aSTero Kristo mov r6, #0xff 17127d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 17227d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 17327d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 17427d59a4aSTero Kristo nop 17527d59a4aSTero Kristo nop 17627d59a4aSTero Kristo nop 17727d59a4aSTero Kristo nop 17827d59a4aSTero Kristo ldmfd sp!, {r1-r12, pc} 17927d59a4aSTero Kristosram_phy_addr_mask: 18027d59a4aSTero Kristo .word SRAM_BASE_P 18127d59a4aSTero Kristohigh_mask: 18227d59a4aSTero Kristo .word 0xffff 18327d59a4aSTero Kristoapi_params: 18427d59a4aSTero Kristo .word 0x4, 0x0, 0x0, 0x1, 0x1 18527d59a4aSTero KristoENTRY(save_secure_ram_context_sz) 18627d59a4aSTero Kristo .word . - save_secure_ram_context 18727d59a4aSTero Kristo 1888bd22949SKevin Hilman/* 1898bd22949SKevin Hilman * Forces OMAP into idle state 1908bd22949SKevin Hilman * 1918bd22949SKevin Hilman * omap34xx_suspend() - This bit of code just executes the WFI 1928bd22949SKevin Hilman * for normal idles. 1938bd22949SKevin Hilman * 1948bd22949SKevin Hilman * Note: This code get's copied to internal SRAM at boot. When the OMAP 1958bd22949SKevin Hilman * wakes up it continues execution at the point it went to sleep. 1968bd22949SKevin Hilman */ 1978bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend) 1988bd22949SKevin Hilman stmfd sp!, {r0-r12, lr} @ save registers on stack 1998bd22949SKevin Hilmanloop: 2008bd22949SKevin Hilman /*b loop*/ @Enable to debug by stepping through code 2018bd22949SKevin Hilman /* r0 contains restore pointer in sdram */ 2028bd22949SKevin Hilman /* r1 contains information about saving context */ 2038bd22949SKevin Hilman ldr r4, sdrc_power @ read the SDRC_POWER register 2048bd22949SKevin Hilman ldr r5, [r4] @ read the contents of SDRC_POWER 2058bd22949SKevin Hilman orr r5, r5, #0x40 @ enable self refresh on idle req 2068bd22949SKevin Hilman str r5, [r4] @ write back to SDRC_POWER register 2078bd22949SKevin Hilman 2088bd22949SKevin Hilman cmp r1, #0x0 2098bd22949SKevin Hilman /* If context save is required, do that and execute wfi */ 2108bd22949SKevin Hilman bne save_context_wfi 2118bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 2128bd22949SKevin Hilman mov r1, #0 2138bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 4 2148bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 5 2158bd22949SKevin Hilman 2168bd22949SKevin Hilman wfi @ wait for interrupt 2178bd22949SKevin Hilman 2188bd22949SKevin Hilman nop 2198bd22949SKevin Hilman nop 2208bd22949SKevin Hilman nop 2218bd22949SKevin Hilman nop 2228bd22949SKevin Hilman nop 2238bd22949SKevin Hilman nop 2248bd22949SKevin Hilman nop 2258bd22949SKevin Hilman nop 2268bd22949SKevin Hilman nop 2278bd22949SKevin Hilman nop 22889139dceSPeter 'p2' De Schrijver bl wait_sdrc_ok 2298bd22949SKevin Hilman 2308bd22949SKevin Hilman ldmfd sp!, {r0-r12, pc} @ restore regs and return 2310795a75aSTero Kristorestore_es3: 2320795a75aSTero Kristo /*b restore_es3*/ @ Enable to debug restore code 2330795a75aSTero Kristo ldr r5, pm_prepwstst_core_p 2340795a75aSTero Kristo ldr r4, [r5] 2350795a75aSTero Kristo and r4, r4, #0x3 2360795a75aSTero Kristo cmp r4, #0x0 @ Check if previous power state of CORE is OFF 2370795a75aSTero Kristo bne restore 2380795a75aSTero Kristo adr r0, es3_sdrc_fix 2390795a75aSTero Kristo ldr r1, sram_base 2400795a75aSTero Kristo ldr r2, es3_sdrc_fix_sz 2410795a75aSTero Kristo mov r2, r2, ror #2 2420795a75aSTero Kristocopy_to_sram: 2430795a75aSTero Kristo ldmia r0!, {r3} @ val = *src 2440795a75aSTero Kristo stmia r1!, {r3} @ *dst = val 2450795a75aSTero Kristo subs r2, r2, #0x1 @ num_words-- 2460795a75aSTero Kristo bne copy_to_sram 2470795a75aSTero Kristo ldr r1, sram_base 2480795a75aSTero Kristo blx r1 2498bd22949SKevin Hilmanrestore: 2508bd22949SKevin Hilman /* b restore*/ @ Enable to debug restore code 2518bd22949SKevin Hilman /* Check what was the reason for mpu reset and store the reason in r9*/ 2528bd22949SKevin Hilman /* 1 - Only L1 and logic lost */ 2538bd22949SKevin Hilman /* 2 - Only L2 lost - In this case, we wont be here */ 2548bd22949SKevin Hilman /* 3 - Both L1 and L2 lost */ 2558bd22949SKevin Hilman ldr r1, pm_pwstctrl_mpu 2568bd22949SKevin Hilman ldr r2, [r1] 2578bd22949SKevin Hilman and r2, r2, #0x3 2588bd22949SKevin Hilman cmp r2, #0x0 @ Check if target power state was OFF or RET 2598bd22949SKevin Hilman moveq r9, #0x3 @ MPU OFF => L1 and L2 lost 2608bd22949SKevin Hilman movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation 2618bd22949SKevin Hilman bne logic_l1_restore 26227d59a4aSTero Kristo ldr r0, control_stat 26327d59a4aSTero Kristo ldr r1, [r0] 26427d59a4aSTero Kristo and r1, #0x700 26527d59a4aSTero Kristo cmp r1, #0x300 26627d59a4aSTero Kristo beq l2_inv_gp 26727d59a4aSTero Kristo mov r0, #40 @ set service ID for PPA 26827d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 26927d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 27027d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 27127d59a4aSTero Kristo mov r6, #0xff 27227d59a4aSTero Kristo adr r3, l2_inv_api_params @ r3 points to dummy parameters 27327d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 27427d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 27527d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 27627d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 27727d59a4aSTero Kristo mov r0, #42 @ set service ID for PPA 27827d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 27927d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 28027d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 28127d59a4aSTero Kristo mov r6, #0xff 282a087cad9STero Kristo ldr r4, scratchpad_base 283a087cad9STero Kristo ldr r3, [r4, #0xBC] @ r3 points to parameters 28427d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 28527d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 28627d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 28727d59a4aSTero Kristo 28879dcfdd4STero Kristo#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 28979dcfdd4STero Kristo /* Restore L2 aux control register */ 29079dcfdd4STero Kristo @ set service ID for PPA 29179dcfdd4STero Kristo mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 29279dcfdd4STero Kristo mov r12, r0 @ copy service ID in r12 29379dcfdd4STero Kristo mov r1, #0 @ set task ID for ROM code in r1 29479dcfdd4STero Kristo mov r2, #4 @ set some flags in r2, r6 29579dcfdd4STero Kristo mov r6, #0xff 29679dcfdd4STero Kristo ldr r4, scratchpad_base 29779dcfdd4STero Kristo ldr r3, [r4, #0xBC] 29879dcfdd4STero Kristo adds r3, r3, #8 @ r3 points to parameters 29979dcfdd4STero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 30079dcfdd4STero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 30179dcfdd4STero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 30279dcfdd4STero Kristo#endif 30327d59a4aSTero Kristo b logic_l1_restore 30427d59a4aSTero Kristol2_inv_api_params: 30527d59a4aSTero Kristo .word 0x1, 0x00 30627d59a4aSTero Kristol2_inv_gp: 3078bd22949SKevin Hilman /* Execute smi to invalidate L2 cache */ 3088bd22949SKevin Hilman mov r12, #0x1 @ set up to invalide L2 3098bd22949SKevin Hilmansmi: .word 0xE1600070 @ Call SMI monitor (smieq) 31027d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 311a087cad9STero Kristo ldr r4, scratchpad_base 312a087cad9STero Kristo ldr r3, [r4,#0xBC] 313a087cad9STero Kristo ldr r0, [r3,#4] 31427d59a4aSTero Kristo mov r12, #0x3 31527d59a4aSTero Kristo .word 0xE1600070 @ Call SMI monitor (smieq) 31679dcfdd4STero Kristo ldr r4, scratchpad_base 31779dcfdd4STero Kristo ldr r3, [r4,#0xBC] 31879dcfdd4STero Kristo ldr r0, [r3,#12] 31979dcfdd4STero Kristo mov r12, #0x2 32079dcfdd4STero Kristo .word 0xE1600070 @ Call SMI monitor (smieq) 3218bd22949SKevin Hilmanlogic_l1_restore: 3228bd22949SKevin Hilman mov r1, #0 3238bd22949SKevin Hilman /* Invalidate all instruction caches to PoU 3248bd22949SKevin Hilman * and flush branch target cache */ 3258bd22949SKevin Hilman mcr p15, 0, r1, c7, c5, 0 3268bd22949SKevin Hilman 3278bd22949SKevin Hilman ldr r4, scratchpad_base 3288bd22949SKevin Hilman ldr r3, [r4,#0xBC] 32979dcfdd4STero Kristo adds r3, r3, #16 3308bd22949SKevin Hilman ldmia r3!, {r4-r6} 3318bd22949SKevin Hilman mov sp, r4 3328bd22949SKevin Hilman msr spsr_cxsf, r5 3338bd22949SKevin Hilman mov lr, r6 3348bd22949SKevin Hilman 3358bd22949SKevin Hilman ldmia r3!, {r4-r9} 3368bd22949SKevin Hilman /* Coprocessor access Control Register */ 3378bd22949SKevin Hilman mcr p15, 0, r4, c1, c0, 2 3388bd22949SKevin Hilman 3398bd22949SKevin Hilman /* TTBR0 */ 3408bd22949SKevin Hilman MCR p15, 0, r5, c2, c0, 0 3418bd22949SKevin Hilman /* TTBR1 */ 3428bd22949SKevin Hilman MCR p15, 0, r6, c2, c0, 1 3438bd22949SKevin Hilman /* Translation table base control register */ 3448bd22949SKevin Hilman MCR p15, 0, r7, c2, c0, 2 3458bd22949SKevin Hilman /*domain access Control Register */ 3468bd22949SKevin Hilman MCR p15, 0, r8, c3, c0, 0 3478bd22949SKevin Hilman /* data fault status Register */ 3488bd22949SKevin Hilman MCR p15, 0, r9, c5, c0, 0 3498bd22949SKevin Hilman 3508bd22949SKevin Hilman ldmia r3!,{r4-r8} 3518bd22949SKevin Hilman /* instruction fault status Register */ 3528bd22949SKevin Hilman MCR p15, 0, r4, c5, c0, 1 3538bd22949SKevin Hilman /*Data Auxiliary Fault Status Register */ 3548bd22949SKevin Hilman MCR p15, 0, r5, c5, c1, 0 3558bd22949SKevin Hilman /*Instruction Auxiliary Fault Status Register*/ 3568bd22949SKevin Hilman MCR p15, 0, r6, c5, c1, 1 3578bd22949SKevin Hilman /*Data Fault Address Register */ 3588bd22949SKevin Hilman MCR p15, 0, r7, c6, c0, 0 3598bd22949SKevin Hilman /*Instruction Fault Address Register*/ 3608bd22949SKevin Hilman MCR p15, 0, r8, c6, c0, 2 3618bd22949SKevin Hilman ldmia r3!,{r4-r7} 3628bd22949SKevin Hilman 3638bd22949SKevin Hilman /* user r/w thread and process ID */ 3648bd22949SKevin Hilman MCR p15, 0, r4, c13, c0, 2 3658bd22949SKevin Hilman /* user ro thread and process ID */ 3668bd22949SKevin Hilman MCR p15, 0, r5, c13, c0, 3 3678bd22949SKevin Hilman /*Privileged only thread and process ID */ 3688bd22949SKevin Hilman MCR p15, 0, r6, c13, c0, 4 3698bd22949SKevin Hilman /* cache size selection */ 3708bd22949SKevin Hilman MCR p15, 2, r7, c0, c0, 0 3718bd22949SKevin Hilman ldmia r3!,{r4-r8} 3728bd22949SKevin Hilman /* Data TLB lockdown registers */ 3738bd22949SKevin Hilman MCR p15, 0, r4, c10, c0, 0 3748bd22949SKevin Hilman /* Instruction TLB lockdown registers */ 3758bd22949SKevin Hilman MCR p15, 0, r5, c10, c0, 1 3768bd22949SKevin Hilman /* Secure or Nonsecure Vector Base Address */ 3778bd22949SKevin Hilman MCR p15, 0, r6, c12, c0, 0 3788bd22949SKevin Hilman /* FCSE PID */ 3798bd22949SKevin Hilman MCR p15, 0, r7, c13, c0, 0 3808bd22949SKevin Hilman /* Context PID */ 3818bd22949SKevin Hilman MCR p15, 0, r8, c13, c0, 1 3828bd22949SKevin Hilman 3838bd22949SKevin Hilman ldmia r3!,{r4-r5} 3848bd22949SKevin Hilman /* primary memory remap register */ 3858bd22949SKevin Hilman MCR p15, 0, r4, c10, c2, 0 3868bd22949SKevin Hilman /*normal memory remap register */ 3878bd22949SKevin Hilman MCR p15, 0, r5, c10, c2, 1 3888bd22949SKevin Hilman 3898bd22949SKevin Hilman /* Restore cpsr */ 3908bd22949SKevin Hilman ldmia r3!,{r4} /*load CPSR from SDRAM*/ 3918bd22949SKevin Hilman msr cpsr, r4 /*store cpsr */ 3928bd22949SKevin Hilman 3938bd22949SKevin Hilman /* Enabling MMU here */ 3948bd22949SKevin Hilman mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */ 3958bd22949SKevin Hilman /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/ 3968bd22949SKevin Hilman and r7, #0x7 3978bd22949SKevin Hilman cmp r7, #0x0 3988bd22949SKevin Hilman beq usettbr0 3998bd22949SKevin Hilmanttbr_error: 4008bd22949SKevin Hilman /* More work needs to be done to support N[0:2] value other than 0 4018bd22949SKevin Hilman * So looping here so that the error can be detected 4028bd22949SKevin Hilman */ 4038bd22949SKevin Hilman b ttbr_error 4048bd22949SKevin Hilmanusettbr0: 4058bd22949SKevin Hilman mrc p15, 0, r2, c2, c0, 0 4068bd22949SKevin Hilman ldr r5, ttbrbit_mask 4078bd22949SKevin Hilman and r2, r5 4088bd22949SKevin Hilman mov r4, pc 4098bd22949SKevin Hilman ldr r5, table_index_mask 4108bd22949SKevin Hilman and r4, r5 /* r4 = 31 to 20 bits of pc */ 4118bd22949SKevin Hilman /* Extract the value to be written to table entry */ 4128bd22949SKevin Hilman ldr r1, table_entry 4138bd22949SKevin Hilman add r1, r1, r4 /* r1 has value to be written to table entry*/ 4148bd22949SKevin Hilman /* Getting the address of table entry to modify */ 4158bd22949SKevin Hilman lsr r4, #18 4168bd22949SKevin Hilman add r2, r4 /* r2 has the location which needs to be modified */ 4178bd22949SKevin Hilman /* Storing previous entry of location being modified */ 4188bd22949SKevin Hilman ldr r5, scratchpad_base 4198bd22949SKevin Hilman ldr r4, [r2] 4208bd22949SKevin Hilman str r4, [r5, #0xC0] 4218bd22949SKevin Hilman /* Modify the table entry */ 4228bd22949SKevin Hilman str r1, [r2] 4238bd22949SKevin Hilman /* Storing address of entry being modified 4248bd22949SKevin Hilman * - will be restored after enabling MMU */ 4258bd22949SKevin Hilman ldr r5, scratchpad_base 4268bd22949SKevin Hilman str r2, [r5, #0xC4] 4278bd22949SKevin Hilman 4288bd22949SKevin Hilman mov r0, #0 4298bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer 4308bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array 4318bd22949SKevin Hilman mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB 4328bd22949SKevin Hilman mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB 4338bd22949SKevin Hilman /* Restore control register but dont enable caches here*/ 4348bd22949SKevin Hilman /* Caches will be enabled after restoring MMU table entry */ 4358bd22949SKevin Hilman ldmia r3!, {r4} 4368bd22949SKevin Hilman /* Store previous value of control register in scratchpad */ 4378bd22949SKevin Hilman str r4, [r5, #0xC8] 4388bd22949SKevin Hilman ldr r2, cache_pred_disable_mask 4398bd22949SKevin Hilman and r4, r2 4408bd22949SKevin Hilman mcr p15, 0, r4, c1, c0, 0 4418bd22949SKevin Hilman 4428bd22949SKevin Hilman ldmfd sp!, {r0-r12, pc} @ restore regs and return 4438bd22949SKevin Hilmansave_context_wfi: 4448bd22949SKevin Hilman /*b save_context_wfi*/ @ enable to debug save code 4458bd22949SKevin Hilman mov r8, r0 /* Store SDRAM address in r8 */ 446a087cad9STero Kristo mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register 447a087cad9STero Kristo mov r4, #0x1 @ Number of parameters for restore call 44879dcfdd4STero Kristo stmia r8!, {r4-r5} @ Push parameters for restore call 44979dcfdd4STero Kristo mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register 45079dcfdd4STero Kristo stmia r8!, {r4-r5} @ Push parameters for restore call 4518bd22949SKevin Hilman /* Check what that target sleep state is:stored in r1*/ 4528bd22949SKevin Hilman /* 1 - Only L1 and logic lost */ 4538bd22949SKevin Hilman /* 2 - Only L2 lost */ 4548bd22949SKevin Hilman /* 3 - Both L1 and L2 lost */ 4558bd22949SKevin Hilman cmp r1, #0x2 /* Only L2 lost */ 4568bd22949SKevin Hilman beq clean_l2 4578bd22949SKevin Hilman cmp r1, #0x1 /* L2 retained */ 4588bd22949SKevin Hilman /* r9 stores whether to clean L2 or not*/ 4598bd22949SKevin Hilman moveq r9, #0x0 /* Dont Clean L2 */ 4608bd22949SKevin Hilman movne r9, #0x1 /* Clean L2 */ 4618bd22949SKevin Hilmanl1_logic_lost: 4628bd22949SKevin Hilman /* Store sp and spsr to SDRAM */ 4638bd22949SKevin Hilman mov r4, sp 4648bd22949SKevin Hilman mrs r5, spsr 4658bd22949SKevin Hilman mov r6, lr 4668bd22949SKevin Hilman stmia r8!, {r4-r6} 4678bd22949SKevin Hilman /* Save all ARM registers */ 4688bd22949SKevin Hilman /* Coprocessor access control register */ 4698bd22949SKevin Hilman mrc p15, 0, r6, c1, c0, 2 4708bd22949SKevin Hilman stmia r8!, {r6} 4718bd22949SKevin Hilman /* TTBR0, TTBR1 and Translation table base control */ 4728bd22949SKevin Hilman mrc p15, 0, r4, c2, c0, 0 4738bd22949SKevin Hilman mrc p15, 0, r5, c2, c0, 1 4748bd22949SKevin Hilman mrc p15, 0, r6, c2, c0, 2 4758bd22949SKevin Hilman stmia r8!, {r4-r6} 4768bd22949SKevin Hilman /* Domain access control register, data fault status register, 4778bd22949SKevin Hilman and instruction fault status register */ 4788bd22949SKevin Hilman mrc p15, 0, r4, c3, c0, 0 4798bd22949SKevin Hilman mrc p15, 0, r5, c5, c0, 0 4808bd22949SKevin Hilman mrc p15, 0, r6, c5, c0, 1 4818bd22949SKevin Hilman stmia r8!, {r4-r6} 4828bd22949SKevin Hilman /* Data aux fault status register, instruction aux fault status, 4838bd22949SKevin Hilman datat fault address register and instruction fault address register*/ 4848bd22949SKevin Hilman mrc p15, 0, r4, c5, c1, 0 4858bd22949SKevin Hilman mrc p15, 0, r5, c5, c1, 1 4868bd22949SKevin Hilman mrc p15, 0, r6, c6, c0, 0 4878bd22949SKevin Hilman mrc p15, 0, r7, c6, c0, 2 4888bd22949SKevin Hilman stmia r8!, {r4-r7} 4898bd22949SKevin Hilman /* user r/w thread and process ID, user r/o thread and process ID, 4908bd22949SKevin Hilman priv only thread and process ID, cache size selection */ 4918bd22949SKevin Hilman mrc p15, 0, r4, c13, c0, 2 4928bd22949SKevin Hilman mrc p15, 0, r5, c13, c0, 3 4938bd22949SKevin Hilman mrc p15, 0, r6, c13, c0, 4 4948bd22949SKevin Hilman mrc p15, 2, r7, c0, c0, 0 4958bd22949SKevin Hilman stmia r8!, {r4-r7} 4968bd22949SKevin Hilman /* Data TLB lockdown, instruction TLB lockdown registers */ 4978bd22949SKevin Hilman mrc p15, 0, r5, c10, c0, 0 4988bd22949SKevin Hilman mrc p15, 0, r6, c10, c0, 1 4998bd22949SKevin Hilman stmia r8!, {r5-r6} 5008bd22949SKevin Hilman /* Secure or non secure vector base address, FCSE PID, Context PID*/ 5018bd22949SKevin Hilman mrc p15, 0, r4, c12, c0, 0 5028bd22949SKevin Hilman mrc p15, 0, r5, c13, c0, 0 5038bd22949SKevin Hilman mrc p15, 0, r6, c13, c0, 1 5048bd22949SKevin Hilman stmia r8!, {r4-r6} 5058bd22949SKevin Hilman /* Primary remap, normal remap registers */ 5068bd22949SKevin Hilman mrc p15, 0, r4, c10, c2, 0 5078bd22949SKevin Hilman mrc p15, 0, r5, c10, c2, 1 5088bd22949SKevin Hilman stmia r8!,{r4-r5} 5098bd22949SKevin Hilman 5108bd22949SKevin Hilman /* Store current cpsr*/ 5118bd22949SKevin Hilman mrs r2, cpsr 5128bd22949SKevin Hilman stmia r8!, {r2} 5138bd22949SKevin Hilman 5148bd22949SKevin Hilman mrc p15, 0, r4, c1, c0, 0 5158bd22949SKevin Hilman /* save control register */ 5168bd22949SKevin Hilman stmia r8!, {r4} 5178bd22949SKevin Hilmanclean_caches: 5188bd22949SKevin Hilman /* Clean Data or unified cache to POU*/ 5198bd22949SKevin Hilman /* How to invalidate only L1 cache???? - #FIX_ME# */ 5208bd22949SKevin Hilman /* mcr p15, 0, r11, c7, c11, 1 */ 5218bd22949SKevin Hilman cmp r9, #1 /* Check whether L2 inval is required or not*/ 5228bd22949SKevin Hilman bne skip_l2_inval 5238bd22949SKevin Hilmanclean_l2: 5240bd40535SRichard Woodruff /* 5250bd40535SRichard Woodruff * Jump out to kernel flush routine 5260bd40535SRichard Woodruff * - reuse that code is better 5270bd40535SRichard Woodruff * - it executes in a cached space so is faster than refetch per-block 5280bd40535SRichard Woodruff * - should be faster and will change with kernel 5290bd40535SRichard Woodruff * - 'might' have to copy address, load and jump to it 5300bd40535SRichard Woodruff * - lr is used since we are running in SRAM currently. 5310bd40535SRichard Woodruff */ 5320bd40535SRichard Woodruff ldr r1, kernel_flush 5330bd40535SRichard Woodruff mov lr, pc 5340bd40535SRichard Woodruff bx r1 5350bd40535SRichard Woodruff 5368bd22949SKevin Hilmanskip_l2_inval: 5378bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 5388bd22949SKevin Hilman mov r1, #0 5398bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 4 5408bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 5 5418bd22949SKevin Hilman 5428bd22949SKevin Hilman wfi @ wait for interrupt 5438bd22949SKevin Hilman nop 5448bd22949SKevin Hilman nop 5458bd22949SKevin Hilman nop 5468bd22949SKevin Hilman nop 5478bd22949SKevin Hilman nop 5488bd22949SKevin Hilman nop 5498bd22949SKevin Hilman nop 5508bd22949SKevin Hilman nop 5518bd22949SKevin Hilman nop 5528bd22949SKevin Hilman nop 55389139dceSPeter 'p2' De Schrijver bl wait_sdrc_ok 5548bd22949SKevin Hilman /* restore regs and return */ 5558bd22949SKevin Hilman ldmfd sp!, {r0-r12, pc} 5568bd22949SKevin Hilman 55789139dceSPeter 'p2' De Schrijver/* Make sure SDRC accesses are ok */ 55889139dceSPeter 'p2' De Schrijverwait_sdrc_ok: 5599d93b8a2SPeter 'p2' De Schrijver 5609d93b8a2SPeter 'p2' De Schrijver/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */ 5619d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest_ckgen 5629d93b8a2SPeter 'p2' De Schrijverwait_dpll3_lock: 56389139dceSPeter 'p2' De Schrijver ldr r5, [r4] 5649d93b8a2SPeter 'p2' De Schrijver tst r5, #1 5659d93b8a2SPeter 'p2' De Schrijver beq wait_dpll3_lock 5669d93b8a2SPeter 'p2' De Schrijver 5679d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest1_core 5689d93b8a2SPeter 'p2' De Schrijverwait_sdrc_ready: 5699d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 5709d93b8a2SPeter 'p2' De Schrijver tst r5, #0x2 5719d93b8a2SPeter 'p2' De Schrijver bne wait_sdrc_ready 5729d93b8a2SPeter 'p2' De Schrijver /* allow DLL powerdown upon hw idle req */ 5738bd22949SKevin Hilman ldr r4, sdrc_power 5748bd22949SKevin Hilman ldr r5, [r4] 5758bd22949SKevin Hilman bic r5, r5, #0x40 5768bd22949SKevin Hilman str r5, [r4] 5779d93b8a2SPeter 'p2' De Schrijveris_dll_in_lock_mode: 5789d93b8a2SPeter 'p2' De Schrijver 57989139dceSPeter 'p2' De Schrijver /* Is dll in lock mode? */ 58089139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 58189139dceSPeter 'p2' De Schrijver ldr r5, [r4] 58289139dceSPeter 'p2' De Schrijver tst r5, #0x4 58389139dceSPeter 'p2' De Schrijver bxne lr 58489139dceSPeter 'p2' De Schrijver /* wait till dll locks */ 5859d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_timed: 5869d93b8a2SPeter 'p2' De Schrijver ldr r4, wait_dll_lock_counter 5879d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 5889d93b8a2SPeter 'p2' De Schrijver str r4, wait_dll_lock_counter 58989139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_status 5909d93b8a2SPeter 'p2' De Schrijver mov r6, #8 /* Wait 20uS for lock */ 5919d93b8a2SPeter 'p2' De Schrijverwait_dll_lock: 5929d93b8a2SPeter 'p2' De Schrijver subs r6, r6, #0x1 5939d93b8a2SPeter 'p2' De Schrijver beq kick_dll 59489139dceSPeter 'p2' De Schrijver ldr r5, [r4] 59589139dceSPeter 'p2' De Schrijver and r5, r5, #0x4 59689139dceSPeter 'p2' De Schrijver cmp r5, #0x4 59789139dceSPeter 'p2' De Schrijver bne wait_dll_lock 5988bd22949SKevin Hilman bx lr 59989139dceSPeter 'p2' De Schrijver 6009d93b8a2SPeter 'p2' De Schrijver /* disable/reenable DLL if not locked */ 6019d93b8a2SPeter 'p2' De Schrijverkick_dll: 6029d93b8a2SPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 6039d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 6049d93b8a2SPeter 'p2' De Schrijver mov r6, r5 6059d93b8a2SPeter 'p2' De Schrijver bic r6, #(1<<3) /* disable dll */ 6069d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 6079d93b8a2SPeter 'p2' De Schrijver dsb 6089d93b8a2SPeter 'p2' De Schrijver orr r6, r6, #(1<<3) /* enable dll */ 6099d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 6109d93b8a2SPeter 'p2' De Schrijver dsb 6119d93b8a2SPeter 'p2' De Schrijver ldr r4, kick_counter 6129d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 6139d93b8a2SPeter 'p2' De Schrijver str r4, kick_counter 6149d93b8a2SPeter 'p2' De Schrijver b wait_dll_lock_timed 6159d93b8a2SPeter 'p2' De Schrijver 61689139dceSPeter 'p2' De Schrijvercm_idlest1_core: 61789139dceSPeter 'p2' De Schrijver .word CM_IDLEST1_CORE_V 6189d93b8a2SPeter 'p2' De Schrijvercm_idlest_ckgen: 6199d93b8a2SPeter 'p2' De Schrijver .word CM_IDLEST_CKGEN_V 62089139dceSPeter 'p2' De Schrijversdrc_dlla_status: 62189139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_STATUS_V 62289139dceSPeter 'p2' De Schrijversdrc_dlla_ctrl: 62389139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_CTRL_V 6248bd22949SKevin Hilmanpm_prepwstst_core: 6258bd22949SKevin Hilman .word PM_PREPWSTST_CORE_V 6260795a75aSTero Kristopm_prepwstst_core_p: 6270795a75aSTero Kristo .word PM_PREPWSTST_CORE_P 6288bd22949SKevin Hilmanpm_prepwstst_mpu: 6298bd22949SKevin Hilman .word PM_PREPWSTST_MPU_V 6308bd22949SKevin Hilmanpm_pwstctrl_mpu: 6318bd22949SKevin Hilman .word PM_PWSTCTRL_MPU_P 6328bd22949SKevin Hilmanscratchpad_base: 6338bd22949SKevin Hilman .word SCRATCHPAD_BASE_P 6340795a75aSTero Kristosram_base: 6350795a75aSTero Kristo .word SRAM_BASE_P + 0x8000 6368bd22949SKevin Hilmansdrc_power: 6378bd22949SKevin Hilman .word SDRC_POWER_V 6388bd22949SKevin Hilmanclk_stabilize_delay: 6398bd22949SKevin Hilman .word 0x000001FF 6408bd22949SKevin Hilmanassoc_mask: 6418bd22949SKevin Hilman .word 0x3ff 6428bd22949SKevin Hilmannumset_mask: 6438bd22949SKevin Hilman .word 0x7fff 6448bd22949SKevin Hilmanttbrbit_mask: 6458bd22949SKevin Hilman .word 0xFFFFC000 6468bd22949SKevin Hilmantable_index_mask: 6478bd22949SKevin Hilman .word 0xFFF00000 6488bd22949SKevin Hilmantable_entry: 6498bd22949SKevin Hilman .word 0x00000C02 6508bd22949SKevin Hilmancache_pred_disable_mask: 6518bd22949SKevin Hilman .word 0xFFFFE7FB 65227d59a4aSTero Kristocontrol_stat: 65327d59a4aSTero Kristo .word CONTROL_STAT 6540bd40535SRichard Woodruffkernel_flush: 6550bd40535SRichard Woodruff .word v7_flush_dcache_all 6569d93b8a2SPeter 'p2' De Schrijver /* 6579d93b8a2SPeter 'p2' De Schrijver * When exporting to userspace while the counters are in SRAM, 6589d93b8a2SPeter 'p2' De Schrijver * these 2 words need to be at the end to facilitate retrival! 6599d93b8a2SPeter 'p2' De Schrijver */ 6609d93b8a2SPeter 'p2' De Schrijverkick_counter: 6619d93b8a2SPeter 'p2' De Schrijver .word 0 6629d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_counter: 6639d93b8a2SPeter 'p2' De Schrijver .word 0 6648bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend_sz) 6658bd22949SKevin Hilman .word . - omap34xx_cpu_suspend 666