18bd22949SKevin Hilman/* 28bd22949SKevin Hilman * (C) Copyright 2007 38bd22949SKevin Hilman * Texas Instruments 48bd22949SKevin Hilman * Karthik Dasu <karthik-dp@ti.com> 58bd22949SKevin Hilman * 68bd22949SKevin Hilman * (C) Copyright 2004 78bd22949SKevin Hilman * Texas Instruments, <www.ti.com> 88bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 98bd22949SKevin Hilman * 108bd22949SKevin Hilman * This program is free software; you can redistribute it and/or 118bd22949SKevin Hilman * modify it under the terms of the GNU General Public License as 128bd22949SKevin Hilman * published by the Free Software Foundation; either version 2 of 138bd22949SKevin Hilman * the License, or (at your option) any later version. 148bd22949SKevin Hilman * 158bd22949SKevin Hilman * This program is distributed in the hope that it will be useful, 168bd22949SKevin Hilman * but WITHOUT ANY WARRANTY; without even the implied warranty of 178bd22949SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 188bd22949SKevin Hilman * GNU General Public License for more details. 198bd22949SKevin Hilman * 208bd22949SKevin Hilman * You should have received a copy of the GNU General Public License 218bd22949SKevin Hilman * along with this program; if not, write to the Free Software 228bd22949SKevin Hilman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 238bd22949SKevin Hilman * MA 02111-1307 USA 248bd22949SKevin Hilman */ 258bd22949SKevin Hilman#include <linux/linkage.h> 268bd22949SKevin Hilman#include <asm/assembler.h> 27b4b36fd9SJean Pihet#include <plat/sram.h> 288bd22949SKevin Hilman#include <mach/io.h> 298bd22949SKevin Hilman 3059fb659bSPaul Walmsley#include "cm2xxx_3xxx.h" 3159fb659bSPaul Walmsley#include "prm2xxx_3xxx.h" 328bd22949SKevin Hilman#include "sdrc.h" 334814ced5SPaul Walmsley#include "control.h" 348bd22949SKevin Hilman 35fe360e1cSJean Pihet/* 36fe360e1cSJean Pihet * Registers access definitions 37fe360e1cSJean Pihet */ 38fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_OFFS 0xc 39fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ 40fe360e1cSJean Pihet (SDRC_SCRATCHPAD_SEM_OFFS) 41fe360e1cSJean Pihet#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ 42fe360e1cSJean Pihet OMAP3430_PM_PREPWSTST 4337903009SAbhijit Pagare#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 4489139dceSPeter 'p2' De Schrijver#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 459d93b8a2SPeter 'p2' De Schrijver#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) 46fe360e1cSJean Pihet#define SRAM_BASE_P OMAP3_SRAM_PA 47fe360e1cSJean Pihet#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS 48fe360e1cSJean Pihet#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ 49fe360e1cSJean Pihet OMAP36XX_CONTROL_MEM_RTA_CTRL) 50fe360e1cSJean Pihet 51fe360e1cSJean Pihet/* Move this as correct place is available */ 52fe360e1cSJean Pihet#define SCRATCHPAD_MEM_OFFS 0x310 53fe360e1cSJean Pihet#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ 54fe360e1cSJean Pihet OMAP343X_CONTROL_MEM_WKUP +\ 55fe360e1cSJean Pihet SCRATCHPAD_MEM_OFFS) 568bd22949SKevin Hilman#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 570795a75aSTero Kristo#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 580795a75aSTero Kristo#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 590795a75aSTero Kristo#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) 600795a75aSTero Kristo#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) 610795a75aSTero Kristo#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) 620795a75aSTero Kristo#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) 630795a75aSTero Kristo#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) 6489139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 6589139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 668bd22949SKevin Hilman 67dd313947SDave Martin/* 68dd313947SDave Martin * This file needs be built unconditionally as ARM to interoperate correctly 69dd313947SDave Martin * with non-Thumb-2-capable firmware. 70dd313947SDave Martin */ 71dd313947SDave Martin .arm 72a89b6f00SRajendra Nayak 73d3cdfd2aSJean Pihet/* 74d3cdfd2aSJean Pihet * API functions 75d3cdfd2aSJean Pihet */ 76a89b6f00SRajendra Nayak 77f7dfe3d8SJean Pihet/* 78f7dfe3d8SJean Pihet * The "get_*restore_pointer" functions are used to provide a 79f7dfe3d8SJean Pihet * physical restore address where the ROM code jumps while waking 80f7dfe3d8SJean Pihet * up from MPU OFF/OSWR state. 81f7dfe3d8SJean Pihet * The restore pointer is stored into the scratchpad. 82f7dfe3d8SJean Pihet */ 83f7dfe3d8SJean Pihet 84a89b6f00SRajendra Nayak .text 858bd22949SKevin Hilman/* Function call to get the restore pointer for resume from OFF */ 868bd22949SKevin HilmanENTRY(get_restore_pointer) 878bd22949SKevin Hilman stmfd sp!, {lr} @ save registers on stack 888bd22949SKevin Hilman adr r0, restore 898bd22949SKevin Hilman ldmfd sp!, {pc} @ restore regs and return 90dd313947SDave MartinENDPROC(get_restore_pointer) 91dd313947SDave Martin .align 928bd22949SKevin HilmanENTRY(get_restore_pointer_sz) 930795a75aSTero Kristo .word . - get_restore_pointer 941e81bc01SJean Pihet 95458e999eSNishanth Menon .text 96458e999eSNishanth Menon/* Function call to get the restore pointer for 3630 resume from OFF */ 97458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer) 98458e999eSNishanth Menon stmfd sp!, {lr} @ save registers on stack 99458e999eSNishanth Menon adr r0, restore_3630 100458e999eSNishanth Menon ldmfd sp!, {pc} @ restore regs and return 101dd313947SDave MartinENDPROC(get_omap3630_restore_pointer) 102dd313947SDave Martin .align 103458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer_sz) 104458e999eSNishanth Menon .word . - get_omap3630_restore_pointer 1050795a75aSTero Kristo 1060795a75aSTero Kristo .text 1071e81bc01SJean Pihet/* Function call to get the restore pointer for ES3 to resume from OFF */ 1081e81bc01SJean PihetENTRY(get_es3_restore_pointer) 1091e81bc01SJean Pihet stmfd sp!, {lr} @ save registers on stack 1101e81bc01SJean Pihet adr r0, restore_es3 1111e81bc01SJean Pihet ldmfd sp!, {pc} @ restore regs and return 112dd313947SDave MartinENDPROC(get_es3_restore_pointer) 113dd313947SDave Martin .align 1141e81bc01SJean PihetENTRY(get_es3_restore_pointer_sz) 1151e81bc01SJean Pihet .word . - get_es3_restore_pointer 1161e81bc01SJean Pihet 1171e81bc01SJean Pihet .text 118c4236d2eSPeter 'p2' De Schrijver/* 119c4236d2eSPeter 'p2' De Schrijver * L2 cache needs to be toggled for stable OFF mode functionality on 3630. 1201e81bc01SJean Pihet * This function sets up a flag that will allow for this toggling to take 121f7dfe3d8SJean Pihet * place on 3630. Hopefully some version in the future may not need this. 122c4236d2eSPeter 'p2' De Schrijver */ 123c4236d2eSPeter 'p2' De SchrijverENTRY(enable_omap3630_toggle_l2_on_restore) 124c4236d2eSPeter 'p2' De Schrijver stmfd sp!, {lr} @ save registers on stack 125c4236d2eSPeter 'p2' De Schrijver /* Setup so that we will disable and enable l2 */ 126c4236d2eSPeter 'p2' De Schrijver mov r1, #0x1 127dd313947SDave Martin adrl r2, l2dis_3630 @ may be too distant for plain adr 128dd313947SDave Martin str r1, [r2] 129c4236d2eSPeter 'p2' De Schrijver ldmfd sp!, {pc} @ restore regs and return 130dd313947SDave MartinENDPROC(enable_omap3630_toggle_l2_on_restore) 131c4236d2eSPeter 'p2' De Schrijver 132bb1c9034SJean Pihet .text 13327d59a4aSTero Kristo/* Function to call rom code to save secure ram context */ 134b6338bdcSJean Pihet .align 3 13527d59a4aSTero KristoENTRY(save_secure_ram_context) 136857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 13727d59a4aSTero Kristo adr r3, api_params @ r3 points to parameters 13827d59a4aSTero Kristo str r0, [r3,#0x4] @ r0 has sdram address 13927d59a4aSTero Kristo ldr r12, high_mask 14027d59a4aSTero Kristo and r3, r3, r12 14127d59a4aSTero Kristo ldr r12, sram_phy_addr_mask 14227d59a4aSTero Kristo orr r3, r3, r12 14327d59a4aSTero Kristo mov r0, #25 @ set service ID for PPA 14427d59a4aSTero Kristo mov r12, r0 @ copy secure service ID in r12 14527d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 146ba50ea7eSKalle Jokiniemi mov r2, #4 @ set some flags in r2, r6 14727d59a4aSTero Kristo mov r6, #0xff 1484444d712SSantosh Shilimkar dsb @ data write barrier 1494444d712SSantosh Shilimkar dmb @ data memory barrier 15076d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 15127d59a4aSTero Kristo nop 15227d59a4aSTero Kristo nop 15327d59a4aSTero Kristo nop 15427d59a4aSTero Kristo nop 155857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} 156dd313947SDave Martin .align 15727d59a4aSTero Kristosram_phy_addr_mask: 15827d59a4aSTero Kristo .word SRAM_BASE_P 15927d59a4aSTero Kristohigh_mask: 16027d59a4aSTero Kristo .word 0xffff 16127d59a4aSTero Kristoapi_params: 16227d59a4aSTero Kristo .word 0x4, 0x0, 0x0, 0x1, 0x1 163dd313947SDave MartinENDPROC(save_secure_ram_context) 16427d59a4aSTero KristoENTRY(save_secure_ram_context_sz) 16527d59a4aSTero Kristo .word . - save_secure_ram_context 16627d59a4aSTero Kristo 1678bd22949SKevin Hilman/* 168f7dfe3d8SJean Pihet * ====================== 169f7dfe3d8SJean Pihet * == Idle entry point == 170f7dfe3d8SJean Pihet * ====================== 171f7dfe3d8SJean Pihet */ 172f7dfe3d8SJean Pihet 173f7dfe3d8SJean Pihet/* 1748bd22949SKevin Hilman * Forces OMAP into idle state 1758bd22949SKevin Hilman * 176f7dfe3d8SJean Pihet * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed 177f7dfe3d8SJean Pihet * and executes the WFI instruction. Calling WFI effectively changes the 178f7dfe3d8SJean Pihet * power domains states to the desired target power states. 1798bd22949SKevin Hilman * 180f7dfe3d8SJean Pihet * 181f7dfe3d8SJean Pihet * Notes: 182bb1c9034SJean Pihet * - this code gets copied to internal SRAM at boot and after wake-up 183bb1c9034SJean Pihet * from OFF mode. The execution pointer in SRAM is _omap_sram_idle. 184f7dfe3d8SJean Pihet * - when the OMAP wakes up it continues at different execution points 185f7dfe3d8SJean Pihet * depending on the low power mode (non-OFF vs OFF modes), 186f7dfe3d8SJean Pihet * cf. 'Resume path for xxx mode' comments. 1878bd22949SKevin Hilman */ 188b6338bdcSJean Pihet .align 3 1898bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend) 190857c1b81SRussell King stmfd sp!, {r4 - r11, lr} @ save registers on stack 191d3cdfd2aSJean Pihet 192f7dfe3d8SJean Pihet /* 193c9749a35SSantosh Shilimkar * r0 contains CPU context save/restore pointer in sdram 194f7dfe3d8SJean Pihet * r1 contains information about saving context: 195f7dfe3d8SJean Pihet * 0 - No context lost 196f7dfe3d8SJean Pihet * 1 - Only L1 and logic lost 197c9749a35SSantosh Shilimkar * 2 - Only L2 lost (Even L1 is retained we clean it along with L2) 198c9749a35SSantosh Shilimkar * 3 - Both L1 and L2 lost and logic lost 199f7dfe3d8SJean Pihet */ 200f7dfe3d8SJean Pihet 201f7dfe3d8SJean Pihet /* Directly jump to WFI is the context save is not required */ 202f7dfe3d8SJean Pihet cmp r1, #0x0 203f7dfe3d8SJean Pihet beq omap3_do_wfi 204f7dfe3d8SJean Pihet 205f7dfe3d8SJean Pihet /* Otherwise fall through to the save context code */ 206f7dfe3d8SJean Pihetsave_context_wfi: 207f7dfe3d8SJean Pihet mov r8, r0 @ Store SDRAM address in r8 208f7dfe3d8SJean Pihet mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register 209f7dfe3d8SJean Pihet mov r4, #0x1 @ Number of parameters for restore call 210f7dfe3d8SJean Pihet stmia r8!, {r4-r5} @ Push parameters for restore call 211f7dfe3d8SJean Pihet mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register 212f7dfe3d8SJean Pihet stmia r8!, {r4-r5} @ Push parameters for restore call 213f7dfe3d8SJean Pihet 214f7dfe3d8SJean Pihet /* Check what that target sleep state is from r1 */ 215f7dfe3d8SJean Pihet cmp r1, #0x2 @ Only L2 lost, no need to save context 216f7dfe3d8SJean Pihet beq clean_caches 217f7dfe3d8SJean Pihet 218f7dfe3d8SJean Pihetl1_logic_lost: 21946f557cbSSantosh Shilimkar mov r4, sp @ Store sp 22046f557cbSSantosh Shilimkar mrs r5, spsr @ Store spsr 22146f557cbSSantosh Shilimkar mov r6, lr @ Store lr 222f7dfe3d8SJean Pihet stmia r8!, {r4-r6} 223f7dfe3d8SJean Pihet 22446f557cbSSantosh Shilimkar mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register 22546f557cbSSantosh Shilimkar mrc p15, 0, r5, c2, c0, 0 @ TTBR0 22646f557cbSSantosh Shilimkar mrc p15, 0, r6, c2, c0, 1 @ TTBR1 22746f557cbSSantosh Shilimkar mrc p15, 0, r7, c2, c0, 2 @ TTBCR 22846f557cbSSantosh Shilimkar stmia r8!, {r4-r7} 229f7dfe3d8SJean Pihet 23046f557cbSSantosh Shilimkar mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register 23146f557cbSSantosh Shilimkar mrc p15, 0, r5, c10, c2, 0 @ PRRR 23246f557cbSSantosh Shilimkar mrc p15, 0, r6, c10, c2, 1 @ NMRR 23346f557cbSSantosh Shilimkar stmia r8!,{r4-r6} 23446f557cbSSantosh Shilimkar 23546f557cbSSantosh Shilimkar mrc p15, 0, r4, c13, c0, 1 @ Context ID 23646f557cbSSantosh Shilimkar mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID 23746f557cbSSantosh Shilimkar mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address 23846f557cbSSantosh Shilimkar mrs r7, cpsr @ Store current cpsr 23946f557cbSSantosh Shilimkar stmia r8!, {r4-r7} 24046f557cbSSantosh Shilimkar 24146f557cbSSantosh Shilimkar mrc p15, 0, r4, c1, c0, 0 @ save control register 242f7dfe3d8SJean Pihet stmia r8!, {r4} 243f7dfe3d8SJean Pihet 244f7dfe3d8SJean Pihetclean_caches: 245f7dfe3d8SJean Pihet /* 246f7dfe3d8SJean Pihet * jump out to kernel flush routine 247f7dfe3d8SJean Pihet * - reuse that code is better 248f7dfe3d8SJean Pihet * - it executes in a cached space so is faster than refetch per-block 249f7dfe3d8SJean Pihet * - should be faster and will change with kernel 250f7dfe3d8SJean Pihet * - 'might' have to copy address, load and jump to it 25190625110SSantosh Shilimkar * Flush all data from the L1 data cache before disabling 25290625110SSantosh Shilimkar * SCTLR.C bit. 253f7dfe3d8SJean Pihet */ 254f7dfe3d8SJean Pihet ldr r1, kernel_flush 255f7dfe3d8SJean Pihet mov lr, pc 256f7dfe3d8SJean Pihet bx r1 257f7dfe3d8SJean Pihet 25890625110SSantosh Shilimkar /* 25990625110SSantosh Shilimkar * Clear the SCTLR.C bit to prevent further data cache 26090625110SSantosh Shilimkar * allocation. Clearing SCTLR.C would make all the data accesses 26190625110SSantosh Shilimkar * strongly ordered and would not hit the cache. 26290625110SSantosh Shilimkar */ 26390625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 26490625110SSantosh Shilimkar bic r0, r0, #(1 << 2) @ Disable the C bit 26590625110SSantosh Shilimkar mcr p15, 0, r0, c1, c0, 0 26690625110SSantosh Shilimkar isb 26790625110SSantosh Shilimkar 26890625110SSantosh Shilimkar /* 26990625110SSantosh Shilimkar * Invalidate L1 data cache. Even though only invalidate is 27090625110SSantosh Shilimkar * necessary exported flush API is used here. Doing clean 27190625110SSantosh Shilimkar * on already clean cache would be almost NOP. 272f7dfe3d8SJean Pihet */ 273f7dfe3d8SJean Pihet ldr r1, kernel_flush 274dd313947SDave Martin blx r1 275dd313947SDave Martin /* 276dd313947SDave Martin * The kernel doesn't interwork: v7_flush_dcache_all in particluar will 277dd313947SDave Martin * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. 278dd313947SDave Martin * This sequence switches back to ARM. Note that .align may insert a 279dd313947SDave Martin * nop: bx pc needs to be word-aligned in order to work. 280dd313947SDave Martin */ 281dd313947SDave Martin THUMB( .thumb ) 282dd313947SDave Martin THUMB( .align ) 283dd313947SDave Martin THUMB( bx pc ) 284dd313947SDave Martin THUMB( nop ) 285dd313947SDave Martin .arm 286f7dfe3d8SJean Pihet 287f7dfe3d8SJean Pihetomap3_do_wfi: 2888bd22949SKevin Hilman ldr r4, sdrc_power @ read the SDRC_POWER register 2898bd22949SKevin Hilman ldr r5, [r4] @ read the contents of SDRC_POWER 2908bd22949SKevin Hilman orr r5, r5, #0x40 @ enable self refresh on idle req 2918bd22949SKevin Hilman str r5, [r4] @ write back to SDRC_POWER register 2928bd22949SKevin Hilman 2938bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 2944444d712SSantosh Shilimkar dsb 2954444d712SSantosh Shilimkar dmb 2968bd22949SKevin Hilman 297f7dfe3d8SJean Pihet/* 298f7dfe3d8SJean Pihet * =================================== 299f7dfe3d8SJean Pihet * == WFI instruction => Enter idle == 300f7dfe3d8SJean Pihet * =================================== 301f7dfe3d8SJean Pihet */ 3028bd22949SKevin Hilman wfi @ wait for interrupt 3038bd22949SKevin Hilman 304f7dfe3d8SJean Pihet/* 305f7dfe3d8SJean Pihet * =================================== 306f7dfe3d8SJean Pihet * == Resume path for non-OFF modes == 307f7dfe3d8SJean Pihet * =================================== 308f7dfe3d8SJean Pihet */ 3098bd22949SKevin Hilman nop 3108bd22949SKevin Hilman nop 3118bd22949SKevin Hilman nop 3128bd22949SKevin Hilman nop 3138bd22949SKevin Hilman nop 3148bd22949SKevin Hilman nop 3158bd22949SKevin Hilman nop 3168bd22949SKevin Hilman nop 3178bd22949SKevin Hilman nop 3188bd22949SKevin Hilman nop 31989139dceSPeter 'p2' De Schrijver bl wait_sdrc_ok 3208bd22949SKevin Hilman 32190625110SSantosh Shilimkar mrc p15, 0, r0, c1, c0, 0 32290625110SSantosh Shilimkar tst r0, #(1 << 2) @ Check C bit enabled? 32390625110SSantosh Shilimkar orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared 32490625110SSantosh Shilimkar mcreq p15, 0, r0, c1, c0, 0 32590625110SSantosh Shilimkar isb 32690625110SSantosh Shilimkar 327f7dfe3d8SJean Pihet/* 328f7dfe3d8SJean Pihet * =================================== 329f7dfe3d8SJean Pihet * == Exit point from non-OFF modes == 330f7dfe3d8SJean Pihet * =================================== 331f7dfe3d8SJean Pihet */ 332857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} @ restore regs and return 333f7dfe3d8SJean Pihet 334f7dfe3d8SJean Pihet 335f7dfe3d8SJean Pihet/* 336f7dfe3d8SJean Pihet * ============================== 337f7dfe3d8SJean Pihet * == Resume path for OFF mode == 338f7dfe3d8SJean Pihet * ============================== 339f7dfe3d8SJean Pihet */ 340f7dfe3d8SJean Pihet 341f7dfe3d8SJean Pihet/* 342f7dfe3d8SJean Pihet * The restore_* functions are called by the ROM code 343f7dfe3d8SJean Pihet * when back from WFI in OFF mode. 344f7dfe3d8SJean Pihet * Cf. the get_*restore_pointer functions. 345f7dfe3d8SJean Pihet * 346f7dfe3d8SJean Pihet * restore_es3: applies to 34xx >= ES3.0 347f7dfe3d8SJean Pihet * restore_3630: applies to 36xx 348f7dfe3d8SJean Pihet * restore: common code for 3xxx 349f7dfe3d8SJean Pihet */ 3500795a75aSTero Kristorestore_es3: 3510795a75aSTero Kristo ldr r5, pm_prepwstst_core_p 3520795a75aSTero Kristo ldr r4, [r5] 3530795a75aSTero Kristo and r4, r4, #0x3 3540795a75aSTero Kristo cmp r4, #0x0 @ Check if previous power state of CORE is OFF 3550795a75aSTero Kristo bne restore 3560795a75aSTero Kristo adr r0, es3_sdrc_fix 3570795a75aSTero Kristo ldr r1, sram_base 3580795a75aSTero Kristo ldr r2, es3_sdrc_fix_sz 3590795a75aSTero Kristo mov r2, r2, ror #2 3600795a75aSTero Kristocopy_to_sram: 3610795a75aSTero Kristo ldmia r0!, {r3} @ val = *src 3620795a75aSTero Kristo stmia r1!, {r3} @ *dst = val 3630795a75aSTero Kristo subs r2, r2, #0x1 @ num_words-- 3640795a75aSTero Kristo bne copy_to_sram 3650795a75aSTero Kristo ldr r1, sram_base 3660795a75aSTero Kristo blx r1 367458e999eSNishanth Menon b restore 368458e999eSNishanth Menon 369458e999eSNishanth Menonrestore_3630: 370458e999eSNishanth Menon ldr r1, pm_prepwstst_core_p 371458e999eSNishanth Menon ldr r2, [r1] 372458e999eSNishanth Menon and r2, r2, #0x3 373458e999eSNishanth Menon cmp r2, #0x0 @ Check if previous power state of CORE is OFF 374458e999eSNishanth Menon bne restore 375458e999eSNishanth Menon /* Disable RTA before giving control */ 376458e999eSNishanth Menon ldr r1, control_mem_rta 377458e999eSNishanth Menon mov r2, #OMAP36XX_RTA_DISABLE 378458e999eSNishanth Menon str r2, [r1] 379f7dfe3d8SJean Pihet 380f7dfe3d8SJean Pihet /* Fall through to common code for the remaining logic */ 381f7dfe3d8SJean Pihet 3828bd22949SKevin Hilmanrestore: 383f7dfe3d8SJean Pihet /* 384f7dfe3d8SJean Pihet * Check what was the reason for mpu reset and store the reason in r9: 385f7dfe3d8SJean Pihet * 0 - No context lost 386f7dfe3d8SJean Pihet * 1 - Only L1 and logic lost 387f7dfe3d8SJean Pihet * 2 - Only L2 lost - In this case, we wont be here 388f7dfe3d8SJean Pihet * 3 - Both L1 and L2 lost 389f7dfe3d8SJean Pihet */ 3908bd22949SKevin Hilman ldr r1, pm_pwstctrl_mpu 3918bd22949SKevin Hilman ldr r2, [r1] 3928bd22949SKevin Hilman and r2, r2, #0x3 3938bd22949SKevin Hilman cmp r2, #0x0 @ Check if target power state was OFF or RET 3948bd22949SKevin Hilman moveq r9, #0x3 @ MPU OFF => L1 and L2 lost 3958bd22949SKevin Hilman movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation 3968bd22949SKevin Hilman bne logic_l1_restore 397c4236d2eSPeter 'p2' De Schrijver 398c4236d2eSPeter 'p2' De Schrijver ldr r0, l2dis_3630 399c4236d2eSPeter 'p2' De Schrijver cmp r0, #0x1 @ should we disable L2 on 3630? 400c4236d2eSPeter 'p2' De Schrijver bne skipl2dis 401c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r0, c1, c0, 1 402c4236d2eSPeter 'p2' De Schrijver bic r0, r0, #2 @ disable L2 cache 403c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r0, c1, c0, 1 404c4236d2eSPeter 'p2' De Schrijverskipl2dis: 40527d59a4aSTero Kristo ldr r0, control_stat 40627d59a4aSTero Kristo ldr r1, [r0] 40727d59a4aSTero Kristo and r1, #0x700 40827d59a4aSTero Kristo cmp r1, #0x300 40927d59a4aSTero Kristo beq l2_inv_gp 41027d59a4aSTero Kristo mov r0, #40 @ set service ID for PPA 41127d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 41227d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 41327d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 41427d59a4aSTero Kristo mov r6, #0xff 41527d59a4aSTero Kristo adr r3, l2_inv_api_params @ r3 points to dummy parameters 4164444d712SSantosh Shilimkar dsb @ data write barrier 4174444d712SSantosh Shilimkar dmb @ data memory barrier 41876d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 41927d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 42027d59a4aSTero Kristo mov r0, #42 @ set service ID for PPA 42127d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 42227d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 42327d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 42427d59a4aSTero Kristo mov r6, #0xff 425a087cad9STero Kristo ldr r4, scratchpad_base 426a087cad9STero Kristo ldr r3, [r4, #0xBC] @ r3 points to parameters 4274444d712SSantosh Shilimkar dsb @ data write barrier 4284444d712SSantosh Shilimkar dmb @ data memory barrier 42976d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 43027d59a4aSTero Kristo 43179dcfdd4STero Kristo#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 43279dcfdd4STero Kristo /* Restore L2 aux control register */ 43379dcfdd4STero Kristo @ set service ID for PPA 43479dcfdd4STero Kristo mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 43579dcfdd4STero Kristo mov r12, r0 @ copy service ID in r12 43679dcfdd4STero Kristo mov r1, #0 @ set task ID for ROM code in r1 43779dcfdd4STero Kristo mov r2, #4 @ set some flags in r2, r6 43879dcfdd4STero Kristo mov r6, #0xff 43979dcfdd4STero Kristo ldr r4, scratchpad_base 44079dcfdd4STero Kristo ldr r3, [r4, #0xBC] 44179dcfdd4STero Kristo adds r3, r3, #8 @ r3 points to parameters 4424444d712SSantosh Shilimkar dsb @ data write barrier 4434444d712SSantosh Shilimkar dmb @ data memory barrier 44476d50018SDave Martin smc #1 @ call SMI monitor (smi #1) 44579dcfdd4STero Kristo#endif 44627d59a4aSTero Kristo b logic_l1_restore 447bb1c9034SJean Pihet 448dd313947SDave Martin .align 44927d59a4aSTero Kristol2_inv_api_params: 45027d59a4aSTero Kristo .word 0x1, 0x00 45127d59a4aSTero Kristol2_inv_gp: 4528bd22949SKevin Hilman /* Execute smi to invalidate L2 cache */ 453bb1c9034SJean Pihet mov r12, #0x1 @ set up to invalidate L2 45476d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 45527d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 456a087cad9STero Kristo ldr r4, scratchpad_base 457a087cad9STero Kristo ldr r3, [r4,#0xBC] 458a087cad9STero Kristo ldr r0, [r3,#4] 45927d59a4aSTero Kristo mov r12, #0x3 46076d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 46179dcfdd4STero Kristo ldr r4, scratchpad_base 46279dcfdd4STero Kristo ldr r3, [r4,#0xBC] 46379dcfdd4STero Kristo ldr r0, [r3,#12] 46479dcfdd4STero Kristo mov r12, #0x2 46576d50018SDave Martin smc #0 @ Call SMI monitor (smieq) 4668bd22949SKevin Hilmanlogic_l1_restore: 467c4236d2eSPeter 'p2' De Schrijver ldr r1, l2dis_3630 468bb1c9034SJean Pihet cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 469c4236d2eSPeter 'p2' De Schrijver bne skipl2reen 470c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r1, c1, c0, 1 471c4236d2eSPeter 'p2' De Schrijver orr r1, r1, #2 @ re-enable L2 cache 472c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r1, c1, c0, 1 473c4236d2eSPeter 'p2' De Schrijverskipl2reen: 4748bd22949SKevin Hilman mov r1, #0 475bb1c9034SJean Pihet /* 476bb1c9034SJean Pihet * Invalidate all instruction caches to PoU 477bb1c9034SJean Pihet * and flush branch target cache 478bb1c9034SJean Pihet */ 4798bd22949SKevin Hilman mcr p15, 0, r1, c7, c5, 0 4808bd22949SKevin Hilman 4818bd22949SKevin Hilman ldr r4, scratchpad_base 4828bd22949SKevin Hilman ldr r3, [r4,#0xBC] 48379dcfdd4STero Kristo adds r3, r3, #16 48446f557cbSSantosh Shilimkar 4858bd22949SKevin Hilman ldmia r3!, {r4-r6} 48646f557cbSSantosh Shilimkar mov sp, r4 @ Restore sp 48746f557cbSSantosh Shilimkar msr spsr_cxsf, r5 @ Restore spsr 48846f557cbSSantosh Shilimkar mov lr, r6 @ Restore lr 4898bd22949SKevin Hilman 4908bd22949SKevin Hilman ldmia r3!, {r4-r7} 49146f557cbSSantosh Shilimkar mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register 49246f557cbSSantosh Shilimkar mcr p15, 0, r5, c2, c0, 0 @ TTBR0 49346f557cbSSantosh Shilimkar mcr p15, 0, r6, c2, c0, 1 @ TTBR1 49446f557cbSSantosh Shilimkar mcr p15, 0, r7, c2, c0, 2 @ TTBCR 4958bd22949SKevin Hilman 49646f557cbSSantosh Shilimkar ldmia r3!,{r4-r6} 49746f557cbSSantosh Shilimkar mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register 49846f557cbSSantosh Shilimkar mcr p15, 0, r5, c10, c2, 0 @ PRRR 49946f557cbSSantosh Shilimkar mcr p15, 0, r6, c10, c2, 1 @ NMRR 5008bd22949SKevin Hilman 5018bd22949SKevin Hilman 50246f557cbSSantosh Shilimkar ldmia r3!,{r4-r7} 50346f557cbSSantosh Shilimkar mcr p15, 0, r4, c13, c0, 1 @ Context ID 50446f557cbSSantosh Shilimkar mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID 50546f557cbSSantosh Shilimkar mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address 50646f557cbSSantosh Shilimkar msr cpsr, r7 @ store cpsr 5078bd22949SKevin Hilman 5088bd22949SKevin Hilman /* Enabling MMU here */ 509bb1c9034SJean Pihet mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl 5108bd22949SKevin Hilman /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */ 5118bd22949SKevin Hilman and r7, #0x7 5128bd22949SKevin Hilman cmp r7, #0x0 5138bd22949SKevin Hilman beq usettbr0 5148bd22949SKevin Hilmanttbr_error: 515bb1c9034SJean Pihet /* 516bb1c9034SJean Pihet * More work needs to be done to support N[0:2] value other than 0 5178bd22949SKevin Hilman * So looping here so that the error can be detected 5188bd22949SKevin Hilman */ 5198bd22949SKevin Hilman b ttbr_error 5208bd22949SKevin Hilmanusettbr0: 5218bd22949SKevin Hilman mrc p15, 0, r2, c2, c0, 0 5228bd22949SKevin Hilman ldr r5, ttbrbit_mask 5238bd22949SKevin Hilman and r2, r5 5248bd22949SKevin Hilman mov r4, pc 5258bd22949SKevin Hilman ldr r5, table_index_mask 526bb1c9034SJean Pihet and r4, r5 @ r4 = 31 to 20 bits of pc 5278bd22949SKevin Hilman /* Extract the value to be written to table entry */ 5288bd22949SKevin Hilman ldr r1, table_entry 529bb1c9034SJean Pihet /* r1 has the value to be written to table entry*/ 530bb1c9034SJean Pihet add r1, r1, r4 5318bd22949SKevin Hilman /* Getting the address of table entry to modify */ 5328bd22949SKevin Hilman lsr r4, #18 533bb1c9034SJean Pihet /* r2 has the location which needs to be modified */ 534bb1c9034SJean Pihet add r2, r4 5358bd22949SKevin Hilman /* Storing previous entry of location being modified */ 5368bd22949SKevin Hilman ldr r5, scratchpad_base 5378bd22949SKevin Hilman ldr r4, [r2] 5388bd22949SKevin Hilman str r4, [r5, #0xC0] 5398bd22949SKevin Hilman /* Modify the table entry */ 5408bd22949SKevin Hilman str r1, [r2] 541bb1c9034SJean Pihet /* 542bb1c9034SJean Pihet * Storing address of entry being modified 543bb1c9034SJean Pihet * - will be restored after enabling MMU 544bb1c9034SJean Pihet */ 5458bd22949SKevin Hilman ldr r5, scratchpad_base 5468bd22949SKevin Hilman str r2, [r5, #0xC4] 5478bd22949SKevin Hilman 5488bd22949SKevin Hilman mov r0, #0 5498bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer 5508bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array 5518bd22949SKevin Hilman mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB 5528bd22949SKevin Hilman mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB 553bb1c9034SJean Pihet /* 554bb1c9034SJean Pihet * Restore control register. This enables the MMU. 555bb1c9034SJean Pihet * The caches and prediction are not enabled here, they 556bb1c9034SJean Pihet * will be enabled after restoring the MMU table entry. 557bb1c9034SJean Pihet */ 5588bd22949SKevin Hilman ldmia r3!, {r4} 5598bd22949SKevin Hilman /* Store previous value of control register in scratchpad */ 5608bd22949SKevin Hilman str r4, [r5, #0xC8] 5618bd22949SKevin Hilman ldr r2, cache_pred_disable_mask 5628bd22949SKevin Hilman and r4, r2 5638bd22949SKevin Hilman mcr p15, 0, r4, c1, c0, 0 5648409d57bSSantosh Shilimkar dsb 5658409d57bSSantosh Shilimkar isb 5668409d57bSSantosh Shilimkar ldr r0, =restoremmu_on 5678409d57bSSantosh Shilimkar bx r0 5688bd22949SKevin Hilman 5690bd40535SRichard Woodruff/* 570f7dfe3d8SJean Pihet * ============================== 571f7dfe3d8SJean Pihet * == Exit point from OFF mode == 572f7dfe3d8SJean Pihet * ============================== 5730bd40535SRichard Woodruff */ 5748409d57bSSantosh Shilimkarrestoremmu_on: 575857c1b81SRussell King ldmfd sp!, {r4 - r11, pc} @ restore regs and return 5768bd22949SKevin Hilman 5771e81bc01SJean Pihet 5781e81bc01SJean Pihet/* 5791e81bc01SJean Pihet * Internal functions 5801e81bc01SJean Pihet */ 5811e81bc01SJean Pihet 58283521291SJean Pihet/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */ 5831e81bc01SJean Pihet .text 584dd313947SDave Martin .align 3 5851e81bc01SJean PihetENTRY(es3_sdrc_fix) 5861e81bc01SJean Pihet ldr r4, sdrc_syscfg @ get config addr 5871e81bc01SJean Pihet ldr r5, [r4] @ get value 5881e81bc01SJean Pihet tst r5, #0x100 @ is part access blocked 5891e81bc01SJean Pihet it eq 5901e81bc01SJean Pihet biceq r5, r5, #0x100 @ clear bit if set 5911e81bc01SJean Pihet str r5, [r4] @ write back change 5921e81bc01SJean Pihet ldr r4, sdrc_mr_0 @ get config addr 5931e81bc01SJean Pihet ldr r5, [r4] @ get value 5941e81bc01SJean Pihet str r5, [r4] @ write back change 5951e81bc01SJean Pihet ldr r4, sdrc_emr2_0 @ get config addr 5961e81bc01SJean Pihet ldr r5, [r4] @ get value 5971e81bc01SJean Pihet str r5, [r4] @ write back change 5981e81bc01SJean Pihet ldr r4, sdrc_manual_0 @ get config addr 5991e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 6001e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 6011e81bc01SJean Pihet ldr r4, sdrc_mr_1 @ get config addr 6021e81bc01SJean Pihet ldr r5, [r4] @ get value 6031e81bc01SJean Pihet str r5, [r4] @ write back change 6041e81bc01SJean Pihet ldr r4, sdrc_emr2_1 @ get config addr 6051e81bc01SJean Pihet ldr r5, [r4] @ get value 6061e81bc01SJean Pihet str r5, [r4] @ write back change 6071e81bc01SJean Pihet ldr r4, sdrc_manual_1 @ get config addr 6081e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 6091e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 6101e81bc01SJean Pihet bx lr 6111e81bc01SJean Pihet 612dd313947SDave Martin .align 6131e81bc01SJean Pihetsdrc_syscfg: 6141e81bc01SJean Pihet .word SDRC_SYSCONFIG_P 6151e81bc01SJean Pihetsdrc_mr_0: 6161e81bc01SJean Pihet .word SDRC_MR_0_P 6171e81bc01SJean Pihetsdrc_emr2_0: 6181e81bc01SJean Pihet .word SDRC_EMR2_0_P 6191e81bc01SJean Pihetsdrc_manual_0: 6201e81bc01SJean Pihet .word SDRC_MANUAL_0_P 6211e81bc01SJean Pihetsdrc_mr_1: 6221e81bc01SJean Pihet .word SDRC_MR_1_P 6231e81bc01SJean Pihetsdrc_emr2_1: 6241e81bc01SJean Pihet .word SDRC_EMR2_1_P 6251e81bc01SJean Pihetsdrc_manual_1: 6261e81bc01SJean Pihet .word SDRC_MANUAL_1_P 627dd313947SDave MartinENDPROC(es3_sdrc_fix) 6281e81bc01SJean PihetENTRY(es3_sdrc_fix_sz) 6291e81bc01SJean Pihet .word . - es3_sdrc_fix 6301e81bc01SJean Pihet 63183521291SJean Pihet/* 63283521291SJean Pihet * This function implements the erratum ID i581 WA: 63383521291SJean Pihet * SDRC state restore before accessing the SDRAM 63483521291SJean Pihet * 63583521291SJean Pihet * Only used at return from non-OFF mode. For OFF 63683521291SJean Pihet * mode the ROM code configures the SDRC and 63783521291SJean Pihet * the DPLL before calling the restore code directly 63883521291SJean Pihet * from DDR. 63983521291SJean Pihet */ 64083521291SJean Pihet 64189139dceSPeter 'p2' De Schrijver/* Make sure SDRC accesses are ok */ 64289139dceSPeter 'p2' De Schrijverwait_sdrc_ok: 6439d93b8a2SPeter 'p2' De Schrijver 644bb1c9034SJean Pihet/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */ 6459d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest_ckgen 6469d93b8a2SPeter 'p2' De Schrijverwait_dpll3_lock: 64789139dceSPeter 'p2' De Schrijver ldr r5, [r4] 6489d93b8a2SPeter 'p2' De Schrijver tst r5, #1 6499d93b8a2SPeter 'p2' De Schrijver beq wait_dpll3_lock 6509d93b8a2SPeter 'p2' De Schrijver 6519d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest1_core 6529d93b8a2SPeter 'p2' De Schrijverwait_sdrc_ready: 6539d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 6549d93b8a2SPeter 'p2' De Schrijver tst r5, #0x2 6559d93b8a2SPeter 'p2' De Schrijver bne wait_sdrc_ready 6569d93b8a2SPeter 'p2' De Schrijver /* allow DLL powerdown upon hw idle req */ 6578bd22949SKevin Hilman ldr r4, sdrc_power 6588bd22949SKevin Hilman ldr r5, [r4] 6598bd22949SKevin Hilman bic r5, r5, #0x40 6608bd22949SKevin Hilman str r5, [r4] 6619d93b8a2SPeter 'p2' De Schrijver 662dd313947SDave Martin/* 663dd313947SDave Martin * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a 664dd313947SDave Martin * base instead. 665dd313947SDave Martin * Be careful not to clobber r7 when maintaing this code. 666dd313947SDave Martin */ 667dd313947SDave Martin 668bb1c9034SJean Pihetis_dll_in_lock_mode: 66989139dceSPeter 'p2' De Schrijver /* Is dll in lock mode? */ 67089139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 67189139dceSPeter 'p2' De Schrijver ldr r5, [r4] 67289139dceSPeter 'p2' De Schrijver tst r5, #0x4 673bb1c9034SJean Pihet bxne lr @ Return if locked 67489139dceSPeter 'p2' De Schrijver /* wait till dll locks */ 675dd313947SDave Martin adr r7, kick_counter 6769d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_timed: 6779d93b8a2SPeter 'p2' De Schrijver ldr r4, wait_dll_lock_counter 6789d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 679dd313947SDave Martin str r4, [r7, #wait_dll_lock_counter - kick_counter] 68089139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_status 681bb1c9034SJean Pihet /* Wait 20uS for lock */ 682bb1c9034SJean Pihet mov r6, #8 6839d93b8a2SPeter 'p2' De Schrijverwait_dll_lock: 6849d93b8a2SPeter 'p2' De Schrijver subs r6, r6, #0x1 6859d93b8a2SPeter 'p2' De Schrijver beq kick_dll 68689139dceSPeter 'p2' De Schrijver ldr r5, [r4] 68789139dceSPeter 'p2' De Schrijver and r5, r5, #0x4 68889139dceSPeter 'p2' De Schrijver cmp r5, #0x4 68989139dceSPeter 'p2' De Schrijver bne wait_dll_lock 690bb1c9034SJean Pihet bx lr @ Return when locked 69189139dceSPeter 'p2' De Schrijver 6929d93b8a2SPeter 'p2' De Schrijver /* disable/reenable DLL if not locked */ 6939d93b8a2SPeter 'p2' De Schrijverkick_dll: 6949d93b8a2SPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 6959d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 6969d93b8a2SPeter 'p2' De Schrijver mov r6, r5 697bb1c9034SJean Pihet bic r6, #(1<<3) @ disable dll 6989d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 6999d93b8a2SPeter 'p2' De Schrijver dsb 700bb1c9034SJean Pihet orr r6, r6, #(1<<3) @ enable dll 7019d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 7029d93b8a2SPeter 'p2' De Schrijver dsb 7039d93b8a2SPeter 'p2' De Schrijver ldr r4, kick_counter 7049d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 705dd313947SDave Martin str r4, [r7] @ kick_counter 7069d93b8a2SPeter 'p2' De Schrijver b wait_dll_lock_timed 7079d93b8a2SPeter 'p2' De Schrijver 708dd313947SDave Martin .align 70989139dceSPeter 'p2' De Schrijvercm_idlest1_core: 71089139dceSPeter 'p2' De Schrijver .word CM_IDLEST1_CORE_V 7119d93b8a2SPeter 'p2' De Schrijvercm_idlest_ckgen: 7129d93b8a2SPeter 'p2' De Schrijver .word CM_IDLEST_CKGEN_V 71389139dceSPeter 'p2' De Schrijversdrc_dlla_status: 71489139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_STATUS_V 71589139dceSPeter 'p2' De Schrijversdrc_dlla_ctrl: 71689139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_CTRL_V 7170795a75aSTero Kristopm_prepwstst_core_p: 7180795a75aSTero Kristo .word PM_PREPWSTST_CORE_P 7198bd22949SKevin Hilmanpm_pwstctrl_mpu: 7208bd22949SKevin Hilman .word PM_PWSTCTRL_MPU_P 7218bd22949SKevin Hilmanscratchpad_base: 7228bd22949SKevin Hilman .word SCRATCHPAD_BASE_P 7230795a75aSTero Kristosram_base: 7240795a75aSTero Kristo .word SRAM_BASE_P + 0x8000 7258bd22949SKevin Hilmansdrc_power: 7268bd22949SKevin Hilman .word SDRC_POWER_V 7278bd22949SKevin Hilmanttbrbit_mask: 7288bd22949SKevin Hilman .word 0xFFFFC000 7298bd22949SKevin Hilmantable_index_mask: 7308bd22949SKevin Hilman .word 0xFFF00000 7318bd22949SKevin Hilmantable_entry: 7328bd22949SKevin Hilman .word 0x00000C02 7338bd22949SKevin Hilmancache_pred_disable_mask: 7348bd22949SKevin Hilman .word 0xFFFFE7FB 73527d59a4aSTero Kristocontrol_stat: 73627d59a4aSTero Kristo .word CONTROL_STAT 737458e999eSNishanth Menoncontrol_mem_rta: 738458e999eSNishanth Menon .word CONTROL_MEM_RTA_CTRL 7390bd40535SRichard Woodruffkernel_flush: 7400bd40535SRichard Woodruff .word v7_flush_dcache_all 741c4236d2eSPeter 'p2' De Schrijverl2dis_3630: 742c4236d2eSPeter 'p2' De Schrijver .word 0 7439d93b8a2SPeter 'p2' De Schrijver /* 7449d93b8a2SPeter 'p2' De Schrijver * When exporting to userspace while the counters are in SRAM, 7459d93b8a2SPeter 'p2' De Schrijver * these 2 words need to be at the end to facilitate retrival! 7469d93b8a2SPeter 'p2' De Schrijver */ 7479d93b8a2SPeter 'p2' De Schrijverkick_counter: 7489d93b8a2SPeter 'p2' De Schrijver .word 0 7499d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_counter: 7509d93b8a2SPeter 'p2' De Schrijver .word 0 751dd313947SDave MartinENDPROC(omap34xx_cpu_suspend) 752f7dfe3d8SJean Pihet 7538bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend_sz) 7548bd22949SKevin Hilman .word . - omap34xx_cpu_suspend 755