18bd22949SKevin Hilman/* 28bd22949SKevin Hilman * linux/arch/arm/mach-omap2/sleep.S 38bd22949SKevin Hilman * 48bd22949SKevin Hilman * (C) Copyright 2007 58bd22949SKevin Hilman * Texas Instruments 68bd22949SKevin Hilman * Karthik Dasu <karthik-dp@ti.com> 78bd22949SKevin Hilman * 88bd22949SKevin Hilman * (C) Copyright 2004 98bd22949SKevin Hilman * Texas Instruments, <www.ti.com> 108bd22949SKevin Hilman * Richard Woodruff <r-woodruff2@ti.com> 118bd22949SKevin Hilman * 128bd22949SKevin Hilman * This program is free software; you can redistribute it and/or 138bd22949SKevin Hilman * modify it under the terms of the GNU General Public License as 148bd22949SKevin Hilman * published by the Free Software Foundation; either version 2 of 158bd22949SKevin Hilman * the License, or (at your option) any later version. 168bd22949SKevin Hilman * 178bd22949SKevin Hilman * This program is distributed in the hope that it will be useful, 188bd22949SKevin Hilman * but WITHOUT ANY WARRANTY; without even the implied warranty of 198bd22949SKevin Hilman * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 208bd22949SKevin Hilman * GNU General Public License for more details. 218bd22949SKevin Hilman * 228bd22949SKevin Hilman * You should have received a copy of the GNU General Public License 238bd22949SKevin Hilman * along with this program; if not, write to the Free Software 248bd22949SKevin Hilman * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 258bd22949SKevin Hilman * MA 02111-1307 USA 268bd22949SKevin Hilman */ 278bd22949SKevin Hilman#include <linux/linkage.h> 288bd22949SKevin Hilman#include <asm/assembler.h> 29b4b36fd9SJean Pihet#include <plat/sram.h> 308bd22949SKevin Hilman#include <mach/io.h> 318bd22949SKevin Hilman 3289139dceSPeter 'p2' De Schrijver#include "cm.h" 338bd22949SKevin Hilman#include "prm.h" 348bd22949SKevin Hilman#include "sdrc.h" 354814ced5SPaul Walmsley#include "control.h" 368bd22949SKevin Hilman 37fe360e1cSJean Pihet/* 38fe360e1cSJean Pihet * Registers access definitions 39fe360e1cSJean Pihet */ 40fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_OFFS 0xc 41fe360e1cSJean Pihet#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ 42fe360e1cSJean Pihet (SDRC_SCRATCHPAD_SEM_OFFS) 43fe360e1cSJean Pihet#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ 44fe360e1cSJean Pihet OMAP3430_PM_PREPWSTST 4537903009SAbhijit Pagare#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL 4689139dceSPeter 'p2' De Schrijver#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) 479d93b8a2SPeter 'p2' De Schrijver#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) 48fe360e1cSJean Pihet#define SRAM_BASE_P OMAP3_SRAM_PA 49fe360e1cSJean Pihet#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS 50fe360e1cSJean Pihet#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ 51fe360e1cSJean Pihet OMAP36XX_CONTROL_MEM_RTA_CTRL) 52fe360e1cSJean Pihet 53fe360e1cSJean Pihet/* Move this as correct place is available */ 54fe360e1cSJean Pihet#define SCRATCHPAD_MEM_OFFS 0x310 55fe360e1cSJean Pihet#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ 56fe360e1cSJean Pihet OMAP343X_CONTROL_MEM_WKUP +\ 57fe360e1cSJean Pihet SCRATCHPAD_MEM_OFFS) 588bd22949SKevin Hilman#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 590795a75aSTero Kristo#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) 600795a75aSTero Kristo#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) 610795a75aSTero Kristo#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0) 620795a75aSTero Kristo#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0) 630795a75aSTero Kristo#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) 640795a75aSTero Kristo#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) 650795a75aSTero Kristo#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) 6689139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 6789139dceSPeter 'p2' De Schrijver#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 688bd22949SKevin Hilman 69a89b6f00SRajendra Nayak 70d3cdfd2aSJean Pihet/* 71d3cdfd2aSJean Pihet * API functions 72d3cdfd2aSJean Pihet */ 73a89b6f00SRajendra Nayak 74a89b6f00SRajendra Nayak .text 758bd22949SKevin Hilman/* Function call to get the restore pointer for resume from OFF */ 768bd22949SKevin HilmanENTRY(get_restore_pointer) 778bd22949SKevin Hilman stmfd sp!, {lr} @ save registers on stack 788bd22949SKevin Hilman adr r0, restore 798bd22949SKevin Hilman ldmfd sp!, {pc} @ restore regs and return 808bd22949SKevin HilmanENTRY(get_restore_pointer_sz) 810795a75aSTero Kristo .word . - get_restore_pointer 821e81bc01SJean Pihet 83458e999eSNishanth Menon .text 84458e999eSNishanth Menon/* Function call to get the restore pointer for 3630 resume from OFF */ 85458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer) 86458e999eSNishanth Menon stmfd sp!, {lr} @ save registers on stack 87458e999eSNishanth Menon adr r0, restore_3630 88458e999eSNishanth Menon ldmfd sp!, {pc} @ restore regs and return 89458e999eSNishanth MenonENTRY(get_omap3630_restore_pointer_sz) 90458e999eSNishanth Menon .word . - get_omap3630_restore_pointer 910795a75aSTero Kristo 920795a75aSTero Kristo .text 931e81bc01SJean Pihet/* Function call to get the restore pointer for ES3 to resume from OFF */ 941e81bc01SJean PihetENTRY(get_es3_restore_pointer) 951e81bc01SJean Pihet stmfd sp!, {lr} @ save registers on stack 961e81bc01SJean Pihet adr r0, restore_es3 971e81bc01SJean Pihet ldmfd sp!, {pc} @ restore regs and return 981e81bc01SJean PihetENTRY(get_es3_restore_pointer_sz) 991e81bc01SJean Pihet .word . - get_es3_restore_pointer 1001e81bc01SJean Pihet 1011e81bc01SJean Pihet .text 102c4236d2eSPeter 'p2' De Schrijver/* 103c4236d2eSPeter 'p2' De Schrijver * L2 cache needs to be toggled for stable OFF mode functionality on 3630. 1041e81bc01SJean Pihet * This function sets up a flag that will allow for this toggling to take 105c4236d2eSPeter 'p2' De Schrijver * place on 3630. Hopefully some version in the future maynot need this 106c4236d2eSPeter 'p2' De Schrijver */ 107c4236d2eSPeter 'p2' De SchrijverENTRY(enable_omap3630_toggle_l2_on_restore) 108c4236d2eSPeter 'p2' De Schrijver stmfd sp!, {lr} @ save registers on stack 109c4236d2eSPeter 'p2' De Schrijver /* Setup so that we will disable and enable l2 */ 110c4236d2eSPeter 'p2' De Schrijver mov r1, #0x1 111c4236d2eSPeter 'p2' De Schrijver str r1, l2dis_3630 112c4236d2eSPeter 'p2' De Schrijver ldmfd sp!, {pc} @ restore regs and return 113c4236d2eSPeter 'p2' De Schrijver 11427d59a4aSTero Kristo/* Function to call rom code to save secure ram context */ 11527d59a4aSTero KristoENTRY(save_secure_ram_context) 11627d59a4aSTero Kristo stmfd sp!, {r1-r12, lr} @ save registers on stack 117d3cdfd2aSJean Pihet 11827d59a4aSTero Kristo adr r3, api_params @ r3 points to parameters 11927d59a4aSTero Kristo str r0, [r3,#0x4] @ r0 has sdram address 12027d59a4aSTero Kristo ldr r12, high_mask 12127d59a4aSTero Kristo and r3, r3, r12 12227d59a4aSTero Kristo ldr r12, sram_phy_addr_mask 12327d59a4aSTero Kristo orr r3, r3, r12 12427d59a4aSTero Kristo mov r0, #25 @ set service ID for PPA 12527d59a4aSTero Kristo mov r12, r0 @ copy secure service ID in r12 12627d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 127ba50ea7eSKalle Jokiniemi mov r2, #4 @ set some flags in r2, r6 12827d59a4aSTero Kristo mov r6, #0xff 12927d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 13027d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 13127d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 13227d59a4aSTero Kristo nop 13327d59a4aSTero Kristo nop 13427d59a4aSTero Kristo nop 13527d59a4aSTero Kristo nop 13627d59a4aSTero Kristo ldmfd sp!, {r1-r12, pc} 13727d59a4aSTero Kristosram_phy_addr_mask: 13827d59a4aSTero Kristo .word SRAM_BASE_P 13927d59a4aSTero Kristohigh_mask: 14027d59a4aSTero Kristo .word 0xffff 14127d59a4aSTero Kristoapi_params: 14227d59a4aSTero Kristo .word 0x4, 0x0, 0x0, 0x1, 0x1 14327d59a4aSTero KristoENTRY(save_secure_ram_context_sz) 14427d59a4aSTero Kristo .word . - save_secure_ram_context 14527d59a4aSTero Kristo 1468bd22949SKevin Hilman/* 1478bd22949SKevin Hilman * Forces OMAP into idle state 1488bd22949SKevin Hilman * 1498bd22949SKevin Hilman * omap34xx_suspend() - This bit of code just executes the WFI 1508bd22949SKevin Hilman * for normal idles. 1518bd22949SKevin Hilman * 1528bd22949SKevin Hilman * Note: This code get's copied to internal SRAM at boot. When the OMAP 1538bd22949SKevin Hilman * wakes up it continues execution at the point it went to sleep. 1548bd22949SKevin Hilman */ 1558bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend) 1568bd22949SKevin Hilman stmfd sp!, {r0-r12, lr} @ save registers on stack 157d3cdfd2aSJean Pihet 1588bd22949SKevin Hilman /* r0 contains restore pointer in sdram */ 1598bd22949SKevin Hilman /* r1 contains information about saving context */ 1608bd22949SKevin Hilman ldr r4, sdrc_power @ read the SDRC_POWER register 1618bd22949SKevin Hilman ldr r5, [r4] @ read the contents of SDRC_POWER 1628bd22949SKevin Hilman orr r5, r5, #0x40 @ enable self refresh on idle req 1638bd22949SKevin Hilman str r5, [r4] @ write back to SDRC_POWER register 1648bd22949SKevin Hilman 1658bd22949SKevin Hilman cmp r1, #0x0 1668bd22949SKevin Hilman /* If context save is required, do that and execute wfi */ 1678bd22949SKevin Hilman bne save_context_wfi 1688bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 1698bd22949SKevin Hilman mov r1, #0 1708bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 4 1718bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 5 1728bd22949SKevin Hilman 1738bd22949SKevin Hilman wfi @ wait for interrupt 1748bd22949SKevin Hilman 1758bd22949SKevin Hilman nop 1768bd22949SKevin Hilman nop 1778bd22949SKevin Hilman nop 1788bd22949SKevin Hilman nop 1798bd22949SKevin Hilman nop 1808bd22949SKevin Hilman nop 1818bd22949SKevin Hilman nop 1828bd22949SKevin Hilman nop 1838bd22949SKevin Hilman nop 1848bd22949SKevin Hilman nop 18589139dceSPeter 'p2' De Schrijver bl wait_sdrc_ok 1868bd22949SKevin Hilman 1878bd22949SKevin Hilman ldmfd sp!, {r0-r12, pc} @ restore regs and return 1880795a75aSTero Kristorestore_es3: 1890795a75aSTero Kristo ldr r5, pm_prepwstst_core_p 1900795a75aSTero Kristo ldr r4, [r5] 1910795a75aSTero Kristo and r4, r4, #0x3 1920795a75aSTero Kristo cmp r4, #0x0 @ Check if previous power state of CORE is OFF 1930795a75aSTero Kristo bne restore 1940795a75aSTero Kristo adr r0, es3_sdrc_fix 1950795a75aSTero Kristo ldr r1, sram_base 1960795a75aSTero Kristo ldr r2, es3_sdrc_fix_sz 1970795a75aSTero Kristo mov r2, r2, ror #2 1980795a75aSTero Kristocopy_to_sram: 1990795a75aSTero Kristo ldmia r0!, {r3} @ val = *src 2000795a75aSTero Kristo stmia r1!, {r3} @ *dst = val 2010795a75aSTero Kristo subs r2, r2, #0x1 @ num_words-- 2020795a75aSTero Kristo bne copy_to_sram 2030795a75aSTero Kristo ldr r1, sram_base 2040795a75aSTero Kristo blx r1 205458e999eSNishanth Menon b restore 206458e999eSNishanth Menon 207458e999eSNishanth Menonrestore_3630: 208458e999eSNishanth Menon ldr r1, pm_prepwstst_core_p 209458e999eSNishanth Menon ldr r2, [r1] 210458e999eSNishanth Menon and r2, r2, #0x3 211458e999eSNishanth Menon cmp r2, #0x0 @ Check if previous power state of CORE is OFF 212458e999eSNishanth Menon bne restore 213458e999eSNishanth Menon /* Disable RTA before giving control */ 214458e999eSNishanth Menon ldr r1, control_mem_rta 215458e999eSNishanth Menon mov r2, #OMAP36XX_RTA_DISABLE 216458e999eSNishanth Menon str r2, [r1] 217458e999eSNishanth Menon /* Fall thru for the remaining logic */ 2188bd22949SKevin Hilmanrestore: 2198bd22949SKevin Hilman /* Check what was the reason for mpu reset and store the reason in r9*/ 2208bd22949SKevin Hilman /* 1 - Only L1 and logic lost */ 2218bd22949SKevin Hilman /* 2 - Only L2 lost - In this case, we wont be here */ 2228bd22949SKevin Hilman /* 3 - Both L1 and L2 lost */ 2238bd22949SKevin Hilman ldr r1, pm_pwstctrl_mpu 2248bd22949SKevin Hilman ldr r2, [r1] 2258bd22949SKevin Hilman and r2, r2, #0x3 2268bd22949SKevin Hilman cmp r2, #0x0 @ Check if target power state was OFF or RET 2278bd22949SKevin Hilman moveq r9, #0x3 @ MPU OFF => L1 and L2 lost 2288bd22949SKevin Hilman movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation 2298bd22949SKevin Hilman bne logic_l1_restore 230c4236d2eSPeter 'p2' De Schrijver 231c4236d2eSPeter 'p2' De Schrijver ldr r0, l2dis_3630 232c4236d2eSPeter 'p2' De Schrijver cmp r0, #0x1 @ should we disable L2 on 3630? 233c4236d2eSPeter 'p2' De Schrijver bne skipl2dis 234c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r0, c1, c0, 1 235c4236d2eSPeter 'p2' De Schrijver bic r0, r0, #2 @ disable L2 cache 236c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r0, c1, c0, 1 237c4236d2eSPeter 'p2' De Schrijverskipl2dis: 23827d59a4aSTero Kristo ldr r0, control_stat 23927d59a4aSTero Kristo ldr r1, [r0] 24027d59a4aSTero Kristo and r1, #0x700 24127d59a4aSTero Kristo cmp r1, #0x300 24227d59a4aSTero Kristo beq l2_inv_gp 24327d59a4aSTero Kristo mov r0, #40 @ set service ID for PPA 24427d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 24527d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 24627d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 24727d59a4aSTero Kristo mov r6, #0xff 24827d59a4aSTero Kristo adr r3, l2_inv_api_params @ r3 points to dummy parameters 24927d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 25027d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 25127d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 25227d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 25327d59a4aSTero Kristo mov r0, #42 @ set service ID for PPA 25427d59a4aSTero Kristo mov r12, r0 @ copy secure Service ID in r12 25527d59a4aSTero Kristo mov r1, #0 @ set task id for ROM code in r1 25627d59a4aSTero Kristo mov r2, #4 @ set some flags in r2, r6 25727d59a4aSTero Kristo mov r6, #0xff 258a087cad9STero Kristo ldr r4, scratchpad_base 259a087cad9STero Kristo ldr r3, [r4, #0xBC] @ r3 points to parameters 26027d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 26127d59a4aSTero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 26227d59a4aSTero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 26327d59a4aSTero Kristo 26479dcfdd4STero Kristo#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 26579dcfdd4STero Kristo /* Restore L2 aux control register */ 26679dcfdd4STero Kristo @ set service ID for PPA 26779dcfdd4STero Kristo mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID 26879dcfdd4STero Kristo mov r12, r0 @ copy service ID in r12 26979dcfdd4STero Kristo mov r1, #0 @ set task ID for ROM code in r1 27079dcfdd4STero Kristo mov r2, #4 @ set some flags in r2, r6 27179dcfdd4STero Kristo mov r6, #0xff 27279dcfdd4STero Kristo ldr r4, scratchpad_base 27379dcfdd4STero Kristo ldr r3, [r4, #0xBC] 27479dcfdd4STero Kristo adds r3, r3, #8 @ r3 points to parameters 27579dcfdd4STero Kristo mcr p15, 0, r0, c7, c10, 4 @ data write barrier 27679dcfdd4STero Kristo mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 27779dcfdd4STero Kristo .word 0xE1600071 @ call SMI monitor (smi #1) 27879dcfdd4STero Kristo#endif 27927d59a4aSTero Kristo b logic_l1_restore 28027d59a4aSTero Kristol2_inv_api_params: 28127d59a4aSTero Kristo .word 0x1, 0x00 28227d59a4aSTero Kristol2_inv_gp: 2838bd22949SKevin Hilman /* Execute smi to invalidate L2 cache */ 2848bd22949SKevin Hilman mov r12, #0x1 @ set up to invalide L2 2858bd22949SKevin Hilmansmi: .word 0xE1600070 @ Call SMI monitor (smieq) 28627d59a4aSTero Kristo /* Write to Aux control register to set some bits */ 287a087cad9STero Kristo ldr r4, scratchpad_base 288a087cad9STero Kristo ldr r3, [r4,#0xBC] 289a087cad9STero Kristo ldr r0, [r3,#4] 29027d59a4aSTero Kristo mov r12, #0x3 29127d59a4aSTero Kristo .word 0xE1600070 @ Call SMI monitor (smieq) 29279dcfdd4STero Kristo ldr r4, scratchpad_base 29379dcfdd4STero Kristo ldr r3, [r4,#0xBC] 29479dcfdd4STero Kristo ldr r0, [r3,#12] 29579dcfdd4STero Kristo mov r12, #0x2 29679dcfdd4STero Kristo .word 0xE1600070 @ Call SMI monitor (smieq) 2978bd22949SKevin Hilmanlogic_l1_restore: 298c4236d2eSPeter 'p2' De Schrijver ldr r1, l2dis_3630 299c4236d2eSPeter 'p2' De Schrijver cmp r1, #0x1 @ Do we need to re-enable L2 on 3630? 300c4236d2eSPeter 'p2' De Schrijver bne skipl2reen 301c4236d2eSPeter 'p2' De Schrijver mrc p15, 0, r1, c1, c0, 1 302c4236d2eSPeter 'p2' De Schrijver orr r1, r1, #2 @ re-enable L2 cache 303c4236d2eSPeter 'p2' De Schrijver mcr p15, 0, r1, c1, c0, 1 304c4236d2eSPeter 'p2' De Schrijverskipl2reen: 3058bd22949SKevin Hilman mov r1, #0 3068bd22949SKevin Hilman /* Invalidate all instruction caches to PoU 3078bd22949SKevin Hilman * and flush branch target cache */ 3088bd22949SKevin Hilman mcr p15, 0, r1, c7, c5, 0 3098bd22949SKevin Hilman 3108bd22949SKevin Hilman ldr r4, scratchpad_base 3118bd22949SKevin Hilman ldr r3, [r4,#0xBC] 31279dcfdd4STero Kristo adds r3, r3, #16 3138bd22949SKevin Hilman ldmia r3!, {r4-r6} 3148bd22949SKevin Hilman mov sp, r4 3158bd22949SKevin Hilman msr spsr_cxsf, r5 3168bd22949SKevin Hilman mov lr, r6 3178bd22949SKevin Hilman 3188bd22949SKevin Hilman ldmia r3!, {r4-r9} 3198bd22949SKevin Hilman /* Coprocessor access Control Register */ 3208bd22949SKevin Hilman mcr p15, 0, r4, c1, c0, 2 3218bd22949SKevin Hilman 3228bd22949SKevin Hilman /* TTBR0 */ 3238bd22949SKevin Hilman MCR p15, 0, r5, c2, c0, 0 3248bd22949SKevin Hilman /* TTBR1 */ 3258bd22949SKevin Hilman MCR p15, 0, r6, c2, c0, 1 3268bd22949SKevin Hilman /* Translation table base control register */ 3278bd22949SKevin Hilman MCR p15, 0, r7, c2, c0, 2 3288bd22949SKevin Hilman /*domain access Control Register */ 3298bd22949SKevin Hilman MCR p15, 0, r8, c3, c0, 0 3308bd22949SKevin Hilman /* data fault status Register */ 3318bd22949SKevin Hilman MCR p15, 0, r9, c5, c0, 0 3328bd22949SKevin Hilman 3338bd22949SKevin Hilman ldmia r3!,{r4-r8} 3348bd22949SKevin Hilman /* instruction fault status Register */ 3358bd22949SKevin Hilman MCR p15, 0, r4, c5, c0, 1 3368bd22949SKevin Hilman /*Data Auxiliary Fault Status Register */ 3378bd22949SKevin Hilman MCR p15, 0, r5, c5, c1, 0 3388bd22949SKevin Hilman /*Instruction Auxiliary Fault Status Register*/ 3398bd22949SKevin Hilman MCR p15, 0, r6, c5, c1, 1 3408bd22949SKevin Hilman /*Data Fault Address Register */ 3418bd22949SKevin Hilman MCR p15, 0, r7, c6, c0, 0 3428bd22949SKevin Hilman /*Instruction Fault Address Register*/ 3438bd22949SKevin Hilman MCR p15, 0, r8, c6, c0, 2 3448bd22949SKevin Hilman ldmia r3!,{r4-r7} 3458bd22949SKevin Hilman 3468bd22949SKevin Hilman /* user r/w thread and process ID */ 3478bd22949SKevin Hilman MCR p15, 0, r4, c13, c0, 2 3488bd22949SKevin Hilman /* user ro thread and process ID */ 3498bd22949SKevin Hilman MCR p15, 0, r5, c13, c0, 3 3508bd22949SKevin Hilman /*Privileged only thread and process ID */ 3518bd22949SKevin Hilman MCR p15, 0, r6, c13, c0, 4 3528bd22949SKevin Hilman /* cache size selection */ 3538bd22949SKevin Hilman MCR p15, 2, r7, c0, c0, 0 3548bd22949SKevin Hilman ldmia r3!,{r4-r8} 3558bd22949SKevin Hilman /* Data TLB lockdown registers */ 3568bd22949SKevin Hilman MCR p15, 0, r4, c10, c0, 0 3578bd22949SKevin Hilman /* Instruction TLB lockdown registers */ 3588bd22949SKevin Hilman MCR p15, 0, r5, c10, c0, 1 3598bd22949SKevin Hilman /* Secure or Nonsecure Vector Base Address */ 3608bd22949SKevin Hilman MCR p15, 0, r6, c12, c0, 0 3618bd22949SKevin Hilman /* FCSE PID */ 3628bd22949SKevin Hilman MCR p15, 0, r7, c13, c0, 0 3638bd22949SKevin Hilman /* Context PID */ 3648bd22949SKevin Hilman MCR p15, 0, r8, c13, c0, 1 3658bd22949SKevin Hilman 3668bd22949SKevin Hilman ldmia r3!,{r4-r5} 3678bd22949SKevin Hilman /* primary memory remap register */ 3688bd22949SKevin Hilman MCR p15, 0, r4, c10, c2, 0 3698bd22949SKevin Hilman /*normal memory remap register */ 3708bd22949SKevin Hilman MCR p15, 0, r5, c10, c2, 1 3718bd22949SKevin Hilman 3728bd22949SKevin Hilman /* Restore cpsr */ 3738bd22949SKevin Hilman ldmia r3!,{r4} /*load CPSR from SDRAM*/ 3748bd22949SKevin Hilman msr cpsr, r4 /*store cpsr */ 3758bd22949SKevin Hilman 3768bd22949SKevin Hilman /* Enabling MMU here */ 3778bd22949SKevin Hilman mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */ 3788bd22949SKevin Hilman /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/ 3798bd22949SKevin Hilman and r7, #0x7 3808bd22949SKevin Hilman cmp r7, #0x0 3818bd22949SKevin Hilman beq usettbr0 3828bd22949SKevin Hilmanttbr_error: 3838bd22949SKevin Hilman /* More work needs to be done to support N[0:2] value other than 0 3848bd22949SKevin Hilman * So looping here so that the error can be detected 3858bd22949SKevin Hilman */ 3868bd22949SKevin Hilman b ttbr_error 3878bd22949SKevin Hilmanusettbr0: 3888bd22949SKevin Hilman mrc p15, 0, r2, c2, c0, 0 3898bd22949SKevin Hilman ldr r5, ttbrbit_mask 3908bd22949SKevin Hilman and r2, r5 3918bd22949SKevin Hilman mov r4, pc 3928bd22949SKevin Hilman ldr r5, table_index_mask 3938bd22949SKevin Hilman and r4, r5 /* r4 = 31 to 20 bits of pc */ 3948bd22949SKevin Hilman /* Extract the value to be written to table entry */ 3958bd22949SKevin Hilman ldr r1, table_entry 3968bd22949SKevin Hilman add r1, r1, r4 /* r1 has value to be written to table entry*/ 3978bd22949SKevin Hilman /* Getting the address of table entry to modify */ 3988bd22949SKevin Hilman lsr r4, #18 3998bd22949SKevin Hilman add r2, r4 /* r2 has the location which needs to be modified */ 4008bd22949SKevin Hilman /* Storing previous entry of location being modified */ 4018bd22949SKevin Hilman ldr r5, scratchpad_base 4028bd22949SKevin Hilman ldr r4, [r2] 4038bd22949SKevin Hilman str r4, [r5, #0xC0] 4048bd22949SKevin Hilman /* Modify the table entry */ 4058bd22949SKevin Hilman str r1, [r2] 4068bd22949SKevin Hilman /* Storing address of entry being modified 4078bd22949SKevin Hilman * - will be restored after enabling MMU */ 4088bd22949SKevin Hilman ldr r5, scratchpad_base 4098bd22949SKevin Hilman str r2, [r5, #0xC4] 4108bd22949SKevin Hilman 4118bd22949SKevin Hilman mov r0, #0 4128bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer 4138bd22949SKevin Hilman mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array 4148bd22949SKevin Hilman mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB 4158bd22949SKevin Hilman mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB 4168bd22949SKevin Hilman /* Restore control register but dont enable caches here*/ 4178bd22949SKevin Hilman /* Caches will be enabled after restoring MMU table entry */ 4188bd22949SKevin Hilman ldmia r3!, {r4} 4198bd22949SKevin Hilman /* Store previous value of control register in scratchpad */ 4208bd22949SKevin Hilman str r4, [r5, #0xC8] 4218bd22949SKevin Hilman ldr r2, cache_pred_disable_mask 4228bd22949SKevin Hilman and r4, r2 4238bd22949SKevin Hilman mcr p15, 0, r4, c1, c0, 0 4248bd22949SKevin Hilman 4258bd22949SKevin Hilman ldmfd sp!, {r0-r12, pc} @ restore regs and return 4268bd22949SKevin Hilmansave_context_wfi: 4278bd22949SKevin Hilman mov r8, r0 /* Store SDRAM address in r8 */ 428a087cad9STero Kristo mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register 429a087cad9STero Kristo mov r4, #0x1 @ Number of parameters for restore call 43079dcfdd4STero Kristo stmia r8!, {r4-r5} @ Push parameters for restore call 43179dcfdd4STero Kristo mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register 43279dcfdd4STero Kristo stmia r8!, {r4-r5} @ Push parameters for restore call 4338bd22949SKevin Hilman /* Check what that target sleep state is:stored in r1*/ 4348bd22949SKevin Hilman /* 1 - Only L1 and logic lost */ 4358bd22949SKevin Hilman /* 2 - Only L2 lost */ 4368bd22949SKevin Hilman /* 3 - Both L1 and L2 lost */ 4378bd22949SKevin Hilman cmp r1, #0x2 /* Only L2 lost */ 4388bd22949SKevin Hilman beq clean_l2 4398bd22949SKevin Hilman cmp r1, #0x1 /* L2 retained */ 4408bd22949SKevin Hilman /* r9 stores whether to clean L2 or not*/ 4418bd22949SKevin Hilman moveq r9, #0x0 /* Dont Clean L2 */ 4428bd22949SKevin Hilman movne r9, #0x1 /* Clean L2 */ 4438bd22949SKevin Hilmanl1_logic_lost: 4448bd22949SKevin Hilman /* Store sp and spsr to SDRAM */ 4458bd22949SKevin Hilman mov r4, sp 4468bd22949SKevin Hilman mrs r5, spsr 4478bd22949SKevin Hilman mov r6, lr 4488bd22949SKevin Hilman stmia r8!, {r4-r6} 4498bd22949SKevin Hilman /* Save all ARM registers */ 4508bd22949SKevin Hilman /* Coprocessor access control register */ 4518bd22949SKevin Hilman mrc p15, 0, r6, c1, c0, 2 4528bd22949SKevin Hilman stmia r8!, {r6} 4538bd22949SKevin Hilman /* TTBR0, TTBR1 and Translation table base control */ 4548bd22949SKevin Hilman mrc p15, 0, r4, c2, c0, 0 4558bd22949SKevin Hilman mrc p15, 0, r5, c2, c0, 1 4568bd22949SKevin Hilman mrc p15, 0, r6, c2, c0, 2 4578bd22949SKevin Hilman stmia r8!, {r4-r6} 4588bd22949SKevin Hilman /* Domain access control register, data fault status register, 4598bd22949SKevin Hilman and instruction fault status register */ 4608bd22949SKevin Hilman mrc p15, 0, r4, c3, c0, 0 4618bd22949SKevin Hilman mrc p15, 0, r5, c5, c0, 0 4628bd22949SKevin Hilman mrc p15, 0, r6, c5, c0, 1 4638bd22949SKevin Hilman stmia r8!, {r4-r6} 4648bd22949SKevin Hilman /* Data aux fault status register, instruction aux fault status, 4658bd22949SKevin Hilman datat fault address register and instruction fault address register*/ 4668bd22949SKevin Hilman mrc p15, 0, r4, c5, c1, 0 4678bd22949SKevin Hilman mrc p15, 0, r5, c5, c1, 1 4688bd22949SKevin Hilman mrc p15, 0, r6, c6, c0, 0 4698bd22949SKevin Hilman mrc p15, 0, r7, c6, c0, 2 4708bd22949SKevin Hilman stmia r8!, {r4-r7} 4718bd22949SKevin Hilman /* user r/w thread and process ID, user r/o thread and process ID, 4728bd22949SKevin Hilman priv only thread and process ID, cache size selection */ 4738bd22949SKevin Hilman mrc p15, 0, r4, c13, c0, 2 4748bd22949SKevin Hilman mrc p15, 0, r5, c13, c0, 3 4758bd22949SKevin Hilman mrc p15, 0, r6, c13, c0, 4 4768bd22949SKevin Hilman mrc p15, 2, r7, c0, c0, 0 4778bd22949SKevin Hilman stmia r8!, {r4-r7} 4788bd22949SKevin Hilman /* Data TLB lockdown, instruction TLB lockdown registers */ 4798bd22949SKevin Hilman mrc p15, 0, r5, c10, c0, 0 4808bd22949SKevin Hilman mrc p15, 0, r6, c10, c0, 1 4818bd22949SKevin Hilman stmia r8!, {r5-r6} 4828bd22949SKevin Hilman /* Secure or non secure vector base address, FCSE PID, Context PID*/ 4838bd22949SKevin Hilman mrc p15, 0, r4, c12, c0, 0 4848bd22949SKevin Hilman mrc p15, 0, r5, c13, c0, 0 4858bd22949SKevin Hilman mrc p15, 0, r6, c13, c0, 1 4868bd22949SKevin Hilman stmia r8!, {r4-r6} 4878bd22949SKevin Hilman /* Primary remap, normal remap registers */ 4888bd22949SKevin Hilman mrc p15, 0, r4, c10, c2, 0 4898bd22949SKevin Hilman mrc p15, 0, r5, c10, c2, 1 4908bd22949SKevin Hilman stmia r8!,{r4-r5} 4918bd22949SKevin Hilman 4928bd22949SKevin Hilman /* Store current cpsr*/ 4938bd22949SKevin Hilman mrs r2, cpsr 4948bd22949SKevin Hilman stmia r8!, {r2} 4958bd22949SKevin Hilman 4968bd22949SKevin Hilman mrc p15, 0, r4, c1, c0, 0 4978bd22949SKevin Hilman /* save control register */ 4988bd22949SKevin Hilman stmia r8!, {r4} 4998bd22949SKevin Hilmanclean_caches: 5008bd22949SKevin Hilman /* Clean Data or unified cache to POU*/ 5018bd22949SKevin Hilman /* How to invalidate only L1 cache???? - #FIX_ME# */ 5028bd22949SKevin Hilman /* mcr p15, 0, r11, c7, c11, 1 */ 5038bd22949SKevin Hilman cmp r9, #1 /* Check whether L2 inval is required or not*/ 5048bd22949SKevin Hilman bne skip_l2_inval 5058bd22949SKevin Hilmanclean_l2: 5060bd40535SRichard Woodruff /* 5070bd40535SRichard Woodruff * Jump out to kernel flush routine 5080bd40535SRichard Woodruff * - reuse that code is better 5090bd40535SRichard Woodruff * - it executes in a cached space so is faster than refetch per-block 5100bd40535SRichard Woodruff * - should be faster and will change with kernel 5110bd40535SRichard Woodruff * - 'might' have to copy address, load and jump to it 5120bd40535SRichard Woodruff * - lr is used since we are running in SRAM currently. 5130bd40535SRichard Woodruff */ 5140bd40535SRichard Woodruff ldr r1, kernel_flush 5150bd40535SRichard Woodruff mov lr, pc 5160bd40535SRichard Woodruff bx r1 5170bd40535SRichard Woodruff 5188bd22949SKevin Hilmanskip_l2_inval: 5198bd22949SKevin Hilman /* Data memory barrier and Data sync barrier */ 5208bd22949SKevin Hilman mov r1, #0 5218bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 4 5228bd22949SKevin Hilman mcr p15, 0, r1, c7, c10, 5 5238bd22949SKevin Hilman 5248bd22949SKevin Hilman wfi @ wait for interrupt 5258bd22949SKevin Hilman nop 5268bd22949SKevin Hilman nop 5278bd22949SKevin Hilman nop 5288bd22949SKevin Hilman nop 5298bd22949SKevin Hilman nop 5308bd22949SKevin Hilman nop 5318bd22949SKevin Hilman nop 5328bd22949SKevin Hilman nop 5338bd22949SKevin Hilman nop 5348bd22949SKevin Hilman nop 53589139dceSPeter 'p2' De Schrijver bl wait_sdrc_ok 5368bd22949SKevin Hilman /* restore regs and return */ 5378bd22949SKevin Hilman ldmfd sp!, {r0-r12, pc} 5388bd22949SKevin Hilman 5391e81bc01SJean Pihet 5401e81bc01SJean Pihet/* 5411e81bc01SJean Pihet * Internal functions 5421e81bc01SJean Pihet */ 5431e81bc01SJean Pihet 5441e81bc01SJean Pihet .text 5451e81bc01SJean PihetENTRY(es3_sdrc_fix) 5461e81bc01SJean Pihet ldr r4, sdrc_syscfg @ get config addr 5471e81bc01SJean Pihet ldr r5, [r4] @ get value 5481e81bc01SJean Pihet tst r5, #0x100 @ is part access blocked 5491e81bc01SJean Pihet it eq 5501e81bc01SJean Pihet biceq r5, r5, #0x100 @ clear bit if set 5511e81bc01SJean Pihet str r5, [r4] @ write back change 5521e81bc01SJean Pihet ldr r4, sdrc_mr_0 @ get config addr 5531e81bc01SJean Pihet ldr r5, [r4] @ get value 5541e81bc01SJean Pihet str r5, [r4] @ write back change 5551e81bc01SJean Pihet ldr r4, sdrc_emr2_0 @ get config addr 5561e81bc01SJean Pihet ldr r5, [r4] @ get value 5571e81bc01SJean Pihet str r5, [r4] @ write back change 5581e81bc01SJean Pihet ldr r4, sdrc_manual_0 @ get config addr 5591e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 5601e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 5611e81bc01SJean Pihet ldr r4, sdrc_mr_1 @ get config addr 5621e81bc01SJean Pihet ldr r5, [r4] @ get value 5631e81bc01SJean Pihet str r5, [r4] @ write back change 5641e81bc01SJean Pihet ldr r4, sdrc_emr2_1 @ get config addr 5651e81bc01SJean Pihet ldr r5, [r4] @ get value 5661e81bc01SJean Pihet str r5, [r4] @ write back change 5671e81bc01SJean Pihet ldr r4, sdrc_manual_1 @ get config addr 5681e81bc01SJean Pihet mov r5, #0x2 @ autorefresh command 5691e81bc01SJean Pihet str r5, [r4] @ kick off refreshes 5701e81bc01SJean Pihet bx lr 5711e81bc01SJean Pihet 5721e81bc01SJean Pihetsdrc_syscfg: 5731e81bc01SJean Pihet .word SDRC_SYSCONFIG_P 5741e81bc01SJean Pihetsdrc_mr_0: 5751e81bc01SJean Pihet .word SDRC_MR_0_P 5761e81bc01SJean Pihetsdrc_emr2_0: 5771e81bc01SJean Pihet .word SDRC_EMR2_0_P 5781e81bc01SJean Pihetsdrc_manual_0: 5791e81bc01SJean Pihet .word SDRC_MANUAL_0_P 5801e81bc01SJean Pihetsdrc_mr_1: 5811e81bc01SJean Pihet .word SDRC_MR_1_P 5821e81bc01SJean Pihetsdrc_emr2_1: 5831e81bc01SJean Pihet .word SDRC_EMR2_1_P 5841e81bc01SJean Pihetsdrc_manual_1: 5851e81bc01SJean Pihet .word SDRC_MANUAL_1_P 5861e81bc01SJean PihetENTRY(es3_sdrc_fix_sz) 5871e81bc01SJean Pihet .word . - es3_sdrc_fix 5881e81bc01SJean Pihet 58989139dceSPeter 'p2' De Schrijver/* Make sure SDRC accesses are ok */ 59089139dceSPeter 'p2' De Schrijverwait_sdrc_ok: 5919d93b8a2SPeter 'p2' De Schrijver 5929d93b8a2SPeter 'p2' De Schrijver/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */ 5939d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest_ckgen 5949d93b8a2SPeter 'p2' De Schrijverwait_dpll3_lock: 59589139dceSPeter 'p2' De Schrijver ldr r5, [r4] 5969d93b8a2SPeter 'p2' De Schrijver tst r5, #1 5979d93b8a2SPeter 'p2' De Schrijver beq wait_dpll3_lock 5989d93b8a2SPeter 'p2' De Schrijver 5999d93b8a2SPeter 'p2' De Schrijver ldr r4, cm_idlest1_core 6009d93b8a2SPeter 'p2' De Schrijverwait_sdrc_ready: 6019d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 6029d93b8a2SPeter 'p2' De Schrijver tst r5, #0x2 6039d93b8a2SPeter 'p2' De Schrijver bne wait_sdrc_ready 6049d93b8a2SPeter 'p2' De Schrijver /* allow DLL powerdown upon hw idle req */ 6058bd22949SKevin Hilman ldr r4, sdrc_power 6068bd22949SKevin Hilman ldr r5, [r4] 6078bd22949SKevin Hilman bic r5, r5, #0x40 6088bd22949SKevin Hilman str r5, [r4] 6099d93b8a2SPeter 'p2' De Schrijveris_dll_in_lock_mode: 6109d93b8a2SPeter 'p2' De Schrijver 61189139dceSPeter 'p2' De Schrijver /* Is dll in lock mode? */ 61289139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 61389139dceSPeter 'p2' De Schrijver ldr r5, [r4] 61489139dceSPeter 'p2' De Schrijver tst r5, #0x4 61589139dceSPeter 'p2' De Schrijver bxne lr 61689139dceSPeter 'p2' De Schrijver /* wait till dll locks */ 6179d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_timed: 6189d93b8a2SPeter 'p2' De Schrijver ldr r4, wait_dll_lock_counter 6199d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 6209d93b8a2SPeter 'p2' De Schrijver str r4, wait_dll_lock_counter 62189139dceSPeter 'p2' De Schrijver ldr r4, sdrc_dlla_status 6229d93b8a2SPeter 'p2' De Schrijver mov r6, #8 /* Wait 20uS for lock */ 6239d93b8a2SPeter 'p2' De Schrijverwait_dll_lock: 6249d93b8a2SPeter 'p2' De Schrijver subs r6, r6, #0x1 6259d93b8a2SPeter 'p2' De Schrijver beq kick_dll 62689139dceSPeter 'p2' De Schrijver ldr r5, [r4] 62789139dceSPeter 'p2' De Schrijver and r5, r5, #0x4 62889139dceSPeter 'p2' De Schrijver cmp r5, #0x4 62989139dceSPeter 'p2' De Schrijver bne wait_dll_lock 6308bd22949SKevin Hilman bx lr 63189139dceSPeter 'p2' De Schrijver 6329d93b8a2SPeter 'p2' De Schrijver /* disable/reenable DLL if not locked */ 6339d93b8a2SPeter 'p2' De Schrijverkick_dll: 6349d93b8a2SPeter 'p2' De Schrijver ldr r4, sdrc_dlla_ctrl 6359d93b8a2SPeter 'p2' De Schrijver ldr r5, [r4] 6369d93b8a2SPeter 'p2' De Schrijver mov r6, r5 6379d93b8a2SPeter 'p2' De Schrijver bic r6, #(1<<3) /* disable dll */ 6389d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 6399d93b8a2SPeter 'p2' De Schrijver dsb 6409d93b8a2SPeter 'p2' De Schrijver orr r6, r6, #(1<<3) /* enable dll */ 6419d93b8a2SPeter 'p2' De Schrijver str r6, [r4] 6429d93b8a2SPeter 'p2' De Schrijver dsb 6439d93b8a2SPeter 'p2' De Schrijver ldr r4, kick_counter 6449d93b8a2SPeter 'p2' De Schrijver add r4, r4, #1 6459d93b8a2SPeter 'p2' De Schrijver str r4, kick_counter 6469d93b8a2SPeter 'p2' De Schrijver b wait_dll_lock_timed 6479d93b8a2SPeter 'p2' De Schrijver 64889139dceSPeter 'p2' De Schrijvercm_idlest1_core: 64989139dceSPeter 'p2' De Schrijver .word CM_IDLEST1_CORE_V 6509d93b8a2SPeter 'p2' De Schrijvercm_idlest_ckgen: 6519d93b8a2SPeter 'p2' De Schrijver .word CM_IDLEST_CKGEN_V 65289139dceSPeter 'p2' De Schrijversdrc_dlla_status: 65389139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_STATUS_V 65489139dceSPeter 'p2' De Schrijversdrc_dlla_ctrl: 65589139dceSPeter 'p2' De Schrijver .word SDRC_DLLA_CTRL_V 6560795a75aSTero Kristopm_prepwstst_core_p: 6570795a75aSTero Kristo .word PM_PREPWSTST_CORE_P 6588bd22949SKevin Hilmanpm_pwstctrl_mpu: 6598bd22949SKevin Hilman .word PM_PWSTCTRL_MPU_P 6608bd22949SKevin Hilmanscratchpad_base: 6618bd22949SKevin Hilman .word SCRATCHPAD_BASE_P 6620795a75aSTero Kristosram_base: 6630795a75aSTero Kristo .word SRAM_BASE_P + 0x8000 6648bd22949SKevin Hilmansdrc_power: 6658bd22949SKevin Hilman .word SDRC_POWER_V 6668bd22949SKevin Hilmanttbrbit_mask: 6678bd22949SKevin Hilman .word 0xFFFFC000 6688bd22949SKevin Hilmantable_index_mask: 6698bd22949SKevin Hilman .word 0xFFF00000 6708bd22949SKevin Hilmantable_entry: 6718bd22949SKevin Hilman .word 0x00000C02 6728bd22949SKevin Hilmancache_pred_disable_mask: 6738bd22949SKevin Hilman .word 0xFFFFE7FB 67427d59a4aSTero Kristocontrol_stat: 67527d59a4aSTero Kristo .word CONTROL_STAT 676458e999eSNishanth Menoncontrol_mem_rta: 677458e999eSNishanth Menon .word CONTROL_MEM_RTA_CTRL 6780bd40535SRichard Woodruffkernel_flush: 6790bd40535SRichard Woodruff .word v7_flush_dcache_all 680c4236d2eSPeter 'p2' De Schrijverl2dis_3630: 681c4236d2eSPeter 'p2' De Schrijver .word 0 6829d93b8a2SPeter 'p2' De Schrijver /* 6839d93b8a2SPeter 'p2' De Schrijver * When exporting to userspace while the counters are in SRAM, 6849d93b8a2SPeter 'p2' De Schrijver * these 2 words need to be at the end to facilitate retrival! 6859d93b8a2SPeter 'p2' De Schrijver */ 6869d93b8a2SPeter 'p2' De Schrijverkick_counter: 6879d93b8a2SPeter 'p2' De Schrijver .word 0 6889d93b8a2SPeter 'p2' De Schrijverwait_dll_lock_counter: 6899d93b8a2SPeter 'p2' De Schrijver .word 0 6908bd22949SKevin HilmanENTRY(omap34xx_cpu_suspend_sz) 6918bd22949SKevin Hilman .word . - omap34xx_cpu_suspend 692