1/* 2 * linux/arch/arm/mach-omap2/sleep.S 3 * 4 * (C) Copyright 2004 5 * Texas Instruments, <www.ti.com> 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * 8 * (C) Copyright 2006 Nokia Corporation 9 * Fixed idle loop sleep 10 * Igor Stoppa <igor.stoppa@nokia.com> 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <linux/linkage.h> 29#include <asm/assembler.h> 30 31#include "omap24xx.h" 32#include "sdrc.h" 33 34/* First address of reserved address space? apparently valid for OMAP2 & 3 */ 35#define A_SDRC0_V (0xC0000000) 36 37 .text 38 39/* 40 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing 41 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore 42 * SDRC. 43 * 44 * Input: 45 * R0 : DLL ctrl value pre-Sleep 46 * R1 : SDRC_DLLA_CTRL 47 * R2 : SDRC_POWER 48 * 49 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on 50 * when we get called, but the DLL probably isn't. We will wait a bit more in 51 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even 52 * if in unlocked mode. 53 * 54 * For less than 242x-ES2.2 upon wake from a sleep mode where the external 55 * oscillator was stopped, a timing bug exists where a non-stabilized 12MHz 56 * clock can pass into the PRCM can cause problems at DSP and IVA. 57 * To work around this the code will switch to the 32kHz source prior to sleep. 58 * Post sleep we will shift back to using the DPLL. Apparently, 59 * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait 60 * 3x12MHz + 3x32kHz clocks for a full switch. 61 * 62 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored 63 * at wake 64 */ 65 .align 3 66ENTRY(omap24xx_cpu_suspend) 67 stmfd sp!, {r0 - r12, lr} @ save registers on stack 68 mov r3, #0x0 @ clear for mcr call 69 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 70 nop 71 nop 72 ldr r4, [r2] @ read SDRC_POWER 73 orr r4, r4, #0x40 @ enable self refresh on idle req 74 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) 75 str r4, [r2] @ make it so 76 nop 77 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt 78 nop 79loop: 80 subs r5, r5, #0x1 @ awake, wait just a bit 81 bne loop 82 83 /* The DPLL has to be on before we take the DDR out of self refresh */ 84 bic r4, r4, #0x40 @ now clear self refresh bit. 85 str r4, [r2] @ write to SDRC_POWER 86 ldr r4, A_SDRC0 @ make a clock happen 87 ldr r4, [r4] @ read A_SDRC0 88 nop @ start auto refresh only after clk ok 89 movs r0, r0 @ see if DDR or SDR 90 strne r0, [r1] @ rewrite DLLA to force DLL reload 91 addne r1, r1, #0x8 @ move to DLLB 92 strne r0, [r1] @ rewrite DLLB to force DLL reload 93 94 mov r5, #0x1000 95loop2: 96 subs r5, r5, #0x1 97 bne loop2 98 /* resume*/ 99 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 100 101A_SDRC0: 102 .word A_SDRC0_V 103 104ENTRY(omap24xx_cpu_suspend_sz) 105 .word . - omap24xx_cpu_suspend 106