1 /* 2 * linux/arch/arm/mach-omap2/sdrc2xxx.c 3 * 4 * SDRAM timing related functions for OMAP2xxx 5 * 6 * Copyright (C) 2005, 2008 Texas Instruments Inc. 7 * Copyright (C) 2005, 2008 Nokia Corporation 8 * 9 * Tony Lindgren <tony@atomide.com> 10 * Paul Walmsley 11 * Richard Woodruff <r-woodruff2@ti.com> 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/device.h> 21 #include <linux/list.h> 22 #include <linux/errno.h> 23 #include <linux/delay.h> 24 #include <linux/clk.h> 25 #include <linux/io.h> 26 27 #include "soc.h" 28 #include "iomap.h" 29 #include "common.h" 30 #include "prm2xxx.h" 31 #include "clock.h" 32 #include "sdrc.h" 33 #include "sram.h" 34 35 /* Memory timing, DLL mode flags */ 36 #define M_DDR 1 37 #define M_LOCK_CTRL (1 << 2) 38 #define M_UNLOCK 0 39 #define M_LOCK 1 40 41 42 static struct memory_timings mem_timings; 43 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; 44 45 static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void) 46 { 47 return mem_timings.slow_dll_ctrl; 48 } 49 50 static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void) 51 { 52 return mem_timings.fast_dll_ctrl; 53 } 54 55 static u32 omap2xxx_sdrc_get_type(void) 56 { 57 return mem_timings.m_type; 58 } 59 60 /* 61 * Check the DLL lock state, and return tue if running in unlock mode. 62 * This is needed to compensate for the shifted DLL value in unlock mode. 63 */ 64 u32 omap2xxx_sdrc_dll_is_unlocked(void) 65 { 66 /* dlla and dllb are a set */ 67 u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); 68 69 if ((dll_state & (1 << 2)) == (1 << 2)) 70 return 1; 71 else 72 return 0; 73 } 74 75 /* 76 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. 77 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or 78 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) 79 * 80 * Used by the clock framework during CORE DPLL changes 81 */ 82 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) 83 { 84 u32 dll_ctrl, m_type; 85 u32 prev = curr_perf_level; 86 unsigned long flags; 87 88 if ((curr_perf_level == level) && !force) 89 return prev; 90 91 if (level == CORE_CLK_SRC_DPLL) 92 dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl(); 93 else if (level == CORE_CLK_SRC_DPLL_X2) 94 dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl(); 95 else 96 return prev; 97 98 m_type = omap2xxx_sdrc_get_type(); 99 100 local_irq_save(flags); 101 /* 102 * XXX These calls should be abstracted out through a 103 * prm2xxx.c function 104 */ 105 if (cpu_is_omap2420()) 106 writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP); 107 else 108 writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP); 109 omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); 110 curr_perf_level = level; 111 local_irq_restore(flags); 112 113 return prev; 114 } 115 116 /* Used by the clock framework during CORE DPLL changes */ 117 void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode) 118 { 119 unsigned long dll_cnt; 120 u32 fast_dll = 0; 121 122 /* DDR = 1, SDR = 0 */ 123 mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); 124 125 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. 126 * In the case of 2422, its ok to use CS1 instead of CS0. 127 */ 128 if (cpu_is_omap2422()) 129 mem_timings.base_cs = 1; 130 else 131 mem_timings.base_cs = 0; 132 133 if (mem_timings.m_type != M_DDR) 134 return; 135 136 /* With DDR we need to determine the low frequency DLL value */ 137 if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL)) 138 mem_timings.dll_mode = M_UNLOCK; 139 else 140 mem_timings.dll_mode = M_LOCK; 141 142 if (mem_timings.base_cs == 0) { 143 fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL); 144 dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00; 145 } else { 146 fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL); 147 dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00; 148 } 149 if (force_lock_to_unlock_mode) { 150 fast_dll &= ~0xff00; 151 fast_dll |= dll_cnt; /* Current lock mode */ 152 } 153 /* set fast timings with DLL filter disabled */ 154 mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8)); 155 156 /* No disruptions, DDR will be offline & C-ABI not followed */ 157 omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl, 158 mem_timings.fast_dll_ctrl, 159 mem_timings.base_cs, 160 force_lock_to_unlock_mode); 161 mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */ 162 163 /* Turn status into unlock ctrl */ 164 mem_timings.slow_dll_ctrl |= 165 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2)); 166 167 /* 90 degree phase for anything below 133Mhz + disable DLL filter */ 168 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); 169 } 170