1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-omap2/sdrc2xxx.c 4 * 5 * SDRAM timing related functions for OMAP2xxx 6 * 7 * Copyright (C) 2005, 2008 Texas Instruments Inc. 8 * Copyright (C) 2005, 2008 Nokia Corporation 9 * 10 * Tony Lindgren <tony@atomide.com> 11 * Paul Walmsley 12 * Richard Woodruff <r-woodruff2@ti.com> 13 */ 14 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/device.h> 18 #include <linux/list.h> 19 #include <linux/errno.h> 20 #include <linux/delay.h> 21 #include <linux/clk.h> 22 #include <linux/io.h> 23 24 #include "soc.h" 25 #include "iomap.h" 26 #include "common.h" 27 #include "prm2xxx.h" 28 #include "clock.h" 29 #include "sdrc.h" 30 #include "sram.h" 31 32 /* Memory timing, DLL mode flags */ 33 #define M_DDR 1 34 #define M_LOCK_CTRL (1 << 2) 35 #define M_UNLOCK 0 36 #define M_LOCK 1 37 38 39 static struct memory_timings mem_timings; 40 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; 41 42 static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void) 43 { 44 return mem_timings.slow_dll_ctrl; 45 } 46 47 static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void) 48 { 49 return mem_timings.fast_dll_ctrl; 50 } 51 52 static u32 omap2xxx_sdrc_get_type(void) 53 { 54 return mem_timings.m_type; 55 } 56 57 /* 58 * Check the DLL lock state, and return tue if running in unlock mode. 59 * This is needed to compensate for the shifted DLL value in unlock mode. 60 */ 61 u32 omap2xxx_sdrc_dll_is_unlocked(void) 62 { 63 /* dlla and dllb are a set */ 64 u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); 65 66 if ((dll_state & (1 << 2)) == (1 << 2)) 67 return 1; 68 else 69 return 0; 70 } 71 72 /* 73 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. 74 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or 75 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) 76 * 77 * Used by the clock framework during CORE DPLL changes 78 */ 79 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) 80 { 81 u32 dll_ctrl, m_type; 82 u32 prev = curr_perf_level; 83 unsigned long flags; 84 85 if ((curr_perf_level == level) && !force) 86 return prev; 87 88 if (level == CORE_CLK_SRC_DPLL) 89 dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl(); 90 else if (level == CORE_CLK_SRC_DPLL_X2) 91 dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl(); 92 else 93 return prev; 94 95 m_type = omap2xxx_sdrc_get_type(); 96 97 local_irq_save(flags); 98 /* 99 * XXX These calls should be abstracted out through a 100 * prm2xxx.c function 101 */ 102 if (cpu_is_omap2420()) 103 writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP); 104 else 105 writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP); 106 omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); 107 curr_perf_level = level; 108 local_irq_restore(flags); 109 110 return prev; 111 } 112 113 /* Used by the clock framework during CORE DPLL changes */ 114 void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode) 115 { 116 unsigned long dll_cnt; 117 u32 fast_dll = 0; 118 119 /* DDR = 1, SDR = 0 */ 120 mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); 121 122 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. 123 * In the case of 2422, its ok to use CS1 instead of CS0. 124 */ 125 if (cpu_is_omap2422()) 126 mem_timings.base_cs = 1; 127 else 128 mem_timings.base_cs = 0; 129 130 if (mem_timings.m_type != M_DDR) 131 return; 132 133 /* With DDR we need to determine the low frequency DLL value */ 134 if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL)) 135 mem_timings.dll_mode = M_UNLOCK; 136 else 137 mem_timings.dll_mode = M_LOCK; 138 139 if (mem_timings.base_cs == 0) { 140 fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL); 141 dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00; 142 } else { 143 fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL); 144 dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00; 145 } 146 if (force_lock_to_unlock_mode) { 147 fast_dll &= ~0xff00; 148 fast_dll |= dll_cnt; /* Current lock mode */ 149 } 150 /* set fast timings with DLL filter disabled */ 151 mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8)); 152 153 /* No disruptions, DDR will be offline & C-ABI not followed */ 154 omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl, 155 mem_timings.fast_dll_ctrl, 156 mem_timings.base_cs, 157 force_lock_to_unlock_mode); 158 mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */ 159 160 /* Turn status into unlock ctrl */ 161 mem_timings.slow_dll_ctrl |= 162 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2)); 163 164 /* 90 degree phase for anything below 133MHz + disable DLL filter */ 165 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); 166 } 167