1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H 3 #define __ARCH_ARM_MACH_OMAP2_SDRC_H 4 5 /* 6 * OMAP2/3 SDRC/SMS macros and prototypes 7 * 8 * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc. 9 * Copyright (C) 2007-2008 Nokia Corporation 10 * 11 * Paul Walmsley 12 * Tony Lindgren 13 * Richard Woodruff 14 */ 15 #undef DEBUG 16 17 #ifndef __ASSEMBLER__ 18 19 #include <linux/io.h> 20 21 extern void __iomem *omap2_sdrc_base; 22 extern void __iomem *omap2_sms_base; 23 24 #define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg)) 25 #define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg)) 26 27 /* SDRC global register get/set */ 28 29 static inline void sdrc_write_reg(u32 val, u16 reg) 30 { 31 writel_relaxed(val, OMAP_SDRC_REGADDR(reg)); 32 } 33 34 static inline u32 sdrc_read_reg(u16 reg) 35 { 36 return readl_relaxed(OMAP_SDRC_REGADDR(reg)); 37 } 38 39 /* SMS global register get/set */ 40 41 static inline void sms_write_reg(u32 val, u16 reg) 42 { 43 writel_relaxed(val, OMAP_SMS_REGADDR(reg)); 44 } 45 46 static inline u32 sms_read_reg(u16 reg) 47 { 48 return readl_relaxed(OMAP_SMS_REGADDR(reg)); 49 } 50 51 extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms); 52 53 54 /** 55 * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate 56 * @rate: SDRC clock rate (in Hz) 57 * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate 58 * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate 59 * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate 60 * @mr: Value to program to SDRC_MR for this rate 61 * 62 * This structure holds a pre-computed set of register values for the 63 * SDRC for a given SDRC clock rate and SDRAM chip. These are 64 * intended to be pre-computed and specified in an array in the board-*.c 65 * files. The structure is keyed off the 'rate' field. 66 */ 67 struct omap_sdrc_params { 68 unsigned long rate; 69 u32 actim_ctrla; 70 u32 actim_ctrlb; 71 u32 rfr_ctrl; 72 u32 mr; 73 }; 74 75 #ifdef CONFIG_SOC_HAS_OMAP2_SDRC 76 void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 77 struct omap_sdrc_params *sdrc_cs1); 78 #else 79 static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 80 struct omap_sdrc_params *sdrc_cs1) {}; 81 #endif 82 83 int omap2_sdrc_get_params(unsigned long r, 84 struct omap_sdrc_params **sdrc_cs0, 85 struct omap_sdrc_params **sdrc_cs1); 86 void omap2_sms_save_context(void); 87 void omap2_sms_restore_context(void); 88 89 struct memory_timings { 90 u32 m_type; /* ddr = 1, sdr = 0 */ 91 u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ 92 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ 93 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ 94 u32 base_cs; /* base chip select to use for calculations */ 95 }; 96 97 extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); 98 struct omap_sdrc_params *rx51_get_sdram_timings(void); 99 100 u32 omap2xxx_sdrc_dll_is_unlocked(void); 101 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); 102 103 104 #else 105 #define OMAP242X_SDRC_REGADDR(reg) \ 106 OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) 107 #define OMAP243X_SDRC_REGADDR(reg) \ 108 OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) 109 #define OMAP34XX_SDRC_REGADDR(reg) \ 110 OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) 111 112 #endif /* __ASSEMBLER__ */ 113 114 /* Minimum frequency that the SDRC DLL can lock at */ 115 #define MIN_SDRC_DLL_LOCK_FREQ 83000000 116 117 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ 118 #define SDRC_MPURATE_SCALE 8 119 120 /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ 121 #define SDRC_MPURATE_BASE_SHIFT 9 122 123 /* 124 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at 125 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize 126 */ 127 #define SDRC_MPURATE_LOOPS 96 128 129 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ 130 131 #define SDRC_SYSCONFIG 0x010 132 #define SDRC_CS_CFG 0x040 133 #define SDRC_SHARING 0x044 134 #define SDRC_ERR_TYPE 0x04C 135 #define SDRC_DLLA_CTRL 0x060 136 #define SDRC_DLLA_STATUS 0x064 137 #define SDRC_DLLB_CTRL 0x068 138 #define SDRC_DLLB_STATUS 0x06C 139 #define SDRC_POWER 0x070 140 #define SDRC_MCFG_0 0x080 141 #define SDRC_MR_0 0x084 142 #define SDRC_EMR2_0 0x08c 143 #define SDRC_ACTIM_CTRL_A_0 0x09c 144 #define SDRC_ACTIM_CTRL_B_0 0x0a0 145 #define SDRC_RFR_CTRL_0 0x0a4 146 #define SDRC_MANUAL_0 0x0a8 147 #define SDRC_MCFG_1 0x0B0 148 #define SDRC_MR_1 0x0B4 149 #define SDRC_EMR2_1 0x0BC 150 #define SDRC_ACTIM_CTRL_A_1 0x0C4 151 #define SDRC_ACTIM_CTRL_B_1 0x0C8 152 #define SDRC_RFR_CTRL_1 0x0D4 153 #define SDRC_MANUAL_1 0x0D8 154 155 #define SDRC_POWER_AUTOCOUNT_SHIFT 8 156 #define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT) 157 #define SDRC_POWER_CLKCTRL_SHIFT 4 158 #define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT) 159 #define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT) 160 161 /* 162 * These values represent the number of memory clock cycles between 163 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 164 * rows per device, and include a subtraction of a 50 cycle window in the 165 * event that the autorefresh command is delayed due to other SDRC activity. 166 * The '| 1' sets the ARE field to send one autorefresh when the autorefresh 167 * counter reaches 0. 168 * 169 * These represent optimal values for common parts, it won't work for all. 170 * As long as you scale down, most parameters are still work, they just 171 * become sub-optimal. The RFR value goes in the opposite direction. If you 172 * don't adjust it down as your clock period increases the refresh interval 173 * will not be met. Setting all parameters for complete worst case may work, 174 * but may cut memory performance by 2x. Due to errata the DLLs need to be 175 * unlocked and their value needs run time calibration. A dynamic call is 176 * need for that as no single right value exists across production samples. 177 * 178 * Only the FULL speed values are given. Current code is such that rate 179 * changes must be made at DPLLoutx2. The actual value adjustment for low 180 * frequency operation will be handled by omap_set_performance() 181 * 182 * By having the boot loader boot up in the fastest L4 speed available likely 183 * will result in something which you can switch between. 184 */ 185 #define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1) 186 #define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) 187 #define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) 188 #define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ 189 #define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ 190 191 192 /* 193 * SMS register access 194 */ 195 196 #define OMAP242X_SMS_REGADDR(reg) \ 197 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg) 198 #define OMAP243X_SMS_REGADDR(reg) \ 199 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg) 200 #define OMAP343X_SMS_REGADDR(reg) \ 201 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg) 202 203 /* SMS register offsets - read/write with sms_{read,write}_reg() */ 204 205 #define SMS_SYSCONFIG 0x010 206 /* REVISIT: fill in other SMS registers here */ 207 208 209 210 #endif 211