1 /* 2 * SMS/SDRC (SDRAM controller) common code for OMAP2/3 3 * 4 * Copyright (C) 2005, 2008 Texas Instruments Inc. 5 * Copyright (C) 2005, 2008 Nokia Corporation 6 * 7 * Tony Lindgren <tony@atomide.com> 8 * Paul Walmsley 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/list.h> 21 #include <linux/errno.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 26 #include <plat/common.h> 27 #include <plat/clock.h> 28 #include <plat/sram.h> 29 30 #include "prm.h" 31 32 #include <plat/sdrc.h> 33 #include "sdrc.h" 34 35 static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1; 36 37 void __iomem *omap2_sdrc_base; 38 void __iomem *omap2_sms_base; 39 40 struct omap2_sms_regs { 41 u32 sms_sysconfig; 42 }; 43 44 static struct omap2_sms_regs sms_context; 45 46 /* SDRC_POWER register bits */ 47 #define SDRC_POWER_EXTCLKDIS_SHIFT 3 48 #define SDRC_POWER_PWDENA_SHIFT 2 49 #define SDRC_POWER_PAGEPOLICY_SHIFT 0 50 51 /** 52 * omap2_sms_save_context - Save SMS registers 53 * 54 * Save SMS registers that need to be restored after off mode. 55 */ 56 void omap2_sms_save_context(void) 57 { 58 sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG); 59 } 60 61 /** 62 * omap2_sms_restore_context - Restore SMS registers 63 * 64 * Restore SMS registers that need to be Restored after off mode. 65 */ 66 void omap2_sms_restore_context(void) 67 { 68 sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG); 69 } 70 71 /** 72 * omap2_sdrc_get_params - return SDRC register values for a given clock rate 73 * @r: SDRC clock rate (in Hz) 74 * @sdrc_cs0: chip select 0 ram timings ** 75 * @sdrc_cs1: chip select 1 ram timings ** 76 * 77 * Return pre-calculated values for the SDRC_ACTIM_CTRLA, 78 * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01] 79 * structs,for a given SDRC clock rate 'r'. 80 * These parameters control various timing delays in the SDRAM controller 81 * that are expressed in terms of the number of SDRC clock cycles to 82 * wait; hence the clock rate dependency. 83 * 84 * Supports 2 different timing parameters for both chip selects. 85 * 86 * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending. 87 * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size 88 * as sdrc_init_params_cs_0. 89 * 90 * Fills in the struct omap_sdrc_params * for each chip select. 91 * Returns 0 upon success or -1 upon failure. 92 */ 93 int omap2_sdrc_get_params(unsigned long r, 94 struct omap_sdrc_params **sdrc_cs0, 95 struct omap_sdrc_params **sdrc_cs1) 96 { 97 struct omap_sdrc_params *sp0, *sp1; 98 99 if (!sdrc_init_params_cs0) 100 return -1; 101 102 sp0 = sdrc_init_params_cs0; 103 sp1 = sdrc_init_params_cs1; 104 105 while (sp0->rate && sp0->rate != r) { 106 sp0++; 107 if (sdrc_init_params_cs1) 108 sp1++; 109 } 110 111 if (!sp0->rate) 112 return -1; 113 114 *sdrc_cs0 = sp0; 115 *sdrc_cs1 = sp1; 116 return 0; 117 } 118 119 120 void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) 121 { 122 omap2_sdrc_base = omap2_globals->sdrc; 123 omap2_sms_base = omap2_globals->sms; 124 } 125 126 /** 127 * omap2_sdrc_init - initialize SMS, SDRC devices on boot 128 * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params 129 * Support for 2 chip selects timings 130 * 131 * Turn on smart idle modes for SDRAM scheduler and controller. 132 * Program a known-good configuration for the SDRC to deal with buggy 133 * bootloaders. 134 */ 135 void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 136 struct omap_sdrc_params *sdrc_cs1) 137 { 138 u32 l; 139 140 l = sms_read_reg(SMS_SYSCONFIG); 141 l &= ~(0x3 << 3); 142 l |= (0x2 << 3); 143 sms_write_reg(l, SMS_SYSCONFIG); 144 145 l = sdrc_read_reg(SDRC_SYSCONFIG); 146 l &= ~(0x3 << 3); 147 l |= (0x2 << 3); 148 sdrc_write_reg(l, SDRC_SYSCONFIG); 149 150 sdrc_init_params_cs0 = sdrc_cs0; 151 sdrc_init_params_cs1 = sdrc_cs1; 152 153 /* XXX Enable SRFRONIDLEREQ here also? */ 154 /* 155 * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA 156 * can cause random memory corruption 157 */ 158 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | 159 (1 << SDRC_POWER_PAGEPOLICY_SHIFT); 160 sdrc_write_reg(l, SDRC_POWER); 161 omap2_sms_save_context(); 162 } 163 164 void omap2_sms_write_rot_control(u32 val, unsigned ctx) 165 { 166 sms_write_reg(val, SMS_ROT_CONTROL(ctx)); 167 } 168 169 void omap2_sms_write_rot_size(u32 val, unsigned ctx) 170 { 171 sms_write_reg(val, SMS_ROT_SIZE(ctx)); 172 } 173 174 void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx) 175 { 176 sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx)); 177 } 178 179