1f2ab9977SPaul Walmsley /* 2f2ab9977SPaul Walmsley * SMS/SDRC (SDRAM controller) common code for OMAP2/3 3f2ab9977SPaul Walmsley * 4f2ab9977SPaul Walmsley * Copyright (C) 2005, 2008 Texas Instruments Inc. 5f2ab9977SPaul Walmsley * Copyright (C) 2005, 2008 Nokia Corporation 6f2ab9977SPaul Walmsley * 7f2ab9977SPaul Walmsley * Tony Lindgren <tony@atomide.com> 8f2ab9977SPaul Walmsley * Paul Walmsley 9f2ab9977SPaul Walmsley * Richard Woodruff <r-woodruff2@ti.com> 10f2ab9977SPaul Walmsley * 11f2ab9977SPaul Walmsley * This program is free software; you can redistribute it and/or modify 12f2ab9977SPaul Walmsley * it under the terms of the GNU General Public License version 2 as 13f2ab9977SPaul Walmsley * published by the Free Software Foundation. 14f2ab9977SPaul Walmsley */ 1587246b75SPaul Walmsley #undef DEBUG 16f2ab9977SPaul Walmsley 17f2ab9977SPaul Walmsley #include <linux/module.h> 18f2ab9977SPaul Walmsley #include <linux/kernel.h> 19f2ab9977SPaul Walmsley #include <linux/device.h> 20f2ab9977SPaul Walmsley #include <linux/list.h> 21f2ab9977SPaul Walmsley #include <linux/errno.h> 22f2ab9977SPaul Walmsley #include <linux/delay.h> 23f2ab9977SPaul Walmsley #include <linux/clk.h> 24f2ab9977SPaul Walmsley #include <linux/io.h> 25f2ab9977SPaul Walmsley 26f2ab9977SPaul Walmsley #include <mach/common.h> 27f2ab9977SPaul Walmsley #include <mach/clock.h> 28f2ab9977SPaul Walmsley #include <mach/sram.h> 29f2ab9977SPaul Walmsley 30f2ab9977SPaul Walmsley #include "prm.h" 31f2ab9977SPaul Walmsley 32f2ab9977SPaul Walmsley #include <mach/sdrc.h> 33f2ab9977SPaul Walmsley #include "sdrc.h" 34f2ab9977SPaul Walmsley 3587246b75SPaul Walmsley static struct omap_sdrc_params *sdrc_init_params; 3687246b75SPaul Walmsley 37f2ab9977SPaul Walmsley void __iomem *omap2_sdrc_base; 38f2ab9977SPaul Walmsley void __iomem *omap2_sms_base; 39f2ab9977SPaul Walmsley 4098cfe5abSPaul Walmsley /* SDRC_POWER register bits */ 4198cfe5abSPaul Walmsley #define SDRC_POWER_EXTCLKDIS_SHIFT 3 4298cfe5abSPaul Walmsley #define SDRC_POWER_PWDENA_SHIFT 2 4398cfe5abSPaul Walmsley #define SDRC_POWER_PAGEPOLICY_SHIFT 0 4487246b75SPaul Walmsley 4587246b75SPaul Walmsley /** 4687246b75SPaul Walmsley * omap2_sdrc_get_params - return SDRC register values for a given clock rate 4787246b75SPaul Walmsley * @r: SDRC clock rate (in Hz) 4887246b75SPaul Walmsley * 4987246b75SPaul Walmsley * Return pre-calculated values for the SDRC_ACTIM_CTRLA, 5087246b75SPaul Walmsley * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given 5187246b75SPaul Walmsley * SDRC clock rate 'r'. These parameters control various timing 5287246b75SPaul Walmsley * delays in the SDRAM controller that are expressed in terms of the 5387246b75SPaul Walmsley * number of SDRC clock cycles to wait; hence the clock rate 5487246b75SPaul Walmsley * dependency. Note that sdrc_init_params must be sorted rate 5587246b75SPaul Walmsley * descending. Also assumes that both chip-selects use the same 5687246b75SPaul Walmsley * timing parameters. Returns a struct omap_sdrc_params * upon 5787246b75SPaul Walmsley * success, or NULL upon failure. 5887246b75SPaul Walmsley */ 5987246b75SPaul Walmsley struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r) 6087246b75SPaul Walmsley { 6187246b75SPaul Walmsley struct omap_sdrc_params *sp; 6287246b75SPaul Walmsley 638bd22949SKevin Hilman if (!sdrc_init_params) 648bd22949SKevin Hilman return NULL; 658bd22949SKevin Hilman 6687246b75SPaul Walmsley sp = sdrc_init_params; 6787246b75SPaul Walmsley 688bd22949SKevin Hilman while (sp->rate && sp->rate != r) 6987246b75SPaul Walmsley sp++; 7087246b75SPaul Walmsley 7187246b75SPaul Walmsley if (!sp->rate) 7287246b75SPaul Walmsley return NULL; 7387246b75SPaul Walmsley 7487246b75SPaul Walmsley return sp; 7587246b75SPaul Walmsley } 7687246b75SPaul Walmsley 7787246b75SPaul Walmsley 78f2ab9977SPaul Walmsley void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) 79f2ab9977SPaul Walmsley { 80f2ab9977SPaul Walmsley omap2_sdrc_base = omap2_globals->sdrc; 81f2ab9977SPaul Walmsley omap2_sms_base = omap2_globals->sms; 82f2ab9977SPaul Walmsley } 83f2ab9977SPaul Walmsley 8498cfe5abSPaul Walmsley /** 8598cfe5abSPaul Walmsley * omap2_sdrc_init - initialize SMS, SDRC devices on boot 8698cfe5abSPaul Walmsley * @sp: pointer to a null-terminated list of struct omap_sdrc_params 8798cfe5abSPaul Walmsley * 8898cfe5abSPaul Walmsley * Turn on smart idle modes for SDRAM scheduler and controller. 8998cfe5abSPaul Walmsley * Program a known-good configuration for the SDRC to deal with buggy 9098cfe5abSPaul Walmsley * bootloaders. 9198cfe5abSPaul Walmsley */ 9287246b75SPaul Walmsley void __init omap2_sdrc_init(struct omap_sdrc_params *sp) 93f2ab9977SPaul Walmsley { 94f2ab9977SPaul Walmsley u32 l; 95f2ab9977SPaul Walmsley 96f2ab9977SPaul Walmsley l = sms_read_reg(SMS_SYSCONFIG); 97f2ab9977SPaul Walmsley l &= ~(0x3 << 3); 98f2ab9977SPaul Walmsley l |= (0x2 << 3); 99f2ab9977SPaul Walmsley sms_write_reg(l, SMS_SYSCONFIG); 100f2ab9977SPaul Walmsley 101f2ab9977SPaul Walmsley l = sdrc_read_reg(SDRC_SYSCONFIG); 102f2ab9977SPaul Walmsley l &= ~(0x3 << 3); 103f2ab9977SPaul Walmsley l |= (0x2 << 3); 104f2ab9977SPaul Walmsley sdrc_write_reg(l, SDRC_SYSCONFIG); 10587246b75SPaul Walmsley 10687246b75SPaul Walmsley sdrc_init_params = sp; 10798cfe5abSPaul Walmsley 10898cfe5abSPaul Walmsley /* XXX Enable SRFRONIDLEREQ here also? */ 10998cfe5abSPaul Walmsley l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | 11098cfe5abSPaul Walmsley (1 << SDRC_POWER_PWDENA_SHIFT) | 11198cfe5abSPaul Walmsley (1 << SDRC_POWER_PAGEPOLICY_SHIFT); 11298cfe5abSPaul Walmsley sdrc_write_reg(l, SDRC_POWER); 113f2ab9977SPaul Walmsley } 114