1 /* 2 * OMAP4 PRM instance functions 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2011 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/types.h> 15 #include <linux/errno.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 19 #include "iomap.h" 20 #include "common.h" 21 #include "prcm-common.h" 22 #include "prm44xx.h" 23 #include "prm54xx.h" 24 #include "prm7xx.h" 25 #include "prminst44xx.h" 26 #include "prm-regbits-44xx.h" 27 #include "prcm44xx.h" 28 #include "prcm43xx.h" 29 #include "prcm_mpu44xx.h" 30 #include "soc.h" 31 32 static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 33 34 static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN; 35 36 /** 37 * omap_prm_base_init - Populates the prm partitions 38 * 39 * Populates the base addresses of the _prm_bases 40 * array used for read/write of prm module registers. 41 */ 42 void omap_prm_base_init(void) 43 { 44 _prm_bases[OMAP4430_PRM_PARTITION] = prm_base; 45 _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; 46 } 47 48 s32 omap4_prmst_get_prm_dev_inst(void) 49 { 50 if (prm_dev_inst != PRM_INSTANCE_UNKNOWN) 51 return prm_dev_inst; 52 53 /* This cannot be done way early at boot.. as things are not setup */ 54 if (cpu_is_omap44xx()) 55 prm_dev_inst = OMAP4430_PRM_DEVICE_INST; 56 else if (soc_is_omap54xx()) 57 prm_dev_inst = OMAP54XX_PRM_DEVICE_INST; 58 else if (soc_is_dra7xx()) 59 prm_dev_inst = DRA7XX_PRM_DEVICE_INST; 60 else if (soc_is_am43xx()) 61 prm_dev_inst = AM43XX_PRM_DEVICE_INST; 62 63 return prm_dev_inst; 64 } 65 66 /* Read a register in a PRM instance */ 67 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) 68 { 69 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 70 part == OMAP4430_INVALID_PRCM_PARTITION || 71 !_prm_bases[part]); 72 return readl_relaxed(_prm_bases[part] + inst + idx); 73 } 74 75 /* Write into a register in a PRM instance */ 76 void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) 77 { 78 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 79 part == OMAP4430_INVALID_PRCM_PARTITION || 80 !_prm_bases[part]); 81 writel_relaxed(val, _prm_bases[part] + inst + idx); 82 } 83 84 /* Read-modify-write a register in PRM. Caller must lock */ 85 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, 86 u16 idx) 87 { 88 u32 v; 89 90 v = omap4_prminst_read_inst_reg(part, inst, idx); 91 v &= ~mask; 92 v |= bits; 93 omap4_prminst_write_inst_reg(v, part, inst, idx); 94 95 return v; 96 } 97 98 /* 99 * Address offset (in bytes) between the reset control and the reset 100 * status registers: 4 bytes on OMAP4 101 */ 102 #define OMAP4_RST_CTRL_ST_OFFSET 4 103 104 /** 105 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of 106 * submodules contained in the hwmod module 107 * @rstctrl_reg: RM_RSTCTRL register address for this module 108 * @shift: register bit shift corresponding to the reset line to check 109 * 110 * Returns 1 if the (sub)module hardreset line is currently asserted, 111 * 0 if the (sub)module hardreset line is not currently asserted, or 112 * -EINVAL upon parameter error. 113 */ 114 int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst, 115 u16 rstctrl_offs) 116 { 117 u32 v; 118 119 v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs); 120 v &= 1 << shift; 121 v >>= shift; 122 123 return v; 124 } 125 126 /** 127 * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule 128 * @rstctrl_reg: RM_RSTCTRL register address for this module 129 * @shift: register bit shift corresponding to the reset line to assert 130 * 131 * Some IPs like dsp, ipu or iva contain processors that require an HW 132 * reset line to be asserted / deasserted in order to fully enable the 133 * IP. These modules may have multiple hard-reset lines that reset 134 * different 'submodules' inside the IP block. This function will 135 * place the submodule into reset. Returns 0 upon success or -EINVAL 136 * upon an argument error. 137 */ 138 int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst, 139 u16 rstctrl_offs) 140 { 141 u32 mask = 1 << shift; 142 143 omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs); 144 145 return 0; 146 } 147 148 /** 149 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and 150 * wait 151 * @rstctrl_reg: RM_RSTCTRL register address for this module 152 * @shift: register bit shift corresponding to the reset line to deassert 153 * 154 * Some IPs like dsp, ipu or iva contain processors that require an HW 155 * reset line to be asserted / deasserted in order to fully enable the 156 * IP. These modules may have multiple hard-reset lines that reset 157 * different 'submodules' inside the IP block. This function will 158 * take the submodule out of reset and wait until the PRCM indicates 159 * that the reset has completed before returning. Returns 0 upon success or 160 * -EINVAL upon an argument error, -EEXIST if the submodule was already out 161 * of reset, or -EBUSY if the submodule did not exit reset promptly. 162 */ 163 int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst, 164 u16 rstctrl_offs) 165 { 166 int c; 167 u32 mask = 1 << shift; 168 u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET; 169 170 /* Check the current status to avoid de-asserting the line twice */ 171 if (omap4_prminst_is_hardreset_asserted(shift, part, inst, 172 rstctrl_offs) == 0) 173 return -EEXIST; 174 175 /* Clear the reset status by writing 1 to the status bit */ 176 omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst, 177 rstst_offs); 178 /* de-assert the reset control line */ 179 omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs); 180 /* wait the status to be set */ 181 omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst, 182 rstst_offs), 183 MAX_MODULE_HARDRESET_WAIT, c); 184 185 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; 186 } 187 188 189 void omap4_prminst_global_warm_sw_reset(void) 190 { 191 u32 v; 192 s32 inst = omap4_prmst_get_prm_dev_inst(); 193 194 if (inst == PRM_INSTANCE_UNKNOWN) 195 return; 196 197 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst, 198 OMAP4_PRM_RSTCTRL_OFFSET); 199 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; 200 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, 201 inst, OMAP4_PRM_RSTCTRL_OFFSET); 202 203 /* OCP barrier */ 204 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 205 inst, OMAP4_PRM_RSTCTRL_OFFSET); 206 } 207