1 /* 2 * OMAP4 PRM instance functions 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2011 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/types.h> 15 #include <linux/errno.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 19 #include "iomap.h" 20 #include "common.h" 21 #include "prcm-common.h" 22 #include "prm44xx.h" 23 #include "prm54xx.h" 24 #include "prm7xx.h" 25 #include "prminst44xx.h" 26 #include "prm-regbits-44xx.h" 27 #include "prcm44xx.h" 28 #include "prcm43xx.h" 29 #include "prcm_mpu44xx.h" 30 #include "soc.h" 31 32 static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 33 34 static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN; 35 36 /** 37 * omap_prm_base_init - Populates the prm partitions 38 * 39 * Populates the base addresses of the _prm_bases 40 * array used for read/write of prm module registers. 41 */ 42 void omap_prm_base_init(void) 43 { 44 _prm_bases[OMAP4430_PRM_PARTITION] = prm_base; 45 _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base; 46 } 47 48 s32 omap4_prmst_get_prm_dev_inst(void) 49 { 50 return prm_dev_inst; 51 } 52 53 void omap4_prminst_set_prm_dev_inst(s32 dev_inst) 54 { 55 prm_dev_inst = dev_inst; 56 } 57 58 /* Read a register in a PRM instance */ 59 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) 60 { 61 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 62 part == OMAP4430_INVALID_PRCM_PARTITION || 63 !_prm_bases[part]); 64 return readl_relaxed(_prm_bases[part] + inst + idx); 65 } 66 67 /* Write into a register in a PRM instance */ 68 void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) 69 { 70 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 71 part == OMAP4430_INVALID_PRCM_PARTITION || 72 !_prm_bases[part]); 73 writel_relaxed(val, _prm_bases[part] + inst + idx); 74 } 75 76 /* Read-modify-write a register in PRM. Caller must lock */ 77 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, 78 u16 idx) 79 { 80 u32 v; 81 82 v = omap4_prminst_read_inst_reg(part, inst, idx); 83 v &= ~mask; 84 v |= bits; 85 omap4_prminst_write_inst_reg(v, part, inst, idx); 86 87 return v; 88 } 89 90 /* 91 * Address offset (in bytes) between the reset control and the reset 92 * status registers: 4 bytes on OMAP4 93 */ 94 #define OMAP4_RST_CTRL_ST_OFFSET 4 95 96 /** 97 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of 98 * submodules contained in the hwmod module 99 * @rstctrl_reg: RM_RSTCTRL register address for this module 100 * @shift: register bit shift corresponding to the reset line to check 101 * 102 * Returns 1 if the (sub)module hardreset line is currently asserted, 103 * 0 if the (sub)module hardreset line is not currently asserted, or 104 * -EINVAL upon parameter error. 105 */ 106 int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst, 107 u16 rstctrl_offs) 108 { 109 u32 v; 110 111 v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs); 112 v &= 1 << shift; 113 v >>= shift; 114 115 return v; 116 } 117 118 /** 119 * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule 120 * @rstctrl_reg: RM_RSTCTRL register address for this module 121 * @shift: register bit shift corresponding to the reset line to assert 122 * 123 * Some IPs like dsp, ipu or iva contain processors that require an HW 124 * reset line to be asserted / deasserted in order to fully enable the 125 * IP. These modules may have multiple hard-reset lines that reset 126 * different 'submodules' inside the IP block. This function will 127 * place the submodule into reset. Returns 0 upon success or -EINVAL 128 * upon an argument error. 129 */ 130 int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst, 131 u16 rstctrl_offs) 132 { 133 u32 mask = 1 << shift; 134 135 omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs); 136 137 return 0; 138 } 139 140 /** 141 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and 142 * wait 143 * @shift: register bit shift corresponding to the reset line to deassert 144 * @st_shift: status bit offset, not used for OMAP4+ 145 * @part: PRM partition 146 * @inst: PRM instance offset 147 * @rstctrl_offs: reset register offset 148 * @st_offs: reset status register offset, not used for OMAP4+ 149 * 150 * Some IPs like dsp, ipu or iva contain processors that require an HW 151 * reset line to be asserted / deasserted in order to fully enable the 152 * IP. These modules may have multiple hard-reset lines that reset 153 * different 'submodules' inside the IP block. This function will 154 * take the submodule out of reset and wait until the PRCM indicates 155 * that the reset has completed before returning. Returns 0 upon success or 156 * -EINVAL upon an argument error, -EEXIST if the submodule was already out 157 * of reset, or -EBUSY if the submodule did not exit reset promptly. 158 */ 159 int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst, 160 u16 rstctrl_offs, u16 st_offs) 161 { 162 int c; 163 u32 mask = 1 << shift; 164 u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET; 165 166 /* Check the current status to avoid de-asserting the line twice */ 167 if (omap4_prminst_is_hardreset_asserted(shift, part, inst, 168 rstctrl_offs) == 0) 169 return -EEXIST; 170 171 /* Clear the reset status by writing 1 to the status bit */ 172 omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst, 173 rstst_offs); 174 /* de-assert the reset control line */ 175 omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs); 176 /* wait the status to be set */ 177 omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst, 178 rstst_offs), 179 MAX_MODULE_HARDRESET_WAIT, c); 180 181 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; 182 } 183 184 185 void omap4_prminst_global_warm_sw_reset(void) 186 { 187 u32 v; 188 s32 inst = omap4_prmst_get_prm_dev_inst(); 189 190 if (inst == PRM_INSTANCE_UNKNOWN) 191 return; 192 193 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst, 194 OMAP4_PRM_RSTCTRL_OFFSET); 195 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; 196 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, 197 inst, OMAP4_PRM_RSTCTRL_OFFSET); 198 199 /* OCP barrier */ 200 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 201 inst, OMAP4_PRM_RSTCTRL_OFFSET); 202 } 203