1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * DRA7xx PRM instance offset macros 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Generated by code originally written by: 8 * Paul Walmsley (paul@pwsan.com) 9 * Rajendra Nayak (rnayak@ti.com) 10 * Benoit Cousson (b-cousson@ti.com) 11 * 12 * This file is automatically generated from the OMAP hardware databases. 13 * We respectfully ask that any modifications to this file be coordinated 14 * with the public linux-omap@vger.kernel.org mailing list and the 15 * authors above to ensure that the autogeneration scripts are kept 16 * up-to-date with the file contents. 17 */ 18 19 #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H 20 #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H 21 22 #include "prcm-common.h" 23 #include "prm44xx_54xx.h" 24 #include "prm.h" 25 26 #define DRA7XX_PRM_BASE 0x4ae06000 27 28 #define DRA7XX_PRM_REGADDR(inst, reg) \ 29 OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg)) 30 31 32 /* PRM instances */ 33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000 34 #define DRA7XX_PRM_CKGEN_INST 0x0100 35 #define DRA7XX_PRM_MPU_INST 0x0300 36 #define DRA7XX_PRM_DSP1_INST 0x0400 37 #define DRA7XX_PRM_IPU_INST 0x0500 38 #define DRA7XX_PRM_COREAON_INST 0x0628 39 #define DRA7XX_PRM_CORE_INST 0x0700 40 #define DRA7XX_PRM_IVA_INST 0x0f00 41 #define DRA7XX_PRM_CAM_INST 0x1000 42 #define DRA7XX_PRM_DSS_INST 0x1100 43 #define DRA7XX_PRM_GPU_INST 0x1200 44 #define DRA7XX_PRM_L3INIT_INST 0x1300 45 #define DRA7XX_PRM_L4PER_INST 0x1400 46 #define DRA7XX_PRM_CUSTEFUSE_INST 0x1600 47 #define DRA7XX_PRM_WKUPAON_INST 0x1724 48 #define DRA7XX_PRM_WKUPAON_CM_INST 0x1800 49 #define DRA7XX_PRM_EMU_INST 0x1900 50 #define DRA7XX_PRM_EMU_CM_INST 0x1a00 51 #define DRA7XX_PRM_DSP2_INST 0x1b00 52 #define DRA7XX_PRM_EVE1_INST 0x1b40 53 #define DRA7XX_PRM_EVE2_INST 0x1b80 54 #define DRA7XX_PRM_EVE3_INST 0x1bc0 55 #define DRA7XX_PRM_EVE4_INST 0x1c00 56 #define DRA7XX_PRM_RTC_INST 0x1c60 57 #define DRA7XX_PRM_VPE_INST 0x1c80 58 #define DRA7XX_PRM_DEVICE_INST 0x1d00 59 60 /* PRM clockdomain register offsets (from instance start) */ 61 #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 62 #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 63 64 /* PRM.CKGEN_PRM register offsets */ 65 #define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010) 66 67 #endif 68