1 /* 2 * DRA7xx PRM instance offset macros 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Generated by code originally written by: 7 * Paul Walmsley (paul@pwsan.com) 8 * Rajendra Nayak (rnayak@ti.com) 9 * Benoit Cousson (b-cousson@ti.com) 10 * 11 * This file is automatically generated from the OMAP hardware databases. 12 * We respectfully ask that any modifications to this file be coordinated 13 * with the public linux-omap@vger.kernel.org mailing list and the 14 * authors above to ensure that the autogeneration scripts are kept 15 * up-to-date with the file contents. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20 */ 21 22 #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H 23 #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H 24 25 #include "prm44xx_54xx.h" 26 #include "prcm-common.h" 27 #include "prm.h" 28 29 #define DRA7XX_PRM_BASE 0x4ae06000 30 31 #define DRA7XX_PRM_REGADDR(inst, reg) \ 32 OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg)) 33 34 35 /* PRM instances */ 36 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000 37 #define DRA7XX_PRM_CKGEN_INST 0x0100 38 #define DRA7XX_PRM_MPU_INST 0x0300 39 #define DRA7XX_PRM_DSP1_INST 0x0400 40 #define DRA7XX_PRM_IPU_INST 0x0500 41 #define DRA7XX_PRM_COREAON_INST 0x0628 42 #define DRA7XX_PRM_CORE_INST 0x0700 43 #define DRA7XX_PRM_IVA_INST 0x0f00 44 #define DRA7XX_PRM_CAM_INST 0x1000 45 #define DRA7XX_PRM_DSS_INST 0x1100 46 #define DRA7XX_PRM_GPU_INST 0x1200 47 #define DRA7XX_PRM_L3INIT_INST 0x1300 48 #define DRA7XX_PRM_L4PER_INST 0x1400 49 #define DRA7XX_PRM_CUSTEFUSE_INST 0x1600 50 #define DRA7XX_PRM_WKUPAON_INST 0x1724 51 #define DRA7XX_PRM_WKUPAON_CM_INST 0x1800 52 #define DRA7XX_PRM_EMU_INST 0x1900 53 #define DRA7XX_PRM_EMU_CM_INST 0x1a00 54 #define DRA7XX_PRM_DSP2_INST 0x1b00 55 #define DRA7XX_PRM_EVE1_INST 0x1b40 56 #define DRA7XX_PRM_EVE2_INST 0x1b80 57 #define DRA7XX_PRM_EVE3_INST 0x1bc0 58 #define DRA7XX_PRM_EVE4_INST 0x1c00 59 #define DRA7XX_PRM_RTC_INST 0x1c60 60 #define DRA7XX_PRM_VPE_INST 0x1c80 61 #define DRA7XX_PRM_DEVICE_INST 0x1d00 62 #define DRA7XX_PRM_INSTR_INST 0x1f00 63 64 /* PRM clockdomain register offsets (from instance start) */ 65 #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 66 #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 67 68 /* PRM */ 69 70 /* PRM.OCP_SOCKET_PRM register offsets */ 71 #define DRA7XX_REVISION_PRM_OFFSET 0x0000 72 #define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 73 #define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 74 #define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 75 #define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 76 #define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020 77 #define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028 78 #define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030 79 #define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038 80 #define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 81 #define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040) 82 #define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044 83 #define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048 84 #define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c 85 #define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050 86 #define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054 87 #define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058 88 #define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c 89 #define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060 90 #define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064 91 #define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068 92 #define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c 93 #define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070 94 #define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4 95 #define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8 96 #define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec 97 #define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4 98 99 /* PRM.CKGEN_PRM register offsets */ 100 #define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000 101 #define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000) 102 #define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 103 #define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008) 104 #define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c 105 #define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c) 106 #define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010 107 #define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010) 108 #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014 109 #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014) 110 #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018 111 #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018) 112 #define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c 113 #define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c) 114 #define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020 115 #define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020) 116 #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024 117 #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024) 118 #define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028 119 #define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028) 120 #define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c 121 #define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c) 122 #define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030 123 #define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030) 124 #define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034 125 #define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034) 126 #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038 127 #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038) 128 #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040 129 #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040) 130 #define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044 131 #define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044) 132 #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048 133 #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048) 134 #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c 135 #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c) 136 #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050 137 #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050) 138 #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054 139 #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054) 140 #define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058 141 #define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058) 142 #define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c 143 #define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c) 144 #define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060 145 #define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060) 146 #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064 147 #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064) 148 #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068 149 #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068) 150 #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c 151 #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c) 152 #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070 153 #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070) 154 #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074 155 #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074) 156 #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078 157 #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078) 158 #define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080 159 #define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080) 160 #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084 161 #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084) 162 #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088 163 #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088) 164 #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c 165 #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c) 166 #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090 167 #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090) 168 #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094 169 #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094) 170 #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098 171 #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098) 172 #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c 173 #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c) 174 #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0 175 #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0) 176 #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4 177 #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4) 178 #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8 179 #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8) 180 #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac 181 #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac) 182 #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0 183 #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0) 184 #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4 185 #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4) 186 #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8 187 #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8) 188 #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc 189 #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc) 190 #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0 191 #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0) 192 #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4 193 #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4) 194 #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8 195 #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8) 196 #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc 197 #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc) 198 #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0 199 #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0) 200 #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4 201 #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4) 202 #define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8 203 #define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8) 204 #define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc 205 #define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc) 206 #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0 207 #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0) 208 209 /* PRM.MPU_PRM register offsets */ 210 #define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 211 #define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004 212 #define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 213 214 /* PRM.DSP1_PRM register offsets */ 215 #define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000 216 #define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004 217 #define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010 218 #define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014 219 #define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024 220 221 /* PRM.IPU_PRM register offsets */ 222 #define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000 223 #define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004 224 #define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010 225 #define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014 226 #define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024 227 #define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050 228 #define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054 229 #define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058 230 #define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c 231 #define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060 232 #define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064 233 #define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068 234 #define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c 235 #define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070 236 #define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074 237 #define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078 238 #define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c 239 #define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080 240 #define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084 241 242 /* PRM.COREAON_PRM register offsets */ 243 #define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000 244 #define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004 245 #define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010 246 #define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014 247 #define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030 248 #define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034 249 #define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040 250 #define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044 251 #define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050 252 #define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054 253 #define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084 254 #define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094 255 #define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4 256 #define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4 257 258 /* PRM.CORE_PRM register offsets */ 259 #define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 260 #define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004 261 #define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 262 #define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c 263 #define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034 264 #define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050 265 #define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054 266 #define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058 267 #define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c 268 #define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060 269 #define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064 270 #define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c 271 #define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070 272 #define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074 273 #define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078 274 #define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c 275 #define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080 276 #define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084 277 #define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c 278 #define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094 279 #define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c 280 #define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4 281 #define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac 282 #define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4 283 #define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc 284 #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4 285 #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc 286 #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4 287 #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc 288 #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4 289 #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc 290 #define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210 291 #define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214 292 #define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224 293 #define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 294 #define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 295 #define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c 296 #define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 297 #define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c 298 #define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 299 #define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524 300 #define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 301 #define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c 302 #define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634 303 #define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 304 #define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 305 #define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c 306 #define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654 307 #define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c 308 #define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664 309 #define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c 310 #define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674 311 #define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c 312 #define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684 313 #define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c 314 #define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694 315 #define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c 316 #define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4 317 #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac 318 #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4 319 #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc 320 #define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4 321 #define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724 322 #define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 323 #define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 324 325 /* PRM.IVA_PRM register offsets */ 326 #define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 327 #define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004 328 #define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010 329 #define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014 330 #define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 331 #define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c 332 333 /* PRM.CAM_PRM register offsets */ 334 #define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 335 #define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004 336 #define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020 337 #define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024 338 #define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028 339 #define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c 340 #define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030 341 #define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034 342 #define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c 343 #define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044 344 #define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c 345 346 /* PRM.DSS_PRM register offsets */ 347 #define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 348 #define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004 349 #define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 350 #define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 351 #define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028 352 #define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 353 #define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c 354 355 /* PRM.GPU_PRM register offsets */ 356 #define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 357 #define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004 358 #define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 359 360 /* PRM.L3INIT_PRM register offsets */ 361 #define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 362 #define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 363 #define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 364 #define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 365 #define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 366 #define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 367 #define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040 368 #define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044 369 #define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048 370 #define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c 371 #define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050 372 #define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054 373 #define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c 374 #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c 375 #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 376 #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 377 #define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 378 #define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 379 #define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec 380 #define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0 381 #define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4 382 383 /* PRM.L4PER_PRM register offsets */ 384 #define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 385 #define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004 386 #define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c 387 #define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014 388 #define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c 389 #define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024 390 #define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028 391 #define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c 392 #define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030 393 #define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034 394 #define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038 395 #define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c 396 #define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040 397 #define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044 398 #define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048 399 #define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c 400 #define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050 401 #define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054 402 #define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c 403 #define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 404 #define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 405 #define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 406 #define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c 407 #define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 408 #define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 409 #define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 410 #define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c 411 #define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 412 #define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 413 #define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c 414 #define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094 415 #define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c 416 #define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 417 #define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 418 #define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 419 #define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac 420 #define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 421 #define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 422 #define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 423 #define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc 424 #define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0 425 #define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4 426 #define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8 427 #define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc 428 #define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0 429 #define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4 430 #define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8 431 #define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc 432 #define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 433 #define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 434 #define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 435 #define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc 436 #define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 437 #define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 438 #define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 439 #define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c 440 #define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110 441 #define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114 442 #define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118 443 #define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c 444 #define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120 445 #define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124 446 #define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128 447 #define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c 448 #define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130 449 #define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134 450 #define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138 451 #define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c 452 #define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 453 #define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 454 #define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 455 #define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c 456 #define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 457 #define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 458 #define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 459 #define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c 460 #define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160 461 #define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164 462 #define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168 463 #define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c 464 #define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170 465 #define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174 466 #define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178 467 #define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c 468 #define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180 469 #define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184 470 #define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188 471 #define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c 472 #define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190 473 #define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194 474 #define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198 475 #define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c 476 #define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 477 #define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac 478 #define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 479 #define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc 480 #define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 481 #define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc 482 #define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0 483 #define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4 484 #define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc 485 #define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0 486 #define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4 487 #define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8 488 #define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec 489 #define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0 490 #define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4 491 #define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc 492 493 /* PRM.CUSTEFUSE_PRM register offsets */ 494 #define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 495 #define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 496 #define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 497 498 /* PRM.WKUPAON_PRM register offsets */ 499 #define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000 500 #define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004 501 #define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008 502 #define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c 503 #define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010 504 #define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014 505 #define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018 506 #define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c 507 #define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020 508 #define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024 509 #define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028 510 #define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030 511 #define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040 512 #define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054 513 #define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058 514 #define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c 515 #define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060 516 #define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064 517 #define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068 518 #define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c 519 #define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080 520 #define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090 521 #define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098 522 #define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0 523 #define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8 524 #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0 525 #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8 526 527 /* PRM.WKUPAON_CM register offsets */ 528 #define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 529 #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 530 #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020) 531 #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 532 #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028) 533 #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 534 #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030) 535 #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 536 #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038) 537 #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 538 #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040) 539 #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 540 #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048) 541 #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 542 #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050) 543 #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 544 #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060) 545 #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 546 #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078) 547 #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080 548 #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080) 549 #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088 550 #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088) 551 #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 552 #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090) 553 #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 554 #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098) 555 #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0 556 #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0) 557 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0 558 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0) 559 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8 560 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8) 561 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0 562 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0) 563 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8 564 #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8) 565 #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0 566 #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0) 567 #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8 568 #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8) 569 570 /* PRM.EMU_PRM register offsets */ 571 #define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 572 #define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004 573 #define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 574 575 /* PRM.EMU_CM register offsets */ 576 #define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 577 #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004 578 #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004) 579 #define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 580 #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c 581 #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c) 582 583 /* PRM.DSP2_PRM register offsets */ 584 #define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000 585 #define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004 586 #define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010 587 #define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014 588 #define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024 589 590 /* PRM.EVE1_PRM register offsets */ 591 #define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000 592 #define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004 593 #define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010 594 #define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014 595 #define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020 596 #define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024 597 598 /* PRM.EVE2_PRM register offsets */ 599 #define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000 600 #define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004 601 #define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010 602 #define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014 603 #define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020 604 #define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024 605 606 /* PRM.EVE3_PRM register offsets */ 607 #define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000 608 #define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004 609 #define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010 610 #define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014 611 #define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020 612 #define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024 613 614 /* PRM.EVE4_PRM register offsets */ 615 #define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000 616 #define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004 617 #define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010 618 #define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014 619 #define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020 620 #define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024 621 622 /* PRM.RTC_PRM register offsets */ 623 #define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000 624 #define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004 625 626 /* PRM.VPE_PRM register offsets */ 627 #define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000 628 #define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004 629 #define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020 630 #define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024 631 632 /* PRM.DEVICE_PRM register offsets */ 633 #define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000 634 #define DRA7XX_PRM_RSTST_OFFSET 0x0004 635 #define DRA7XX_PRM_RSTTIME_OFFSET 0x0008 636 #define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c 637 #define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010 638 #define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014 639 #define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018 640 #define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c 641 #define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020 642 #define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 643 #define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 644 #define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 645 #define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 646 #define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 647 #define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 648 #define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c 649 #define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc 650 #define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 651 #define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 652 #define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 653 #define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc 654 #define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 655 #define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4 656 #define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8 657 #define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc 658 #define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 659 #define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4 660 #define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8 661 #define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec 662 #define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 663 #define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 664 #define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 665 #define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc 666 #define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 667 #define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110 668 #define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114 669 #define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118 670 #define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c 671 #define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120 672 #define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124 673 #define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128 674 #define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c 675 #define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130 676 #define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134 677 678 #endif 679