1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2da6f388bSAmbresh K /* 3da6f388bSAmbresh K * DRA7xx PRM instance offset macros 4da6f388bSAmbresh K * 5da6f388bSAmbresh K * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 6da6f388bSAmbresh K * 7da6f388bSAmbresh K * Generated by code originally written by: 8da6f388bSAmbresh K * Paul Walmsley (paul@pwsan.com) 9da6f388bSAmbresh K * Rajendra Nayak (rnayak@ti.com) 10da6f388bSAmbresh K * Benoit Cousson (b-cousson@ti.com) 11da6f388bSAmbresh K * 12da6f388bSAmbresh K * This file is automatically generated from the OMAP hardware databases. 13da6f388bSAmbresh K * We respectfully ask that any modifications to this file be coordinated 14da6f388bSAmbresh K * with the public linux-omap@vger.kernel.org mailing list and the 15da6f388bSAmbresh K * authors above to ensure that the autogeneration scripts are kept 16da6f388bSAmbresh K * up-to-date with the file contents. 17da6f388bSAmbresh K */ 18da6f388bSAmbresh K 19da6f388bSAmbresh K #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H 20da6f388bSAmbresh K #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H 21da6f388bSAmbresh K 22da6f388bSAmbresh K #include "prcm-common.h" 23ab7b2ffcSTero Kristo #include "prm44xx_54xx.h" 24da6f388bSAmbresh K #include "prm.h" 25da6f388bSAmbresh K 26da6f388bSAmbresh K #define DRA7XX_PRM_BASE 0x4ae06000 27da6f388bSAmbresh K 28da6f388bSAmbresh K #define DRA7XX_PRM_REGADDR(inst, reg) \ 29da6f388bSAmbresh K OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg)) 30da6f388bSAmbresh K 31da6f388bSAmbresh K 32da6f388bSAmbresh K /* PRM instances */ 33da6f388bSAmbresh K #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000 34da6f388bSAmbresh K #define DRA7XX_PRM_CKGEN_INST 0x0100 35da6f388bSAmbresh K #define DRA7XX_PRM_MPU_INST 0x0300 36da6f388bSAmbresh K #define DRA7XX_PRM_DSP1_INST 0x0400 37da6f388bSAmbresh K #define DRA7XX_PRM_IPU_INST 0x0500 38da6f388bSAmbresh K #define DRA7XX_PRM_COREAON_INST 0x0628 39da6f388bSAmbresh K #define DRA7XX_PRM_CORE_INST 0x0700 40da6f388bSAmbresh K #define DRA7XX_PRM_IVA_INST 0x0f00 41da6f388bSAmbresh K #define DRA7XX_PRM_CAM_INST 0x1000 42da6f388bSAmbresh K #define DRA7XX_PRM_DSS_INST 0x1100 43da6f388bSAmbresh K #define DRA7XX_PRM_GPU_INST 0x1200 44da6f388bSAmbresh K #define DRA7XX_PRM_L3INIT_INST 0x1300 45da6f388bSAmbresh K #define DRA7XX_PRM_L4PER_INST 0x1400 46da6f388bSAmbresh K #define DRA7XX_PRM_CUSTEFUSE_INST 0x1600 47da6f388bSAmbresh K #define DRA7XX_PRM_WKUPAON_INST 0x1724 48da6f388bSAmbresh K #define DRA7XX_PRM_WKUPAON_CM_INST 0x1800 49da6f388bSAmbresh K #define DRA7XX_PRM_EMU_INST 0x1900 50da6f388bSAmbresh K #define DRA7XX_PRM_EMU_CM_INST 0x1a00 51da6f388bSAmbresh K #define DRA7XX_PRM_DSP2_INST 0x1b00 52da6f388bSAmbresh K #define DRA7XX_PRM_EVE1_INST 0x1b40 53da6f388bSAmbresh K #define DRA7XX_PRM_EVE2_INST 0x1b80 54da6f388bSAmbresh K #define DRA7XX_PRM_EVE3_INST 0x1bc0 55da6f388bSAmbresh K #define DRA7XX_PRM_EVE4_INST 0x1c00 56da6f388bSAmbresh K #define DRA7XX_PRM_RTC_INST 0x1c60 57da6f388bSAmbresh K #define DRA7XX_PRM_VPE_INST 0x1c80 58da6f388bSAmbresh K #define DRA7XX_PRM_DEVICE_INST 0x1d00 59da6f388bSAmbresh K #define DRA7XX_PRM_INSTR_INST 0x1f00 60da6f388bSAmbresh K 61da6f388bSAmbresh K /* PRM clockdomain register offsets (from instance start) */ 62da6f388bSAmbresh K #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 63da6f388bSAmbresh K #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 64da6f388bSAmbresh K 65da6f388bSAmbresh K /* PRM */ 66da6f388bSAmbresh K 67da6f388bSAmbresh K /* PRM.OCP_SOCKET_PRM register offsets */ 68da6f388bSAmbresh K #define DRA7XX_REVISION_PRM_OFFSET 0x0000 69da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 70da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 71da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 72da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 73da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020 74da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028 75da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030 76da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038 77da6f388bSAmbresh K #define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 78da6f388bSAmbresh K #define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040) 79da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044 80da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048 81da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c 82da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050 83da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054 84da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058 85da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c 86da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060 87da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064 88da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068 89da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c 90da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070 91da6f388bSAmbresh K #define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4 92da6f388bSAmbresh K #define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8 93da6f388bSAmbresh K #define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec 94da6f388bSAmbresh K #define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4 95da6f388bSAmbresh K 96da6f388bSAmbresh K /* PRM.CKGEN_PRM register offsets */ 97da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000 98da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000) 99da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 100da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008) 101da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c 102da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c) 103da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010 104da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010) 105da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014 106da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014) 107da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018 108da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018) 109da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c 110da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c) 111da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020 112da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020) 113da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024 114da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024) 115da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028 116da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028) 117da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c 118da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c) 119da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030 120da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030) 121da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034 122da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034) 123da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038 124da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038) 125da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040 126da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040) 127da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044 128da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044) 129da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048 130da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048) 131da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c 132da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c) 133da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050 134da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050) 135da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054 136da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054) 137da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058 138da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058) 139da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c 140da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c) 141da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060 142da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060) 143da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064 144da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064) 145da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068 146da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068) 147da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c 148da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c) 149da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070 150da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070) 151da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074 152da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074) 153da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078 154da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078) 155da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080 156da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080) 157da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084 158da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084) 159da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088 160da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088) 161da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c 162da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c) 163da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090 164da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090) 165da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094 166da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094) 167da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098 168da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098) 169da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c 170da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c) 171da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0 172da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0) 173da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4 174da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4) 175da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8 176da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8) 177da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac 178da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac) 179da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0 180da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0) 181da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4 182da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4) 183da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8 184da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8) 185da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc 186da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc) 187da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0 188da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0) 189da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4 190da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4) 191da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8 192da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8) 193da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc 194da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc) 195da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0 196da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0) 197da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4 198da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4) 199da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8 200da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8) 201da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc 202da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc) 203da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0 204da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0) 205da6f388bSAmbresh K 206da6f388bSAmbresh K /* PRM.MPU_PRM register offsets */ 207da6f388bSAmbresh K #define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 208da6f388bSAmbresh K #define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004 209da6f388bSAmbresh K #define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 210da6f388bSAmbresh K 211da6f388bSAmbresh K /* PRM.DSP1_PRM register offsets */ 212da6f388bSAmbresh K #define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000 213da6f388bSAmbresh K #define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004 214da6f388bSAmbresh K #define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010 215da6f388bSAmbresh K #define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014 216da6f388bSAmbresh K #define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024 217da6f388bSAmbresh K 218da6f388bSAmbresh K /* PRM.IPU_PRM register offsets */ 219da6f388bSAmbresh K #define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000 220da6f388bSAmbresh K #define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004 221da6f388bSAmbresh K #define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010 222da6f388bSAmbresh K #define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014 223da6f388bSAmbresh K #define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024 224da6f388bSAmbresh K #define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050 225da6f388bSAmbresh K #define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054 226da6f388bSAmbresh K #define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058 227da6f388bSAmbresh K #define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c 228da6f388bSAmbresh K #define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060 229da6f388bSAmbresh K #define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064 230da6f388bSAmbresh K #define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068 231da6f388bSAmbresh K #define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c 232da6f388bSAmbresh K #define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070 233da6f388bSAmbresh K #define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074 234da6f388bSAmbresh K #define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078 235da6f388bSAmbresh K #define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c 236da6f388bSAmbresh K #define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080 237da6f388bSAmbresh K #define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084 238da6f388bSAmbresh K 239da6f388bSAmbresh K /* PRM.COREAON_PRM register offsets */ 240da6f388bSAmbresh K #define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000 241da6f388bSAmbresh K #define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004 242da6f388bSAmbresh K #define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010 243da6f388bSAmbresh K #define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014 244da6f388bSAmbresh K #define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030 245da6f388bSAmbresh K #define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034 246da6f388bSAmbresh K #define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040 247da6f388bSAmbresh K #define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044 248da6f388bSAmbresh K #define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050 249da6f388bSAmbresh K #define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054 250da6f388bSAmbresh K #define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084 251da6f388bSAmbresh K #define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094 252da6f388bSAmbresh K #define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4 253da6f388bSAmbresh K #define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4 254da6f388bSAmbresh K 255da6f388bSAmbresh K /* PRM.CORE_PRM register offsets */ 256da6f388bSAmbresh K #define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 257da6f388bSAmbresh K #define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004 258da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 259da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c 260da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034 261da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050 262da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054 263da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058 264da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c 265da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060 266da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064 267da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c 268da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070 269da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074 270da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078 271da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c 272da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080 273da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084 274da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c 275da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094 276da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c 277da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4 278da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac 279da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4 280da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc 281da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4 282da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc 283da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4 284da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc 285da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4 286da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc 287da6f388bSAmbresh K #define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210 288da6f388bSAmbresh K #define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214 289da6f388bSAmbresh K #define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224 290da6f388bSAmbresh K #define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 291da6f388bSAmbresh K #define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 292da6f388bSAmbresh K #define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c 293da6f388bSAmbresh K #define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 294da6f388bSAmbresh K #define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c 295da6f388bSAmbresh K #define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 296da6f388bSAmbresh K #define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524 297da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 298da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c 299da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634 300da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 301da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 302da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c 303da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654 304da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c 305da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664 306da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c 307da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674 308da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c 309da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684 310da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c 311da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694 312da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c 313da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4 314da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac 315da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4 316da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc 317da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4 318da6f388bSAmbresh K #define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724 319da6f388bSAmbresh K #define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 320da6f388bSAmbresh K #define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 321da6f388bSAmbresh K 322da6f388bSAmbresh K /* PRM.IVA_PRM register offsets */ 323da6f388bSAmbresh K #define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 324da6f388bSAmbresh K #define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004 325da6f388bSAmbresh K #define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010 326da6f388bSAmbresh K #define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014 327da6f388bSAmbresh K #define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 328da6f388bSAmbresh K #define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c 329da6f388bSAmbresh K 330da6f388bSAmbresh K /* PRM.CAM_PRM register offsets */ 331da6f388bSAmbresh K #define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 332da6f388bSAmbresh K #define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004 333da6f388bSAmbresh K #define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020 334da6f388bSAmbresh K #define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024 335da6f388bSAmbresh K #define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028 336da6f388bSAmbresh K #define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c 337da6f388bSAmbresh K #define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030 338da6f388bSAmbresh K #define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034 339da6f388bSAmbresh K #define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c 340da6f388bSAmbresh K #define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044 341da6f388bSAmbresh K #define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c 342da6f388bSAmbresh K 343da6f388bSAmbresh K /* PRM.DSS_PRM register offsets */ 344da6f388bSAmbresh K #define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 345da6f388bSAmbresh K #define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004 346da6f388bSAmbresh K #define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 347da6f388bSAmbresh K #define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 348da6f388bSAmbresh K #define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028 349da6f388bSAmbresh K #define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 350da6f388bSAmbresh K #define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c 351da6f388bSAmbresh K 352da6f388bSAmbresh K /* PRM.GPU_PRM register offsets */ 353da6f388bSAmbresh K #define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 354da6f388bSAmbresh K #define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004 355da6f388bSAmbresh K #define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 356da6f388bSAmbresh K 357da6f388bSAmbresh K /* PRM.L3INIT_PRM register offsets */ 358da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 359da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 3608fe097a3SKishon Vijay Abraham I #define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010 361da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 362da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 363da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 364da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 365da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040 366da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044 367da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048 368da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c 369da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050 370da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054 371da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c 372da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c 373da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 374da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 37570c18ef7SKishon Vijay Abraham I #define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0 37670c18ef7SKishon Vijay Abraham I #define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4 37770c18ef7SKishon Vijay Abraham I #define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8 37870c18ef7SKishon Vijay Abraham I #define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc 379da6f388bSAmbresh K #define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 380da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 381da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec 382da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0 383da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4 384da6f388bSAmbresh K 385da6f388bSAmbresh K /* PRM.L4PER_PRM register offsets */ 386da6f388bSAmbresh K #define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 387da6f388bSAmbresh K #define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004 388da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c 389da6f388bSAmbresh K #define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014 390da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c 391da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024 392da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028 393da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c 394da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030 395da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034 396da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038 397da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c 398da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040 399da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044 400da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048 401da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c 402da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050 403da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054 404da6f388bSAmbresh K #define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c 405da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 406da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 407da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 408da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c 409da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 410da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 411da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 412da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c 413da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 414da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 415da6f388bSAmbresh K #define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c 416da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094 417da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c 418da6f388bSAmbresh K #define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 419da6f388bSAmbresh K #define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 420da6f388bSAmbresh K #define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 421da6f388bSAmbresh K #define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac 422da6f388bSAmbresh K #define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 423da6f388bSAmbresh K #define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 424da6f388bSAmbresh K #define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 425da6f388bSAmbresh K #define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc 426da6f388bSAmbresh K #define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0 427da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4 428da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8 429da6f388bSAmbresh K #define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc 430da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0 431da6f388bSAmbresh K #define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4 432da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8 433da6f388bSAmbresh K #define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc 434da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 435da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 436da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 437da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc 438da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 439da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 440da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 441da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c 442da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110 443da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114 444da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118 445da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c 446da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120 447da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124 448da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128 449da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c 450da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130 451da6f388bSAmbresh K #define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134 452da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138 453da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c 454da6f388bSAmbresh K #define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 455da6f388bSAmbresh K #define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 456da6f388bSAmbresh K #define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 457da6f388bSAmbresh K #define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c 458da6f388bSAmbresh K #define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 459da6f388bSAmbresh K #define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 460da6f388bSAmbresh K #define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 461da6f388bSAmbresh K #define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c 462da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160 463da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164 464da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168 465da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c 466da6f388bSAmbresh K #define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170 467da6f388bSAmbresh K #define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174 468da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178 469da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c 470da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180 471da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184 472da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188 473da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c 474da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190 475da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194 476da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198 477da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c 478da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 479da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac 480da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 481da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc 482da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 483da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc 484da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0 485da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4 486da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc 487da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0 488da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4 489da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8 490da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec 491da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0 492da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4 493da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc 494da6f388bSAmbresh K 495da6f388bSAmbresh K /* PRM.CUSTEFUSE_PRM register offsets */ 496da6f388bSAmbresh K #define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 497da6f388bSAmbresh K #define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 498da6f388bSAmbresh K #define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 499da6f388bSAmbresh K 500da6f388bSAmbresh K /* PRM.WKUPAON_PRM register offsets */ 501da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000 502da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004 503da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008 504da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c 505da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010 506da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014 507da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018 508da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c 509da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020 510da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024 511da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028 512da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030 513da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040 514da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054 515da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058 516da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c 517da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060 518da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064 519da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068 520da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c 521da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080 522da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090 523da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098 524da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0 525da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8 526da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0 527da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8 528da6f388bSAmbresh K 529da6f388bSAmbresh K /* PRM.WKUPAON_CM register offsets */ 530da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 531da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 532da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020) 533da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 534da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028) 535da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 536da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030) 537da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 538da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038) 539da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 540da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040) 541da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 542da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048) 543da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 544da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050) 545da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 546da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060) 547da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 548da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078) 549da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080 550da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080) 551da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088 552da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088) 553da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 554da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090) 555da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 556da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098) 557da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0 558da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0) 559da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0 560da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0) 561da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8 562da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8) 563da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0 564da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0) 565da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8 566da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8) 567da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0 568da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0) 569da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8 570da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8) 571da6f388bSAmbresh K 572da6f388bSAmbresh K /* PRM.EMU_PRM register offsets */ 573da6f388bSAmbresh K #define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 574da6f388bSAmbresh K #define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004 575da6f388bSAmbresh K #define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 576da6f388bSAmbresh K 577da6f388bSAmbresh K /* PRM.EMU_CM register offsets */ 578da6f388bSAmbresh K #define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 579da6f388bSAmbresh K #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004 580da6f388bSAmbresh K #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004) 581da6f388bSAmbresh K #define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 582da6f388bSAmbresh K #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c 583da6f388bSAmbresh K #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c) 584da6f388bSAmbresh K 585da6f388bSAmbresh K /* PRM.DSP2_PRM register offsets */ 586da6f388bSAmbresh K #define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000 587da6f388bSAmbresh K #define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004 588da6f388bSAmbresh K #define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010 589da6f388bSAmbresh K #define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014 590da6f388bSAmbresh K #define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024 591da6f388bSAmbresh K 592da6f388bSAmbresh K /* PRM.EVE1_PRM register offsets */ 593da6f388bSAmbresh K #define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000 594da6f388bSAmbresh K #define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004 595da6f388bSAmbresh K #define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010 596da6f388bSAmbresh K #define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014 597da6f388bSAmbresh K #define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020 598da6f388bSAmbresh K #define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024 599da6f388bSAmbresh K 600da6f388bSAmbresh K /* PRM.EVE2_PRM register offsets */ 601da6f388bSAmbresh K #define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000 602da6f388bSAmbresh K #define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004 603da6f388bSAmbresh K #define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010 604da6f388bSAmbresh K #define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014 605da6f388bSAmbresh K #define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020 606da6f388bSAmbresh K #define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024 607da6f388bSAmbresh K 608da6f388bSAmbresh K /* PRM.EVE3_PRM register offsets */ 609da6f388bSAmbresh K #define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000 610da6f388bSAmbresh K #define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004 611da6f388bSAmbresh K #define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010 612da6f388bSAmbresh K #define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014 613da6f388bSAmbresh K #define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020 614da6f388bSAmbresh K #define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024 615da6f388bSAmbresh K 616da6f388bSAmbresh K /* PRM.EVE4_PRM register offsets */ 617da6f388bSAmbresh K #define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000 618da6f388bSAmbresh K #define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004 619da6f388bSAmbresh K #define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010 620da6f388bSAmbresh K #define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014 621da6f388bSAmbresh K #define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020 622da6f388bSAmbresh K #define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024 623da6f388bSAmbresh K 624da6f388bSAmbresh K /* PRM.RTC_PRM register offsets */ 625da6f388bSAmbresh K #define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000 626da6f388bSAmbresh K #define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004 627da6f388bSAmbresh K 628da6f388bSAmbresh K /* PRM.VPE_PRM register offsets */ 629da6f388bSAmbresh K #define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000 630da6f388bSAmbresh K #define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004 631da6f388bSAmbresh K #define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020 632da6f388bSAmbresh K #define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024 633da6f388bSAmbresh K 634da6f388bSAmbresh K /* PRM.DEVICE_PRM register offsets */ 635da6f388bSAmbresh K #define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000 636da6f388bSAmbresh K #define DRA7XX_PRM_RSTST_OFFSET 0x0004 637da6f388bSAmbresh K #define DRA7XX_PRM_RSTTIME_OFFSET 0x0008 638da6f388bSAmbresh K #define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c 639da6f388bSAmbresh K #define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010 640da6f388bSAmbresh K #define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014 641da6f388bSAmbresh K #define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018 642da6f388bSAmbresh K #define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c 643da6f388bSAmbresh K #define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020 644da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 645da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 646da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 647da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 648da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 649da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 650da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c 651da6f388bSAmbresh K #define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc 652da6f388bSAmbresh K #define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 653da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 654da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 655da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc 656da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 657da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4 658da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8 659da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc 660da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 661da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4 662da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8 663da6f388bSAmbresh K #define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec 664da6f388bSAmbresh K #define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 665da6f388bSAmbresh K #define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 666da6f388bSAmbresh K #define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 667da6f388bSAmbresh K #define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc 668da6f388bSAmbresh K #define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 669da6f388bSAmbresh K #define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110 670da6f388bSAmbresh K #define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114 671da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118 672da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c 673da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120 674da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124 675da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128 676da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c 677da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130 678da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134 679da6f388bSAmbresh K 680da6f388bSAmbresh K #endif 681