1da6f388bSAmbresh K /* 2da6f388bSAmbresh K * DRA7xx PRM instance offset macros 3da6f388bSAmbresh K * 4da6f388bSAmbresh K * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 5da6f388bSAmbresh K * 6da6f388bSAmbresh K * Generated by code originally written by: 7da6f388bSAmbresh K * Paul Walmsley (paul@pwsan.com) 8da6f388bSAmbresh K * Rajendra Nayak (rnayak@ti.com) 9da6f388bSAmbresh K * Benoit Cousson (b-cousson@ti.com) 10da6f388bSAmbresh K * 11da6f388bSAmbresh K * This file is automatically generated from the OMAP hardware databases. 12da6f388bSAmbresh K * We respectfully ask that any modifications to this file be coordinated 13da6f388bSAmbresh K * with the public linux-omap@vger.kernel.org mailing list and the 14da6f388bSAmbresh K * authors above to ensure that the autogeneration scripts are kept 15da6f388bSAmbresh K * up-to-date with the file contents. 16da6f388bSAmbresh K * 17da6f388bSAmbresh K * This program is free software; you can redistribute it and/or modify 18da6f388bSAmbresh K * it under the terms of the GNU General Public License version 2 as 19da6f388bSAmbresh K * published by the Free Software Foundation. 20da6f388bSAmbresh K */ 21da6f388bSAmbresh K 22da6f388bSAmbresh K #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H 23da6f388bSAmbresh K #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H 24da6f388bSAmbresh K 25da6f388bSAmbresh K #include "prcm-common.h" 26ab7b2ffcSTero Kristo #include "prm44xx_54xx.h" 27da6f388bSAmbresh K #include "prm.h" 28da6f388bSAmbresh K 29da6f388bSAmbresh K #define DRA7XX_PRM_BASE 0x4ae06000 30da6f388bSAmbresh K 31da6f388bSAmbresh K #define DRA7XX_PRM_REGADDR(inst, reg) \ 32da6f388bSAmbresh K OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg)) 33da6f388bSAmbresh K 34da6f388bSAmbresh K 35da6f388bSAmbresh K /* PRM instances */ 36da6f388bSAmbresh K #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000 37da6f388bSAmbresh K #define DRA7XX_PRM_CKGEN_INST 0x0100 38da6f388bSAmbresh K #define DRA7XX_PRM_MPU_INST 0x0300 39da6f388bSAmbresh K #define DRA7XX_PRM_DSP1_INST 0x0400 40da6f388bSAmbresh K #define DRA7XX_PRM_IPU_INST 0x0500 41da6f388bSAmbresh K #define DRA7XX_PRM_COREAON_INST 0x0628 42da6f388bSAmbresh K #define DRA7XX_PRM_CORE_INST 0x0700 43da6f388bSAmbresh K #define DRA7XX_PRM_IVA_INST 0x0f00 44da6f388bSAmbresh K #define DRA7XX_PRM_CAM_INST 0x1000 45da6f388bSAmbresh K #define DRA7XX_PRM_DSS_INST 0x1100 46da6f388bSAmbresh K #define DRA7XX_PRM_GPU_INST 0x1200 47da6f388bSAmbresh K #define DRA7XX_PRM_L3INIT_INST 0x1300 48da6f388bSAmbresh K #define DRA7XX_PRM_L4PER_INST 0x1400 49da6f388bSAmbresh K #define DRA7XX_PRM_CUSTEFUSE_INST 0x1600 50da6f388bSAmbresh K #define DRA7XX_PRM_WKUPAON_INST 0x1724 51da6f388bSAmbresh K #define DRA7XX_PRM_WKUPAON_CM_INST 0x1800 52da6f388bSAmbresh K #define DRA7XX_PRM_EMU_INST 0x1900 53da6f388bSAmbresh K #define DRA7XX_PRM_EMU_CM_INST 0x1a00 54da6f388bSAmbresh K #define DRA7XX_PRM_DSP2_INST 0x1b00 55da6f388bSAmbresh K #define DRA7XX_PRM_EVE1_INST 0x1b40 56da6f388bSAmbresh K #define DRA7XX_PRM_EVE2_INST 0x1b80 57da6f388bSAmbresh K #define DRA7XX_PRM_EVE3_INST 0x1bc0 58da6f388bSAmbresh K #define DRA7XX_PRM_EVE4_INST 0x1c00 59da6f388bSAmbresh K #define DRA7XX_PRM_RTC_INST 0x1c60 60da6f388bSAmbresh K #define DRA7XX_PRM_VPE_INST 0x1c80 61da6f388bSAmbresh K #define DRA7XX_PRM_DEVICE_INST 0x1d00 62da6f388bSAmbresh K #define DRA7XX_PRM_INSTR_INST 0x1f00 63da6f388bSAmbresh K 64da6f388bSAmbresh K /* PRM clockdomain register offsets (from instance start) */ 65da6f388bSAmbresh K #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 66da6f388bSAmbresh K #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 67da6f388bSAmbresh K 68da6f388bSAmbresh K /* PRM */ 69da6f388bSAmbresh K 70da6f388bSAmbresh K /* PRM.OCP_SOCKET_PRM register offsets */ 71da6f388bSAmbresh K #define DRA7XX_REVISION_PRM_OFFSET 0x0000 72da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 73da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 74da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 75da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 76da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020 77da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028 78da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030 79da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038 80da6f388bSAmbresh K #define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 81da6f388bSAmbresh K #define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040) 82da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044 83da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048 84da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c 85da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050 86da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054 87da6f388bSAmbresh K #define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058 88da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c 89da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060 90da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064 91da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068 92da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c 93da6f388bSAmbresh K #define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070 94da6f388bSAmbresh K #define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4 95da6f388bSAmbresh K #define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8 96da6f388bSAmbresh K #define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec 97da6f388bSAmbresh K #define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4 98da6f388bSAmbresh K 99da6f388bSAmbresh K /* PRM.CKGEN_PRM register offsets */ 100da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000 101da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000) 102da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 103da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008) 104da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c 105da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c) 106da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010 107da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010) 108da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014 109da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014) 110da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018 111da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018) 112da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c 113da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c) 114da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020 115da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020) 116da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024 117da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024) 118da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028 119da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028) 120da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c 121da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c) 122da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030 123da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030) 124da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034 125da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034) 126da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038 127da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038) 128da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040 129da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040) 130da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044 131da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044) 132da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048 133da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048) 134da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c 135da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c) 136da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050 137da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050) 138da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054 139da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054) 140da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058 141da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058) 142da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c 143da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c) 144da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060 145da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060) 146da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064 147da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064) 148da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068 149da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068) 150da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c 151da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c) 152da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070 153da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070) 154da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074 155da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074) 156da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078 157da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078) 158da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080 159da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080) 160da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084 161da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084) 162da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088 163da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088) 164da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c 165da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c) 166da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090 167da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090) 168da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094 169da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094) 170da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098 171da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098) 172da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c 173da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c) 174da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0 175da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0) 176da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4 177da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4) 178da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8 179da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8) 180da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac 181da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac) 182da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0 183da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0) 184da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4 185da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4) 186da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8 187da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8) 188da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc 189da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc) 190da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0 191da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0) 192da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4 193da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4) 194da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8 195da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8) 196da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc 197da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc) 198da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0 199da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0) 200da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4 201da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4) 202da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8 203da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8) 204da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc 205da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc) 206da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0 207da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0) 208da6f388bSAmbresh K 209da6f388bSAmbresh K /* PRM.MPU_PRM register offsets */ 210da6f388bSAmbresh K #define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 211da6f388bSAmbresh K #define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004 212da6f388bSAmbresh K #define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 213da6f388bSAmbresh K 214da6f388bSAmbresh K /* PRM.DSP1_PRM register offsets */ 215da6f388bSAmbresh K #define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000 216da6f388bSAmbresh K #define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004 217da6f388bSAmbresh K #define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010 218da6f388bSAmbresh K #define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014 219da6f388bSAmbresh K #define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024 220da6f388bSAmbresh K 221da6f388bSAmbresh K /* PRM.IPU_PRM register offsets */ 222da6f388bSAmbresh K #define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000 223da6f388bSAmbresh K #define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004 224da6f388bSAmbresh K #define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010 225da6f388bSAmbresh K #define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014 226da6f388bSAmbresh K #define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024 227da6f388bSAmbresh K #define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050 228da6f388bSAmbresh K #define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054 229da6f388bSAmbresh K #define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058 230da6f388bSAmbresh K #define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c 231da6f388bSAmbresh K #define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060 232da6f388bSAmbresh K #define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064 233da6f388bSAmbresh K #define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068 234da6f388bSAmbresh K #define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c 235da6f388bSAmbresh K #define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070 236da6f388bSAmbresh K #define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074 237da6f388bSAmbresh K #define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078 238da6f388bSAmbresh K #define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c 239da6f388bSAmbresh K #define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080 240da6f388bSAmbresh K #define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084 241da6f388bSAmbresh K 242da6f388bSAmbresh K /* PRM.COREAON_PRM register offsets */ 243da6f388bSAmbresh K #define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000 244da6f388bSAmbresh K #define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004 245da6f388bSAmbresh K #define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010 246da6f388bSAmbresh K #define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014 247da6f388bSAmbresh K #define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030 248da6f388bSAmbresh K #define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034 249da6f388bSAmbresh K #define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040 250da6f388bSAmbresh K #define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044 251da6f388bSAmbresh K #define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050 252da6f388bSAmbresh K #define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054 253da6f388bSAmbresh K #define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084 254da6f388bSAmbresh K #define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094 255da6f388bSAmbresh K #define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4 256da6f388bSAmbresh K #define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4 257da6f388bSAmbresh K 258da6f388bSAmbresh K /* PRM.CORE_PRM register offsets */ 259da6f388bSAmbresh K #define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 260da6f388bSAmbresh K #define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004 261da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 262da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c 263da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034 264da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050 265da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054 266da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058 267da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c 268da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060 269da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064 270da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c 271da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070 272da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074 273da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078 274da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c 275da6f388bSAmbresh K #define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080 276da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084 277da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c 278da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094 279da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c 280da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4 281da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac 282da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4 283da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc 284da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4 285da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc 286da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4 287da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc 288da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4 289da6f388bSAmbresh K #define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc 290da6f388bSAmbresh K #define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210 291da6f388bSAmbresh K #define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214 292da6f388bSAmbresh K #define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224 293da6f388bSAmbresh K #define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 294da6f388bSAmbresh K #define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 295da6f388bSAmbresh K #define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c 296da6f388bSAmbresh K #define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 297da6f388bSAmbresh K #define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c 298da6f388bSAmbresh K #define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 299da6f388bSAmbresh K #define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524 300da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 301da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c 302da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634 303da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 304da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 305da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c 306da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654 307da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c 308da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664 309da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c 310da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674 311da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c 312da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684 313da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c 314da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694 315da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c 316da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4 317da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac 318da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4 319da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc 320da6f388bSAmbresh K #define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4 321da6f388bSAmbresh K #define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724 322da6f388bSAmbresh K #define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 323da6f388bSAmbresh K #define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 324da6f388bSAmbresh K 325da6f388bSAmbresh K /* PRM.IVA_PRM register offsets */ 326da6f388bSAmbresh K #define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 327da6f388bSAmbresh K #define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004 328da6f388bSAmbresh K #define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010 329da6f388bSAmbresh K #define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014 330da6f388bSAmbresh K #define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 331da6f388bSAmbresh K #define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c 332da6f388bSAmbresh K 333da6f388bSAmbresh K /* PRM.CAM_PRM register offsets */ 334da6f388bSAmbresh K #define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 335da6f388bSAmbresh K #define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004 336da6f388bSAmbresh K #define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020 337da6f388bSAmbresh K #define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024 338da6f388bSAmbresh K #define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028 339da6f388bSAmbresh K #define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c 340da6f388bSAmbresh K #define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030 341da6f388bSAmbresh K #define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034 342da6f388bSAmbresh K #define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c 343da6f388bSAmbresh K #define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044 344da6f388bSAmbresh K #define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c 345da6f388bSAmbresh K 346da6f388bSAmbresh K /* PRM.DSS_PRM register offsets */ 347da6f388bSAmbresh K #define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 348da6f388bSAmbresh K #define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004 349da6f388bSAmbresh K #define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 350da6f388bSAmbresh K #define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 351da6f388bSAmbresh K #define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028 352da6f388bSAmbresh K #define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 353da6f388bSAmbresh K #define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c 354da6f388bSAmbresh K 355da6f388bSAmbresh K /* PRM.GPU_PRM register offsets */ 356da6f388bSAmbresh K #define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 357da6f388bSAmbresh K #define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004 358da6f388bSAmbresh K #define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 359da6f388bSAmbresh K 360da6f388bSAmbresh K /* PRM.L3INIT_PRM register offsets */ 361da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 362da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 3638fe097a3SKishon Vijay Abraham I #define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010 364da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 365da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 366da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 367da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 368da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040 369da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044 370da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048 371da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c 372da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050 373da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054 374da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c 375da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c 376da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 377da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 37870c18ef7SKishon Vijay Abraham I #define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0 37970c18ef7SKishon Vijay Abraham I #define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4 38070c18ef7SKishon Vijay Abraham I #define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8 38170c18ef7SKishon Vijay Abraham I #define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc 382da6f388bSAmbresh K #define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 383da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 384da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec 385da6f388bSAmbresh K #define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0 386da6f388bSAmbresh K #define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4 387da6f388bSAmbresh K 388da6f388bSAmbresh K /* PRM.L4PER_PRM register offsets */ 389da6f388bSAmbresh K #define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 390da6f388bSAmbresh K #define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004 391da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c 392da6f388bSAmbresh K #define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014 393da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c 394da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024 395da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028 396da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c 397da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030 398da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034 399da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038 400da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c 401da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040 402da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044 403da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048 404da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c 405da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050 406da6f388bSAmbresh K #define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054 407da6f388bSAmbresh K #define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c 408da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 409da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 410da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 411da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c 412da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 413da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 414da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 415da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c 416da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 417da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 418da6f388bSAmbresh K #define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c 419da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094 420da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c 421da6f388bSAmbresh K #define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 422da6f388bSAmbresh K #define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 423da6f388bSAmbresh K #define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 424da6f388bSAmbresh K #define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac 425da6f388bSAmbresh K #define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 426da6f388bSAmbresh K #define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 427da6f388bSAmbresh K #define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 428da6f388bSAmbresh K #define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc 429da6f388bSAmbresh K #define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0 430da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4 431da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8 432da6f388bSAmbresh K #define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc 433da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0 434da6f388bSAmbresh K #define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4 435da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8 436da6f388bSAmbresh K #define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc 437da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 438da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 439da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 440da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc 441da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 442da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 443da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 444da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c 445da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110 446da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114 447da6f388bSAmbresh K #define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118 448da6f388bSAmbresh K #define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c 449da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120 450da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124 451da6f388bSAmbresh K #define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128 452da6f388bSAmbresh K #define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c 453da6f388bSAmbresh K #define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130 454da6f388bSAmbresh K #define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134 455da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138 456da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c 457da6f388bSAmbresh K #define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 458da6f388bSAmbresh K #define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 459da6f388bSAmbresh K #define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 460da6f388bSAmbresh K #define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c 461da6f388bSAmbresh K #define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 462da6f388bSAmbresh K #define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 463da6f388bSAmbresh K #define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 464da6f388bSAmbresh K #define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c 465da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160 466da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164 467da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168 468da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c 469da6f388bSAmbresh K #define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170 470da6f388bSAmbresh K #define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174 471da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178 472da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c 473da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180 474da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184 475da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188 476da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c 477da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190 478da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194 479da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198 480da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c 481da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 482da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac 483da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 484da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc 485da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 486da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc 487da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0 488da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4 489da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc 490da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0 491da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4 492da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8 493da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec 494da6f388bSAmbresh K #define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0 495da6f388bSAmbresh K #define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4 496da6f388bSAmbresh K #define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc 497da6f388bSAmbresh K 498da6f388bSAmbresh K /* PRM.CUSTEFUSE_PRM register offsets */ 499da6f388bSAmbresh K #define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 500da6f388bSAmbresh K #define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 501da6f388bSAmbresh K #define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 502da6f388bSAmbresh K 503da6f388bSAmbresh K /* PRM.WKUPAON_PRM register offsets */ 504da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000 505da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004 506da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008 507da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c 508da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010 509da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014 510da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018 511da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c 512da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020 513da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024 514da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028 515da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030 516da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040 517da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054 518da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058 519da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c 520da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060 521da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064 522da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068 523da6f388bSAmbresh K #define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c 524da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080 525da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090 526da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098 527da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0 528da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8 529da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0 530da6f388bSAmbresh K #define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8 531da6f388bSAmbresh K 532da6f388bSAmbresh K /* PRM.WKUPAON_CM register offsets */ 533da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 534da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 535da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020) 536da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 537da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028) 538da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 539da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030) 540da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 541da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038) 542da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 543da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040) 544da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 545da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048) 546da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 547da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050) 548da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 549da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060) 550da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 551da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078) 552da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080 553da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080) 554da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088 555da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088) 556da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 557da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090) 558da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 559da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098) 560da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0 561da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0) 562da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0 563da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0) 564da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8 565da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8) 566da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0 567da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0) 568da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8 569da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8) 570da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0 571da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0) 572da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8 573da6f388bSAmbresh K #define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8) 574da6f388bSAmbresh K 575da6f388bSAmbresh K /* PRM.EMU_PRM register offsets */ 576da6f388bSAmbresh K #define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 577da6f388bSAmbresh K #define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004 578da6f388bSAmbresh K #define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 579da6f388bSAmbresh K 580da6f388bSAmbresh K /* PRM.EMU_CM register offsets */ 581da6f388bSAmbresh K #define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 582da6f388bSAmbresh K #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004 583da6f388bSAmbresh K #define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004) 584da6f388bSAmbresh K #define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 585da6f388bSAmbresh K #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c 586da6f388bSAmbresh K #define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c) 587da6f388bSAmbresh K 588da6f388bSAmbresh K /* PRM.DSP2_PRM register offsets */ 589da6f388bSAmbresh K #define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000 590da6f388bSAmbresh K #define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004 591da6f388bSAmbresh K #define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010 592da6f388bSAmbresh K #define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014 593da6f388bSAmbresh K #define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024 594da6f388bSAmbresh K 595da6f388bSAmbresh K /* PRM.EVE1_PRM register offsets */ 596da6f388bSAmbresh K #define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000 597da6f388bSAmbresh K #define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004 598da6f388bSAmbresh K #define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010 599da6f388bSAmbresh K #define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014 600da6f388bSAmbresh K #define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020 601da6f388bSAmbresh K #define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024 602da6f388bSAmbresh K 603da6f388bSAmbresh K /* PRM.EVE2_PRM register offsets */ 604da6f388bSAmbresh K #define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000 605da6f388bSAmbresh K #define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004 606da6f388bSAmbresh K #define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010 607da6f388bSAmbresh K #define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014 608da6f388bSAmbresh K #define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020 609da6f388bSAmbresh K #define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024 610da6f388bSAmbresh K 611da6f388bSAmbresh K /* PRM.EVE3_PRM register offsets */ 612da6f388bSAmbresh K #define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000 613da6f388bSAmbresh K #define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004 614da6f388bSAmbresh K #define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010 615da6f388bSAmbresh K #define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014 616da6f388bSAmbresh K #define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020 617da6f388bSAmbresh K #define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024 618da6f388bSAmbresh K 619da6f388bSAmbresh K /* PRM.EVE4_PRM register offsets */ 620da6f388bSAmbresh K #define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000 621da6f388bSAmbresh K #define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004 622da6f388bSAmbresh K #define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010 623da6f388bSAmbresh K #define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014 624da6f388bSAmbresh K #define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020 625da6f388bSAmbresh K #define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024 626da6f388bSAmbresh K 627da6f388bSAmbresh K /* PRM.RTC_PRM register offsets */ 628da6f388bSAmbresh K #define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000 629da6f388bSAmbresh K #define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004 630da6f388bSAmbresh K 631da6f388bSAmbresh K /* PRM.VPE_PRM register offsets */ 632da6f388bSAmbresh K #define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000 633da6f388bSAmbresh K #define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004 634da6f388bSAmbresh K #define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020 635da6f388bSAmbresh K #define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024 636da6f388bSAmbresh K 637da6f388bSAmbresh K /* PRM.DEVICE_PRM register offsets */ 638da6f388bSAmbresh K #define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000 639da6f388bSAmbresh K #define DRA7XX_PRM_RSTST_OFFSET 0x0004 640da6f388bSAmbresh K #define DRA7XX_PRM_RSTTIME_OFFSET 0x0008 641da6f388bSAmbresh K #define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c 642da6f388bSAmbresh K #define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010 643da6f388bSAmbresh K #define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014 644da6f388bSAmbresh K #define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018 645da6f388bSAmbresh K #define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c 646da6f388bSAmbresh K #define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020 647da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 648da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 649da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 650da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 651da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 652da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 653da6f388bSAmbresh K #define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c 654da6f388bSAmbresh K #define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc 655da6f388bSAmbresh K #define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 656da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 657da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 658da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc 659da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 660da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4 661da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8 662da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc 663da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 664da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4 665da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8 666da6f388bSAmbresh K #define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec 667da6f388bSAmbresh K #define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 668da6f388bSAmbresh K #define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 669da6f388bSAmbresh K #define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 670da6f388bSAmbresh K #define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc 671da6f388bSAmbresh K #define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 672da6f388bSAmbresh K #define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110 673da6f388bSAmbresh K #define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114 674da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118 675da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c 676da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120 677da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124 678da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128 679da6f388bSAmbresh K #define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c 680da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130 681da6f388bSAmbresh K #define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134 682da6f388bSAmbresh K 683da6f388bSAmbresh K #endif 684