1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2da6f388bSAmbresh K /* 3da6f388bSAmbresh K * DRA7xx PRM instance offset macros 4da6f388bSAmbresh K * 53aa36fddSAlexander A. Klimov * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6da6f388bSAmbresh K * 7da6f388bSAmbresh K * Generated by code originally written by: 8da6f388bSAmbresh K * Paul Walmsley (paul@pwsan.com) 9da6f388bSAmbresh K * Rajendra Nayak (rnayak@ti.com) 10da6f388bSAmbresh K * Benoit Cousson (b-cousson@ti.com) 11da6f388bSAmbresh K * 12da6f388bSAmbresh K * This file is automatically generated from the OMAP hardware databases. 13da6f388bSAmbresh K * We respectfully ask that any modifications to this file be coordinated 14da6f388bSAmbresh K * with the public linux-omap@vger.kernel.org mailing list and the 15da6f388bSAmbresh K * authors above to ensure that the autogeneration scripts are kept 16da6f388bSAmbresh K * up-to-date with the file contents. 17da6f388bSAmbresh K */ 18da6f388bSAmbresh K 19da6f388bSAmbresh K #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H 20da6f388bSAmbresh K #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H 21da6f388bSAmbresh K 22da6f388bSAmbresh K #include "prcm-common.h" 23ab7b2ffcSTero Kristo #include "prm44xx_54xx.h" 24da6f388bSAmbresh K #include "prm.h" 25da6f388bSAmbresh K 26da6f388bSAmbresh K #define DRA7XX_PRM_BASE 0x4ae06000 27da6f388bSAmbresh K 28da6f388bSAmbresh K #define DRA7XX_PRM_REGADDR(inst, reg) \ 29da6f388bSAmbresh K OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg)) 30da6f388bSAmbresh K 31da6f388bSAmbresh K 32da6f388bSAmbresh K /* PRM instances */ 33da6f388bSAmbresh K #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000 34da6f388bSAmbresh K #define DRA7XX_PRM_CKGEN_INST 0x0100 35da6f388bSAmbresh K #define DRA7XX_PRM_MPU_INST 0x0300 36da6f388bSAmbresh K #define DRA7XX_PRM_DSP1_INST 0x0400 37da6f388bSAmbresh K #define DRA7XX_PRM_IPU_INST 0x0500 38da6f388bSAmbresh K #define DRA7XX_PRM_COREAON_INST 0x0628 39da6f388bSAmbresh K #define DRA7XX_PRM_CORE_INST 0x0700 40da6f388bSAmbresh K #define DRA7XX_PRM_IVA_INST 0x0f00 41da6f388bSAmbresh K #define DRA7XX_PRM_CAM_INST 0x1000 42da6f388bSAmbresh K #define DRA7XX_PRM_DSS_INST 0x1100 43da6f388bSAmbresh K #define DRA7XX_PRM_GPU_INST 0x1200 44da6f388bSAmbresh K #define DRA7XX_PRM_L3INIT_INST 0x1300 45da6f388bSAmbresh K #define DRA7XX_PRM_L4PER_INST 0x1400 46da6f388bSAmbresh K #define DRA7XX_PRM_CUSTEFUSE_INST 0x1600 47da6f388bSAmbresh K #define DRA7XX_PRM_WKUPAON_INST 0x1724 48da6f388bSAmbresh K #define DRA7XX_PRM_WKUPAON_CM_INST 0x1800 49da6f388bSAmbresh K #define DRA7XX_PRM_EMU_INST 0x1900 50da6f388bSAmbresh K #define DRA7XX_PRM_EMU_CM_INST 0x1a00 51da6f388bSAmbresh K #define DRA7XX_PRM_DSP2_INST 0x1b00 52da6f388bSAmbresh K #define DRA7XX_PRM_EVE1_INST 0x1b40 53da6f388bSAmbresh K #define DRA7XX_PRM_EVE2_INST 0x1b80 54da6f388bSAmbresh K #define DRA7XX_PRM_EVE3_INST 0x1bc0 55da6f388bSAmbresh K #define DRA7XX_PRM_EVE4_INST 0x1c00 56da6f388bSAmbresh K #define DRA7XX_PRM_RTC_INST 0x1c60 57da6f388bSAmbresh K #define DRA7XX_PRM_VPE_INST 0x1c80 58da6f388bSAmbresh K #define DRA7XX_PRM_DEVICE_INST 0x1d00 59da6f388bSAmbresh K 60da6f388bSAmbresh K /* PRM clockdomain register offsets (from instance start) */ 61da6f388bSAmbresh K #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 62da6f388bSAmbresh K #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 63da6f388bSAmbresh K 64da6f388bSAmbresh K /* PRM.CKGEN_PRM register offsets */ 65da6f388bSAmbresh K #define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010) 66da6f388bSAmbresh K 67da6f388bSAmbresh K #endif 68