1 /* 2 * OMAP54xx PRM instance offset macros 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Paul Walmsley (paul@pwsan.com) 7 * Rajendra Nayak (rnayak@ti.com) 8 * Benoit Cousson (b-cousson@ti.com) 9 * 10 * This file is automatically generated from the OMAP hardware databases. 11 * We respectfully ask that any modifications to this file be coordinated 12 * with the public linux-omap@vger.kernel.org mailing list and the 13 * authors above to ensure that the autogeneration scripts are kept 14 * up-to-date with the file contents. 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as 18 * published by the Free Software Foundation. 19 */ 20 21 #ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H 22 #define __ARCH_ARM_MACH_OMAP2_PRM54XX_H 23 24 #include "prm44xx_54xx.h" 25 #include "prm.h" 26 27 #define OMAP54XX_PRM_BASE 0x4ae06000 28 29 #define OMAP54XX_PRM_REGADDR(inst, reg) \ 30 OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg)) 31 32 33 /* PRM instances */ 34 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000 35 #define OMAP54XX_PRM_CKGEN_INST 0x0100 36 #define OMAP54XX_PRM_MPU_INST 0x0300 37 #define OMAP54XX_PRM_DSP_INST 0x0400 38 #define OMAP54XX_PRM_ABE_INST 0x0500 39 #define OMAP54XX_PRM_COREAON_INST 0x0600 40 #define OMAP54XX_PRM_CORE_INST 0x0700 41 #define OMAP54XX_PRM_IVA_INST 0x1200 42 #define OMAP54XX_PRM_CAM_INST 0x1300 43 #define OMAP54XX_PRM_DSS_INST 0x1400 44 #define OMAP54XX_PRM_GPU_INST 0x1500 45 #define OMAP54XX_PRM_L3INIT_INST 0x1600 46 #define OMAP54XX_PRM_CUSTEFUSE_INST 0x1700 47 #define OMAP54XX_PRM_WKUPAON_INST 0x1800 48 #define OMAP54XX_PRM_WKUPAON_CM_INST 0x1900 49 #define OMAP54XX_PRM_EMU_INST 0x1a00 50 #define OMAP54XX_PRM_EMU_CM_INST 0x1b00 51 #define OMAP54XX_PRM_DEVICE_INST 0x1c00 52 #define OMAP54XX_PRM_INSTR_INST 0x1f00 53 54 /* PRM clockdomain register offsets (from instance start) */ 55 #define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 56 #define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 57 58 /* PRM */ 59 60 /* PRM.OCP_SOCKET_PRM register offsets */ 61 #define OMAP54XX_REVISION_PRM_OFFSET 0x0000 62 #define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 63 #define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 64 #define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 65 #define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 66 #define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET 0x0020 67 #define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET 0x0028 68 #define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030 69 #define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038 70 #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 71 #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040) 72 #define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084 73 #define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090 74 #define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094 75 #define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET 0x0098 76 #define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET 0x009c 77 #define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET 0x00a0 78 #define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET 0x00a4 79 80 /* PRM.CKGEN_PRM register offsets */ 81 #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000 82 #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000) 83 #define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 84 #define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008) 85 #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c 86 #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c) 87 #define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010 88 #define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010) 89 90 /* PRM.MPU_PRM register offsets */ 91 #define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 92 #define OMAP54XX_PM_MPU_PWRSTST_OFFSET 0x0004 93 #define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 94 95 /* PRM.DSP_PRM register offsets */ 96 #define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET 0x0000 97 #define OMAP54XX_PM_DSP_PWRSTST_OFFSET 0x0004 98 #define OMAP54XX_RM_DSP_RSTCTRL_OFFSET 0x0010 99 #define OMAP54XX_RM_DSP_RSTST_OFFSET 0x0014 100 #define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET 0x0024 101 102 /* PRM.ABE_PRM register offsets */ 103 #define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET 0x0000 104 #define OMAP54XX_PM_ABE_PWRSTST_OFFSET 0x0004 105 #define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET 0x002c 106 #define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET 0x0030 107 #define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET 0x0034 108 #define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 109 #define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c 110 #define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 111 #define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 112 #define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 113 #define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c 114 #define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 115 #define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 116 #define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 117 #define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c 118 #define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET 0x0060 119 #define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET 0x0064 120 #define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 121 #define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c 122 #define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 123 #define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 124 #define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 125 #define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c 126 #define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 127 #define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 128 #define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET 0x0088 129 #define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET 0x008c 130 131 /* PRM.COREAON_PRM register offsets */ 132 #define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0028 133 #define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x002c 134 #define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET 0x0030 135 #define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET 0x0034 136 #define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0038 137 #define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x003c 138 139 /* PRM.CORE_PRM register offsets */ 140 #define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 141 #define OMAP54XX_PM_CORE_PWRSTST_OFFSET 0x0004 142 #define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 143 #define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET 0x0124 144 #define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET 0x012c 145 #define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET 0x0134 146 #define OMAP54XX_RM_IPU_RSTCTRL_OFFSET 0x0210 147 #define OMAP54XX_RM_IPU_RSTST_OFFSET 0x0214 148 #define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET 0x0224 149 #define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 150 #define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 151 #define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c 152 #define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 153 #define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c 154 #define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 155 #define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET 0x0524 156 #define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET 0x052c 157 #define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET 0x0534 158 #define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 159 #define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c 160 #define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 161 #define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 162 #define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 163 #define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET 0x0724 164 #define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 165 #define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 166 #define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET 0x0824 167 #define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET 0x082c 168 #define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET 0x0834 169 #define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0928 170 #define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x092c 171 #define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0930 172 #define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0934 173 #define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0938 174 #define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x093c 175 #define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0940 176 #define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0944 177 #define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0948 178 #define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x094c 179 #define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0950 180 #define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0954 181 #define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x095c 182 #define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0960 183 #define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0964 184 #define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0968 185 #define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x096c 186 #define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0970 187 #define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0974 188 #define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0978 189 #define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x097c 190 #define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0980 191 #define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0984 192 #define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x098c 193 #define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x09a0 194 #define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x09a4 195 #define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x09a8 196 #define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x09ac 197 #define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x09b0 198 #define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x09b4 199 #define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x09b8 200 #define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x09bc 201 #define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x09c0 202 #define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x09f0 203 #define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x09f4 204 #define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x09f8 205 #define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x09fc 206 #define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0a00 207 #define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0a04 208 #define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0a08 209 #define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x0a0c 210 #define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0a10 211 #define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0a14 212 #define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0a18 213 #define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x0a1c 214 #define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0a20 215 #define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0a24 216 #define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0a28 217 #define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x0a2c 218 #define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0a40 219 #define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0a44 220 #define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0a48 221 #define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x0a4c 222 #define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0a50 223 #define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0a54 224 #define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x0a58 225 #define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0a5c 226 #define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET 0x0a60 227 #define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET 0x0a64 228 #define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET 0x0a68 229 #define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET 0x0a6c 230 #define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0a70 231 #define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0a74 232 #define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET 0x0a78 233 #define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET 0x0a7c 234 #define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x0aa4 235 #define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x0aac 236 #define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x0ab4 237 #define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x0abc 238 #define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x0ac4 239 #define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET 0x0acc 240 #define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x0adc 241 242 /* PRM.IVA_PRM register offsets */ 243 #define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 244 #define OMAP54XX_PM_IVA_PWRSTST_OFFSET 0x0004 245 #define OMAP54XX_RM_IVA_RSTCTRL_OFFSET 0x0010 246 #define OMAP54XX_RM_IVA_RSTST_OFFSET 0x0014 247 #define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 248 #define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c 249 250 /* PRM.CAM_PRM register offsets */ 251 #define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 252 #define OMAP54XX_PM_CAM_PWRSTST_OFFSET 0x0004 253 #define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 254 #define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c 255 #define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET 0x0034 256 257 /* PRM.DSS_PRM register offsets */ 258 #define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 259 #define OMAP54XX_PM_DSS_PWRSTST_OFFSET 0x0004 260 #define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 261 #define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 262 #define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 263 264 /* PRM.GPU_PRM register offsets */ 265 #define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 266 #define OMAP54XX_PM_GPU_PWRSTST_OFFSET 0x0004 267 #define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 268 269 /* PRM.L3INIT_PRM register offsets */ 270 #define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 271 #define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 272 #define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 273 #define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 274 #define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 275 #define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 276 #define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 277 #define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c 278 #define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET 0x0040 279 #define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET 0x0044 280 #define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET 0x0058 281 #define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET 0x005c 282 #define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET 0x0068 283 #define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET 0x006c 284 #define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c 285 #define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 286 #define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 287 #define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 288 #define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec 289 #define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET 0x00f0 290 #define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET 0x00f4 291 292 /* PRM.CUSTEFUSE_PRM register offsets */ 293 #define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 294 #define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 295 #define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 296 297 /* PRM.WKUPAON_PRM register offsets */ 298 #define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0024 299 #define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x002c 300 #define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x0030 301 #define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0034 302 #define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0038 303 #define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x003c 304 #define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x0040 305 #define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0044 306 #define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0048 307 #define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x004c 308 #define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0054 309 #define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0064 310 #define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0078 311 #define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x007c 312 313 /* PRM.WKUPAON_CM register offsets */ 314 #define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 315 #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 316 #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020) 317 #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 318 #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028) 319 #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 320 #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030) 321 #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 322 #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038) 323 #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 324 #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040) 325 #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 326 #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048) 327 #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 328 #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050) 329 #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 330 #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060) 331 #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 332 #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078) 333 #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 334 #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090) 335 #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 336 #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098) 337 338 /* PRM.EMU_PRM register offsets */ 339 #define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 340 #define OMAP54XX_PM_EMU_PWRSTST_OFFSET 0x0004 341 #define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 342 343 /* PRM.EMU_CM register offsets */ 344 #define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 345 #define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 346 #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 347 #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020) 348 #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028 349 #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028) 350 351 /* PRM.DEVICE_PRM register offsets */ 352 #define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000 353 #define OMAP54XX_PRM_RSTST_OFFSET 0x0004 354 #define OMAP54XX_PRM_RSTTIME_OFFSET 0x0008 355 #define OMAP54XX_PRM_CLKREQCTRL_OFFSET 0x000c 356 #define OMAP54XX_PRM_VOLTCTRL_OFFSET 0x0010 357 #define OMAP54XX_PRM_PWRREQCTRL_OFFSET 0x0014 358 #define OMAP54XX_PRM_PSCON_COUNT_OFFSET 0x0018 359 #define OMAP54XX_PRM_IO_COUNT_OFFSET 0x001c 360 #define OMAP54XX_PRM_IO_PMCTRL_OFFSET 0x0020 361 #define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 362 #define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 363 #define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 364 #define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 365 #define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 366 #define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 367 #define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c 368 #define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET 0x0040 369 #define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET 0x0044 370 #define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 371 #define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c 372 #define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 373 #define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 374 #define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET 0x0058 375 #define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET 0x005c 376 #define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 377 #define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 378 #define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 379 #define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c 380 #define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET 0x0070 381 #define OMAP54XX_PRM_VP_MM_STATUS_OFFSET 0x0074 382 #define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET 0x0078 383 #define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET 0x007c 384 #define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET 0x0080 385 #define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET 0x0084 386 #define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET 0x0088 387 #define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET 0x008c 388 #define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET 0x0090 389 #define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 390 #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET 0x0098 391 #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x009c 392 #define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 393 #define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET 0x00a4 394 #define OMAP54XX_PRM_VC_MM_ERRST_OFFSET 0x00a8 395 #define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET 0x00ac 396 #define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET 0x00b0 397 #define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET 0x00b4 398 #define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET 0x00b8 399 #define OMAP54XX_PRM_SRAM_COUNT_OFFSET 0x00bc 400 #define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 401 #define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 402 #define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 403 #define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc 404 #define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 405 #define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET 0x00d4 406 #define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET 0x00d8 407 #define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc 408 #define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 409 #define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET 0x00e4 410 #define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET 0x00e8 411 #define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec 412 #define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 413 #define OMAP54XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 414 #define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 415 #define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc 416 #define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 417 #define OMAP54XX_PRM_VOLTST_MPU_OFFSET 0x0110 418 #define OMAP54XX_PRM_VOLTST_MM_OFFSET 0x0114 419 420 #endif 421