1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * OMAP54xx PRM instance offset macros 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Paul Walmsley (paul@pwsan.com) 8 * Rajendra Nayak (rnayak@ti.com) 9 * Benoit Cousson (b-cousson@ti.com) 10 * 11 * This file is automatically generated from the OMAP hardware databases. 12 * We respectfully ask that any modifications to this file be coordinated 13 * with the public linux-omap@vger.kernel.org mailing list and the 14 * authors above to ensure that the autogeneration scripts are kept 15 * up-to-date with the file contents. 16 */ 17 18 #ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H 19 #define __ARCH_ARM_MACH_OMAP2_PRM54XX_H 20 21 #include "prm44xx_54xx.h" 22 #include "prm.h" 23 24 #define OMAP54XX_PRM_BASE 0x4ae06000 25 26 #define OMAP54XX_PRM_REGADDR(inst, reg) \ 27 OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg)) 28 29 30 /* PRM instances */ 31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000 32 #define OMAP54XX_PRM_CKGEN_INST 0x0100 33 #define OMAP54XX_PRM_MPU_INST 0x0300 34 #define OMAP54XX_PRM_DSP_INST 0x0400 35 #define OMAP54XX_PRM_ABE_INST 0x0500 36 #define OMAP54XX_PRM_COREAON_INST 0x0600 37 #define OMAP54XX_PRM_CORE_INST 0x0700 38 #define OMAP54XX_PRM_IVA_INST 0x1200 39 #define OMAP54XX_PRM_CAM_INST 0x1300 40 #define OMAP54XX_PRM_DSS_INST 0x1400 41 #define OMAP54XX_PRM_GPU_INST 0x1500 42 #define OMAP54XX_PRM_L3INIT_INST 0x1600 43 #define OMAP54XX_PRM_CUSTEFUSE_INST 0x1700 44 #define OMAP54XX_PRM_WKUPAON_INST 0x1800 45 #define OMAP54XX_PRM_WKUPAON_CM_INST 0x1900 46 #define OMAP54XX_PRM_EMU_INST 0x1a00 47 #define OMAP54XX_PRM_EMU_CM_INST 0x1b00 48 #define OMAP54XX_PRM_DEVICE_INST 0x1c00 49 #define OMAP54XX_PRM_INSTR_INST 0x1f00 50 51 /* PRM clockdomain register offsets (from instance start) */ 52 #define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 53 #define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 54 55 /* PRM */ 56 57 /* PRM.OCP_SOCKET_PRM register offsets */ 58 #define OMAP54XX_REVISION_PRM_OFFSET 0x0000 59 #define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 60 #define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 61 #define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 62 #define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 63 #define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET 0x0020 64 #define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET 0x0028 65 #define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030 66 #define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038 67 #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 68 #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040) 69 #define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084 70 #define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090 71 #define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094 72 #define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET 0x0098 73 #define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET 0x009c 74 #define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET 0x00a0 75 #define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET 0x00a4 76 77 /* PRM.CKGEN_PRM register offsets */ 78 #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000 79 #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000) 80 #define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 81 #define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008) 82 #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c 83 #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c) 84 #define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010 85 #define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010) 86 87 /* PRM.MPU_PRM register offsets */ 88 #define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 89 #define OMAP54XX_PM_MPU_PWRSTST_OFFSET 0x0004 90 #define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 91 92 /* PRM.DSP_PRM register offsets */ 93 #define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET 0x0000 94 #define OMAP54XX_PM_DSP_PWRSTST_OFFSET 0x0004 95 #define OMAP54XX_RM_DSP_RSTCTRL_OFFSET 0x0010 96 #define OMAP54XX_RM_DSP_RSTST_OFFSET 0x0014 97 #define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET 0x0024 98 99 /* PRM.ABE_PRM register offsets */ 100 #define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET 0x0000 101 #define OMAP54XX_PM_ABE_PWRSTST_OFFSET 0x0004 102 #define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET 0x002c 103 #define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET 0x0030 104 #define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET 0x0034 105 #define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 106 #define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c 107 #define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 108 #define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 109 #define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 110 #define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c 111 #define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 112 #define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 113 #define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 114 #define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c 115 #define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET 0x0060 116 #define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET 0x0064 117 #define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 118 #define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c 119 #define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 120 #define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 121 #define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 122 #define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c 123 #define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 124 #define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 125 #define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET 0x0088 126 #define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET 0x008c 127 128 /* PRM.COREAON_PRM register offsets */ 129 #define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0028 130 #define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x002c 131 #define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET 0x0030 132 #define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET 0x0034 133 #define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0038 134 #define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x003c 135 136 /* PRM.CORE_PRM register offsets */ 137 #define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 138 #define OMAP54XX_PM_CORE_PWRSTST_OFFSET 0x0004 139 #define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 140 #define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET 0x0124 141 #define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET 0x012c 142 #define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET 0x0134 143 #define OMAP54XX_RM_IPU_RSTCTRL_OFFSET 0x0210 144 #define OMAP54XX_RM_IPU_RSTST_OFFSET 0x0214 145 #define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET 0x0224 146 #define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 147 #define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 148 #define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c 149 #define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 150 #define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c 151 #define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 152 #define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET 0x0524 153 #define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET 0x052c 154 #define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET 0x0534 155 #define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 156 #define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c 157 #define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 158 #define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 159 #define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 160 #define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET 0x0724 161 #define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 162 #define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 163 #define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET 0x0824 164 #define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET 0x082c 165 #define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET 0x0834 166 #define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0928 167 #define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x092c 168 #define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0930 169 #define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0934 170 #define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0938 171 #define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x093c 172 #define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0940 173 #define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0944 174 #define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0948 175 #define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x094c 176 #define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0950 177 #define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0954 178 #define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x095c 179 #define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0960 180 #define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0964 181 #define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0968 182 #define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x096c 183 #define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0970 184 #define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0974 185 #define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0978 186 #define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x097c 187 #define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0980 188 #define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0984 189 #define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x098c 190 #define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x09a0 191 #define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x09a4 192 #define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x09a8 193 #define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x09ac 194 #define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x09b0 195 #define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x09b4 196 #define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x09b8 197 #define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x09bc 198 #define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x09c0 199 #define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x09f0 200 #define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x09f4 201 #define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x09f8 202 #define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x09fc 203 #define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0a00 204 #define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0a04 205 #define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0a08 206 #define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x0a0c 207 #define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0a10 208 #define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0a14 209 #define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0a18 210 #define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x0a1c 211 #define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0a20 212 #define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0a24 213 #define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0a28 214 #define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x0a2c 215 #define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0a40 216 #define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0a44 217 #define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0a48 218 #define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x0a4c 219 #define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0a50 220 #define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0a54 221 #define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x0a58 222 #define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0a5c 223 #define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET 0x0a60 224 #define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET 0x0a64 225 #define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET 0x0a68 226 #define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET 0x0a6c 227 #define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0a70 228 #define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0a74 229 #define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET 0x0a78 230 #define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET 0x0a7c 231 #define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x0aa4 232 #define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x0aac 233 #define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x0ab4 234 #define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x0abc 235 #define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x0ac4 236 #define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET 0x0acc 237 #define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x0adc 238 239 /* PRM.IVA_PRM register offsets */ 240 #define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 241 #define OMAP54XX_PM_IVA_PWRSTST_OFFSET 0x0004 242 #define OMAP54XX_RM_IVA_RSTCTRL_OFFSET 0x0010 243 #define OMAP54XX_RM_IVA_RSTST_OFFSET 0x0014 244 #define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 245 #define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c 246 247 /* PRM.CAM_PRM register offsets */ 248 #define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 249 #define OMAP54XX_PM_CAM_PWRSTST_OFFSET 0x0004 250 #define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 251 #define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c 252 #define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET 0x0034 253 254 /* PRM.DSS_PRM register offsets */ 255 #define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 256 #define OMAP54XX_PM_DSS_PWRSTST_OFFSET 0x0004 257 #define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 258 #define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 259 #define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 260 261 /* PRM.GPU_PRM register offsets */ 262 #define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 263 #define OMAP54XX_PM_GPU_PWRSTST_OFFSET 0x0004 264 #define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 265 266 /* PRM.L3INIT_PRM register offsets */ 267 #define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 268 #define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 269 #define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 270 #define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 271 #define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 272 #define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 273 #define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 274 #define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c 275 #define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET 0x0040 276 #define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET 0x0044 277 #define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET 0x0058 278 #define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET 0x005c 279 #define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET 0x0068 280 #define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET 0x006c 281 #define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c 282 #define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 283 #define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 284 #define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 285 #define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec 286 #define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET 0x00f0 287 #define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET 0x00f4 288 289 /* PRM.CUSTEFUSE_PRM register offsets */ 290 #define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 291 #define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 292 #define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 293 294 /* PRM.WKUPAON_PRM register offsets */ 295 #define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0024 296 #define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x002c 297 #define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x0030 298 #define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0034 299 #define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0038 300 #define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x003c 301 #define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x0040 302 #define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0044 303 #define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0048 304 #define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x004c 305 #define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0054 306 #define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0064 307 #define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0078 308 #define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x007c 309 310 /* PRM.WKUPAON_CM register offsets */ 311 #define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 312 #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 313 #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020) 314 #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 315 #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028) 316 #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 317 #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030) 318 #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 319 #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038) 320 #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 321 #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040) 322 #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 323 #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048) 324 #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 325 #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050) 326 #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 327 #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060) 328 #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 329 #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078) 330 #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 331 #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090) 332 #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 333 #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098) 334 335 /* PRM.EMU_PRM register offsets */ 336 #define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 337 #define OMAP54XX_PM_EMU_PWRSTST_OFFSET 0x0004 338 #define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 339 340 /* PRM.EMU_CM register offsets */ 341 #define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 342 #define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 343 #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 344 #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020) 345 #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028 346 #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028) 347 348 /* PRM.DEVICE_PRM register offsets */ 349 #define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000 350 #define OMAP54XX_PRM_RSTST_OFFSET 0x0004 351 #define OMAP54XX_PRM_RSTTIME_OFFSET 0x0008 352 #define OMAP54XX_PRM_CLKREQCTRL_OFFSET 0x000c 353 #define OMAP54XX_PRM_VOLTCTRL_OFFSET 0x0010 354 #define OMAP54XX_PRM_PWRREQCTRL_OFFSET 0x0014 355 #define OMAP54XX_PRM_PSCON_COUNT_OFFSET 0x0018 356 #define OMAP54XX_PRM_IO_COUNT_OFFSET 0x001c 357 #define OMAP54XX_PRM_IO_PMCTRL_OFFSET 0x0020 358 #define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 359 #define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 360 #define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 361 #define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 362 #define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 363 #define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 364 #define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c 365 #define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET 0x0040 366 #define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET 0x0044 367 #define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 368 #define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c 369 #define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 370 #define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 371 #define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET 0x0058 372 #define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET 0x005c 373 #define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 374 #define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 375 #define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 376 #define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c 377 #define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET 0x0070 378 #define OMAP54XX_PRM_VP_MM_STATUS_OFFSET 0x0074 379 #define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET 0x0078 380 #define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET 0x007c 381 #define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET 0x0080 382 #define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET 0x0084 383 #define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET 0x0088 384 #define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET 0x008c 385 #define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET 0x0090 386 #define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 387 #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET 0x0098 388 #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x009c 389 #define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 390 #define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET 0x00a4 391 #define OMAP54XX_PRM_VC_MM_ERRST_OFFSET 0x00a8 392 #define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET 0x00ac 393 #define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET 0x00b0 394 #define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET 0x00b4 395 #define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET 0x00b8 396 #define OMAP54XX_PRM_SRAM_COUNT_OFFSET 0x00bc 397 #define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 398 #define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 399 #define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 400 #define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc 401 #define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 402 #define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET 0x00d4 403 #define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET 0x00d8 404 #define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc 405 #define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 406 #define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET 0x00e4 407 #define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET 0x00e8 408 #define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec 409 #define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 410 #define OMAP54XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 411 #define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 412 #define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc 413 #define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 414 #define OMAP54XX_PRM_VOLTST_MPU_OFFSET 0x0110 415 #define OMAP54XX_PRM_VOLTST_MM_OFFSET 0x0114 416 417 #endif 418