xref: /openbmc/linux/arch/arm/mach-omap2/prm54xx.h (revision 3aa36fdd)
1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
242e872a4SBenoit Cousson /*
342e872a4SBenoit Cousson  * OMAP54xx PRM instance offset macros
442e872a4SBenoit Cousson  *
53aa36fddSAlexander A. Klimov  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
642e872a4SBenoit Cousson  *
742e872a4SBenoit Cousson  * Paul Walmsley (paul@pwsan.com)
842e872a4SBenoit Cousson  * Rajendra Nayak (rnayak@ti.com)
942e872a4SBenoit Cousson  * Benoit Cousson (b-cousson@ti.com)
1042e872a4SBenoit Cousson  *
1142e872a4SBenoit Cousson  * This file is automatically generated from the OMAP hardware databases.
1242e872a4SBenoit Cousson  * We respectfully ask that any modifications to this file be coordinated
1342e872a4SBenoit Cousson  * with the public linux-omap@vger.kernel.org mailing list and the
1442e872a4SBenoit Cousson  * authors above to ensure that the autogeneration scripts are kept
1542e872a4SBenoit Cousson  * up-to-date with the file contents.
1642e872a4SBenoit Cousson  */
1742e872a4SBenoit Cousson 
1842e872a4SBenoit Cousson #ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H
1942e872a4SBenoit Cousson #define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
2042e872a4SBenoit Cousson 
2142e872a4SBenoit Cousson #include "prm44xx_54xx.h"
2242e872a4SBenoit Cousson #include "prm.h"
2342e872a4SBenoit Cousson 
2442e872a4SBenoit Cousson #define OMAP54XX_PRM_BASE		0x4ae06000
2542e872a4SBenoit Cousson 
2642e872a4SBenoit Cousson #define OMAP54XX_PRM_REGADDR(inst, reg)				\
2742e872a4SBenoit Cousson 	OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
2842e872a4SBenoit Cousson 
2942e872a4SBenoit Cousson 
3042e872a4SBenoit Cousson /* PRM instances */
3142e872a4SBenoit Cousson #define OMAP54XX_PRM_OCP_SOCKET_INST	0x0000
3242e872a4SBenoit Cousson #define OMAP54XX_PRM_CKGEN_INST		0x0100
3342e872a4SBenoit Cousson #define OMAP54XX_PRM_MPU_INST		0x0300
3442e872a4SBenoit Cousson #define OMAP54XX_PRM_DSP_INST		0x0400
3542e872a4SBenoit Cousson #define OMAP54XX_PRM_ABE_INST		0x0500
3642e872a4SBenoit Cousson #define OMAP54XX_PRM_COREAON_INST	0x0600
3742e872a4SBenoit Cousson #define OMAP54XX_PRM_CORE_INST		0x0700
3842e872a4SBenoit Cousson #define OMAP54XX_PRM_IVA_INST		0x1200
3942e872a4SBenoit Cousson #define OMAP54XX_PRM_CAM_INST		0x1300
4042e872a4SBenoit Cousson #define OMAP54XX_PRM_DSS_INST		0x1400
4142e872a4SBenoit Cousson #define OMAP54XX_PRM_GPU_INST		0x1500
4242e872a4SBenoit Cousson #define OMAP54XX_PRM_L3INIT_INST	0x1600
4342e872a4SBenoit Cousson #define OMAP54XX_PRM_CUSTEFUSE_INST	0x1700
4442e872a4SBenoit Cousson #define OMAP54XX_PRM_WKUPAON_INST	0x1800
4542e872a4SBenoit Cousson #define OMAP54XX_PRM_WKUPAON_CM_INST	0x1900
4642e872a4SBenoit Cousson #define OMAP54XX_PRM_EMU_INST		0x1a00
4742e872a4SBenoit Cousson #define OMAP54XX_PRM_EMU_CM_INST	0x1b00
4842e872a4SBenoit Cousson #define OMAP54XX_PRM_DEVICE_INST	0x1c00
4942e872a4SBenoit Cousson #define OMAP54XX_PRM_INSTR_INST		0x1f00
5042e872a4SBenoit Cousson 
5142e872a4SBenoit Cousson /* PRM clockdomain register offsets (from instance start) */
5242e872a4SBenoit Cousson #define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS	0x0000
5342e872a4SBenoit Cousson #define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS		0x0000
5442e872a4SBenoit Cousson 
5542e872a4SBenoit Cousson /* PRM */
5642e872a4SBenoit Cousson 
5742e872a4SBenoit Cousson /* PRM.OCP_SOCKET_PRM register offsets */
5842e872a4SBenoit Cousson #define OMAP54XX_REVISION_PRM_OFFSET				0x0000
5942e872a4SBenoit Cousson #define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET			0x0010
6042e872a4SBenoit Cousson #define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET			0x0014
6142e872a4SBenoit Cousson #define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET			0x0018
6242e872a4SBenoit Cousson #define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET			0x001c
6342e872a4SBenoit Cousson #define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET			0x0020
6442e872a4SBenoit Cousson #define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET			0x0028
6542e872a4SBenoit Cousson #define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET			0x0030
6642e872a4SBenoit Cousson #define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET			0x0038
6742e872a4SBenoit Cousson #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET		0x0040
6842e872a4SBenoit Cousson #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040)
6942e872a4SBenoit Cousson #define OMAP54XX_PRM_DEBUG_OUT_OFFSET				0x0084
7042e872a4SBenoit Cousson #define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET			0x0090
7142e872a4SBenoit Cousson #define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET			0x0094
7242e872a4SBenoit Cousson #define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET		0x0098
7342e872a4SBenoit Cousson #define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET			0x009c
7442e872a4SBenoit Cousson #define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET			0x00a0
7542e872a4SBenoit Cousson #define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET		0x00a4
7642e872a4SBenoit Cousson 
7742e872a4SBenoit Cousson /* PRM.CKGEN_PRM register offsets */
7842e872a4SBenoit Cousson #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET			0x0000
7942e872a4SBenoit Cousson #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS				OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000)
8042e872a4SBenoit Cousson #define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET			0x0008
8142e872a4SBenoit Cousson #define OMAP54XX_CM_CLKSEL_WKUPAON				OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008)
8242e872a4SBenoit Cousson #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET			0x000c
8342e872a4SBenoit Cousson #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF				OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c)
8442e872a4SBenoit Cousson #define OMAP54XX_CM_CLKSEL_SYS_OFFSET				0x0010
8542e872a4SBenoit Cousson #define OMAP54XX_CM_CLKSEL_SYS					OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010)
8642e872a4SBenoit Cousson 
8742e872a4SBenoit Cousson /* PRM.MPU_PRM register offsets */
8842e872a4SBenoit Cousson #define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET			0x0000
8942e872a4SBenoit Cousson #define OMAP54XX_PM_MPU_PWRSTST_OFFSET				0x0004
9042e872a4SBenoit Cousson #define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET			0x0024
9142e872a4SBenoit Cousson 
9242e872a4SBenoit Cousson /* PRM.DSP_PRM register offsets */
9342e872a4SBenoit Cousson #define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET			0x0000
9442e872a4SBenoit Cousson #define OMAP54XX_PM_DSP_PWRSTST_OFFSET				0x0004
9542e872a4SBenoit Cousson #define OMAP54XX_RM_DSP_RSTCTRL_OFFSET				0x0010
9642e872a4SBenoit Cousson #define OMAP54XX_RM_DSP_RSTST_OFFSET				0x0014
9742e872a4SBenoit Cousson #define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET			0x0024
9842e872a4SBenoit Cousson 
9942e872a4SBenoit Cousson /* PRM.ABE_PRM register offsets */
10042e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET			0x0000
10142e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_PWRSTST_OFFSET				0x0004
10242e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET			0x002c
10342e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET			0x0030
10442e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET			0x0034
10542e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET			0x0038
10642e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET			0x003c
10742e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET			0x0040
10842e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET			0x0044
10942e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET			0x0048
11042e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET			0x004c
11142e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET			0x0050
11242e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET			0x0054
11342e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET			0x0058
11442e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET			0x005c
11542e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET			0x0060
11642e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET			0x0064
11742e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET			0x0068
11842e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET			0x006c
11942e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET			0x0070
12042e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET			0x0074
12142e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET			0x0078
12242e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET			0x007c
12342e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET			0x0080
12442e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET			0x0084
12542e872a4SBenoit Cousson #define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET			0x0088
12642e872a4SBenoit Cousson #define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET		0x008c
12742e872a4SBenoit Cousson 
12842e872a4SBenoit Cousson /* PRM.COREAON_PRM register offsets */
12942e872a4SBenoit Cousson #define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET	0x0028
13042e872a4SBenoit Cousson #define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET	0x002c
13142e872a4SBenoit Cousson #define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET		0x0030
13242e872a4SBenoit Cousson #define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET	0x0034
13342e872a4SBenoit Cousson #define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET	0x0038
13442e872a4SBenoit Cousson #define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET	0x003c
13542e872a4SBenoit Cousson 
13642e872a4SBenoit Cousson /* PRM.CORE_PRM register offsets */
13742e872a4SBenoit Cousson #define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET			0x0000
13842e872a4SBenoit Cousson #define OMAP54XX_PM_CORE_PWRSTST_OFFSET				0x0004
13942e872a4SBenoit Cousson #define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET		0x0024
14042e872a4SBenoit Cousson #define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET		0x0124
14142e872a4SBenoit Cousson #define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET			0x012c
14242e872a4SBenoit Cousson #define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET		0x0134
14342e872a4SBenoit Cousson #define OMAP54XX_RM_IPU_RSTCTRL_OFFSET				0x0210
14442e872a4SBenoit Cousson #define OMAP54XX_RM_IPU_RSTST_OFFSET				0x0214
14542e872a4SBenoit Cousson #define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET			0x0224
14642e872a4SBenoit Cousson #define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET		0x0324
14742e872a4SBenoit Cousson #define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET			0x0424
14842e872a4SBenoit Cousson #define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET		0x042c
14942e872a4SBenoit Cousson #define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET			0x0434
15042e872a4SBenoit Cousson #define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET			0x043c
15142e872a4SBenoit Cousson #define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET		0x0444
15242e872a4SBenoit Cousson #define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET			0x0524
15342e872a4SBenoit Cousson #define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET		0x052c
15442e872a4SBenoit Cousson #define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET		0x0534
15542e872a4SBenoit Cousson #define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET			0x0624
15642e872a4SBenoit Cousson #define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET		0x062c
15742e872a4SBenoit Cousson #define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET		0x0634
15842e872a4SBenoit Cousson #define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET		0x063c
15942e872a4SBenoit Cousson #define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET		0x0644
16042e872a4SBenoit Cousson #define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET		0x0724
16142e872a4SBenoit Cousson #define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET		0x072c
16242e872a4SBenoit Cousson #define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET		0x0744
16342e872a4SBenoit Cousson #define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET			0x0824
16442e872a4SBenoit Cousson #define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET		0x082c
16542e872a4SBenoit Cousson #define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET			0x0834
16642e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET			0x0928
16742e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET		0x092c
16842e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET			0x0930
16942e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET		0x0934
17042e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET			0x0938
17142e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET			0x093c
17242e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET			0x0940
17342e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET			0x0944
17442e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET			0x0948
17542e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET			0x094c
17642e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET			0x0950
17742e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET			0x0954
17842e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET			0x095c
17942e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET			0x0960
18042e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET			0x0964
18142e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET			0x0968
18242e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET			0x096c
18342e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET			0x0970
18442e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET			0x0974
18542e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET			0x0978
18642e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET			0x097c
18742e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET			0x0980
18842e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET			0x0984
18942e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET			0x098c
19042e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET			0x09a0
19142e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET			0x09a4
19242e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET			0x09a8
19342e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET			0x09ac
19442e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET			0x09b0
19542e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET			0x09b4
19642e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET			0x09b8
19742e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET			0x09bc
19842e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET			0x09c0
19942e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET			0x09f0
20042e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET			0x09f4
20142e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET			0x09f8
20242e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET			0x09fc
20342e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET			0x0a00
20442e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET			0x0a04
20542e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET			0x0a08
20642e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET			0x0a0c
20742e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET			0x0a10
20842e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET			0x0a14
20942e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET			0x0a18
21042e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET			0x0a1c
21142e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET			0x0a20
21242e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET			0x0a24
21342e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET			0x0a28
21442e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET			0x0a2c
21542e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET			0x0a40
21642e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET			0x0a44
21742e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET			0x0a48
21842e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET			0x0a4c
21942e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET			0x0a50
22042e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET			0x0a54
22142e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET			0x0a58
22242e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET			0x0a5c
22342e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET			0x0a60
22442e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET			0x0a64
22542e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET			0x0a68
22642e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET			0x0a6c
22742e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET			0x0a70
22842e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET			0x0a74
22942e872a4SBenoit Cousson #define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET			0x0a78
23042e872a4SBenoit Cousson #define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET			0x0a7c
23142e872a4SBenoit Cousson #define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET			0x0aa4
23242e872a4SBenoit Cousson #define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET			0x0aac
23342e872a4SBenoit Cousson #define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET		0x0ab4
23442e872a4SBenoit Cousson #define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET			0x0abc
23542e872a4SBenoit Cousson #define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET			0x0ac4
23642e872a4SBenoit Cousson #define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET		0x0acc
23742e872a4SBenoit Cousson #define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET		0x0adc
23842e872a4SBenoit Cousson 
23942e872a4SBenoit Cousson /* PRM.IVA_PRM register offsets */
24042e872a4SBenoit Cousson #define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET			0x0000
24142e872a4SBenoit Cousson #define OMAP54XX_PM_IVA_PWRSTST_OFFSET				0x0004
24242e872a4SBenoit Cousson #define OMAP54XX_RM_IVA_RSTCTRL_OFFSET				0x0010
24342e872a4SBenoit Cousson #define OMAP54XX_RM_IVA_RSTST_OFFSET				0x0014
24442e872a4SBenoit Cousson #define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET			0x0024
24542e872a4SBenoit Cousson #define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET			0x002c
24642e872a4SBenoit Cousson 
24742e872a4SBenoit Cousson /* PRM.CAM_PRM register offsets */
24842e872a4SBenoit Cousson #define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET			0x0000
24942e872a4SBenoit Cousson #define OMAP54XX_PM_CAM_PWRSTST_OFFSET				0x0004
25042e872a4SBenoit Cousson #define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET			0x0024
25142e872a4SBenoit Cousson #define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET			0x002c
25242e872a4SBenoit Cousson #define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET			0x0034
25342e872a4SBenoit Cousson 
25442e872a4SBenoit Cousson /* PRM.DSS_PRM register offsets */
25542e872a4SBenoit Cousson #define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET			0x0000
25642e872a4SBenoit Cousson #define OMAP54XX_PM_DSS_PWRSTST_OFFSET				0x0004
25742e872a4SBenoit Cousson #define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET			0x0020
25842e872a4SBenoit Cousson #define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET			0x0024
25942e872a4SBenoit Cousson #define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET			0x0034
26042e872a4SBenoit Cousson 
26142e872a4SBenoit Cousson /* PRM.GPU_PRM register offsets */
26242e872a4SBenoit Cousson #define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET			0x0000
26342e872a4SBenoit Cousson #define OMAP54XX_PM_GPU_PWRSTST_OFFSET				0x0004
26442e872a4SBenoit Cousson #define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET			0x0024
26542e872a4SBenoit Cousson 
26642e872a4SBenoit Cousson /* PRM.L3INIT_PRM register offsets */
26742e872a4SBenoit Cousson #define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET			0x0000
26842e872a4SBenoit Cousson #define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET			0x0004
26942e872a4SBenoit Cousson #define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET			0x0028
27042e872a4SBenoit Cousson #define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET			0x002c
27142e872a4SBenoit Cousson #define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET			0x0030
27242e872a4SBenoit Cousson #define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET			0x0034
27342e872a4SBenoit Cousson #define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET			0x0038
27442e872a4SBenoit Cousson #define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET			0x003c
27542e872a4SBenoit Cousson #define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET			0x0040
27642e872a4SBenoit Cousson #define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET		0x0044
27742e872a4SBenoit Cousson #define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET		0x0058
27842e872a4SBenoit Cousson #define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET		0x005c
27942e872a4SBenoit Cousson #define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET		0x0068
28042e872a4SBenoit Cousson #define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET		0x006c
28142e872a4SBenoit Cousson #define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET	0x007c
28242e872a4SBenoit Cousson #define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET			0x0088
28342e872a4SBenoit Cousson #define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET			0x008c
28442e872a4SBenoit Cousson #define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET		0x00e4
28542e872a4SBenoit Cousson #define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET		0x00ec
28642e872a4SBenoit Cousson #define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET		0x00f0
28742e872a4SBenoit Cousson #define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET		0x00f4
28842e872a4SBenoit Cousson 
28942e872a4SBenoit Cousson /* PRM.CUSTEFUSE_PRM register offsets */
29042e872a4SBenoit Cousson #define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET			0x0000
29142e872a4SBenoit Cousson #define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET			0x0004
29242e872a4SBenoit Cousson #define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET	0x0024
29342e872a4SBenoit Cousson 
29442e872a4SBenoit Cousson /* PRM.WKUPAON_PRM register offsets */
29542e872a4SBenoit Cousson #define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET		0x0024
29642e872a4SBenoit Cousson #define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET		0x002c
29742e872a4SBenoit Cousson #define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET		0x0030
29842e872a4SBenoit Cousson #define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET		0x0034
29942e872a4SBenoit Cousson #define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET			0x0038
30042e872a4SBenoit Cousson #define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET		0x003c
30142e872a4SBenoit Cousson #define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET			0x0040
30242e872a4SBenoit Cousson #define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET		0x0044
30342e872a4SBenoit Cousson #define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET		0x0048
30442e872a4SBenoit Cousson #define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET		0x004c
30542e872a4SBenoit Cousson #define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET		0x0054
30642e872a4SBenoit Cousson #define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET		0x0064
30742e872a4SBenoit Cousson #define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET			0x0078
30842e872a4SBenoit Cousson #define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET			0x007c
30942e872a4SBenoit Cousson 
31042e872a4SBenoit Cousson /* PRM.WKUPAON_CM register offsets */
31142e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET			0x0000
31242e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET		0x0020
31342e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020)
31442e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET		0x0028
31542e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028)
31642e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET		0x0030
31742e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030)
31842e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET		0x0038
31942e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038)
32042e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET		0x0040
32142e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040)
32242e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET		0x0048
32342e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048)
32442e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET		0x0050
32542e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050)
32642e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET		0x0060
32742e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060)
32842e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET			0x0078
32942e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL				OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078)
33042e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET			0x0090
33142e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090)
33242e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET		0x0098
33342e872a4SBenoit Cousson #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098)
33442e872a4SBenoit Cousson 
33542e872a4SBenoit Cousson /* PRM.EMU_PRM register offsets */
33642e872a4SBenoit Cousson #define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET			0x0000
33742e872a4SBenoit Cousson #define OMAP54XX_PM_EMU_PWRSTST_OFFSET				0x0004
33842e872a4SBenoit Cousson #define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET			0x0024
33942e872a4SBenoit Cousson 
34042e872a4SBenoit Cousson /* PRM.EMU_CM register offsets */
34142e872a4SBenoit Cousson #define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET			0x0000
34242e872a4SBenoit Cousson #define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET			0x0008
34342e872a4SBenoit Cousson #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET			0x0020
34442e872a4SBenoit Cousson #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL				OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020)
34542e872a4SBenoit Cousson #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET		0x0028
34642e872a4SBenoit Cousson #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL			OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028)
34742e872a4SBenoit Cousson 
34842e872a4SBenoit Cousson /* PRM.DEVICE_PRM register offsets */
34942e872a4SBenoit Cousson #define OMAP54XX_PRM_RSTCTRL_OFFSET				0x0000
35042e872a4SBenoit Cousson #define OMAP54XX_PRM_RSTST_OFFSET				0x0004
35142e872a4SBenoit Cousson #define OMAP54XX_PRM_RSTTIME_OFFSET				0x0008
35242e872a4SBenoit Cousson #define OMAP54XX_PRM_CLKREQCTRL_OFFSET				0x000c
35342e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTCTRL_OFFSET				0x0010
35442e872a4SBenoit Cousson #define OMAP54XX_PRM_PWRREQCTRL_OFFSET				0x0014
35542e872a4SBenoit Cousson #define OMAP54XX_PRM_PSCON_COUNT_OFFSET				0x0018
35642e872a4SBenoit Cousson #define OMAP54XX_PRM_IO_COUNT_OFFSET				0x001c
35742e872a4SBenoit Cousson #define OMAP54XX_PRM_IO_PMCTRL_OFFSET				0x0020
35842e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET			0x0024
35942e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET			0x0028
36042e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET			0x002c
36142e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET			0x0030
36242e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET		0x0034
36342e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET		0x0038
36442e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET		0x003c
36542e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET			0x0040
36642e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET			0x0044
36742e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET			0x0048
36842e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET			0x004c
36942e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET			0x0050
37042e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET			0x0054
37142e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET			0x0058
37242e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET			0x005c
37342e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET			0x0060
37442e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET			0x0064
37542e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET			0x0068
37642e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET			0x006c
37742e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET			0x0070
37842e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MM_STATUS_OFFSET			0x0074
37942e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET			0x0078
38042e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET			0x007c
38142e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET			0x0080
38242e872a4SBenoit Cousson #define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET			0x0084
38342e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET			0x0088
38442e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET			0x008c
38542e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET			0x0090
38642e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET		0x0094
38742e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET			0x0098
38842e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET		0x009c
38942e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET			0x00a0
39042e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET			0x00a4
39142e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_MM_ERRST_OFFSET				0x00a8
39242e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET			0x00ac
39342e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET			0x00b0
39442e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET			0x00b4
39542e872a4SBenoit Cousson #define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET			0x00b8
39642e872a4SBenoit Cousson #define OMAP54XX_PRM_SRAM_COUNT_OFFSET				0x00bc
39742e872a4SBenoit Cousson #define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET			0x00c0
39842e872a4SBenoit Cousson #define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET			0x00c4
39942e872a4SBenoit Cousson #define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET			0x00c8
40042e872a4SBenoit Cousson #define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET			0x00cc
40142e872a4SBenoit Cousson #define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET			0x00d0
40242e872a4SBenoit Cousson #define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET			0x00d4
40342e872a4SBenoit Cousson #define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET			0x00d8
40442e872a4SBenoit Cousson #define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET			0x00dc
40542e872a4SBenoit Cousson #define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET			0x00e0
40642e872a4SBenoit Cousson #define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET			0x00e4
40742e872a4SBenoit Cousson #define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET			0x00e8
40842e872a4SBenoit Cousson #define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET			0x00ec
40942e872a4SBenoit Cousson #define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET			0x00f0
41042e872a4SBenoit Cousson #define OMAP54XX_PRM_PHASE1_CNDP_OFFSET				0x00f4
41142e872a4SBenoit Cousson #define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET			0x00f8
41242e872a4SBenoit Cousson #define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET			0x00fc
41342e872a4SBenoit Cousson #define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET			0x0100
41442e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTST_MPU_OFFSET				0x0110
41542e872a4SBenoit Cousson #define OMAP54XX_PRM_VOLTST_MM_OFFSET				0x0114
41642e872a4SBenoit Cousson 
41742e872a4SBenoit Cousson #endif
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