1c1294045SRajendra Nayak /* 2c1294045SRajendra Nayak * OMAP44xx PRM instance offset macros 3c1294045SRajendra Nayak * 426c98c56SPaul Walmsley * Copyright (C) 2009-2011 Texas Instruments, Inc. 579328706SBenoit Cousson * Copyright (C) 2009-2010 Nokia Corporation 6c1294045SRajendra Nayak * 7c1294045SRajendra Nayak * Paul Walmsley (paul@pwsan.com) 8c1294045SRajendra Nayak * Rajendra Nayak (rnayak@ti.com) 9c1294045SRajendra Nayak * Benoit Cousson (b-cousson@ti.com) 10c1294045SRajendra Nayak * 11c1294045SRajendra Nayak * This file is automatically generated from the OMAP hardware databases. 12c1294045SRajendra Nayak * We respectfully ask that any modifications to this file be coordinated 13c1294045SRajendra Nayak * with the public linux-omap@vger.kernel.org mailing list and the 14c1294045SRajendra Nayak * authors above to ensure that the autogeneration scripts are kept 15c1294045SRajendra Nayak * up-to-date with the file contents. 16c1294045SRajendra Nayak * 17c1294045SRajendra Nayak * This program is free software; you can redistribute it and/or modify 18c1294045SRajendra Nayak * it under the terms of the GNU General Public License version 2 as 19c1294045SRajendra Nayak * published by the Free Software Foundation. 20d198b514SPaul Walmsley * 21d198b514SPaul Walmsley * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 22d198b514SPaul Walmsley * or "OMAP4430". 23c1294045SRajendra Nayak */ 24c1294045SRajendra Nayak 25c1294045SRajendra Nayak #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H 26c1294045SRajendra Nayak #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H 27c1294045SRajendra Nayak 28d198b514SPaul Walmsley #include "prcm-common.h" 2959fb659bSPaul Walmsley #include "prm.h" 30d198b514SPaul Walmsley 31d198b514SPaul Walmsley #define OMAP4430_PRM_BASE 0x4a306000 32d198b514SPaul Walmsley 33cdb54c44SPaul Walmsley #define OMAP44XX_PRM_REGADDR(inst, reg) \ 34cdb54c44SPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg)) 35d198b514SPaul Walmsley 36d198b514SPaul Walmsley 37d198b514SPaul Walmsley /* PRM instances */ 38cdb54c44SPaul Walmsley #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000 39cdb54c44SPaul Walmsley #define OMAP4430_PRM_CKGEN_INST 0x0100 40cdb54c44SPaul Walmsley #define OMAP4430_PRM_MPU_INST 0x0300 41cdb54c44SPaul Walmsley #define OMAP4430_PRM_TESLA_INST 0x0400 42cdb54c44SPaul Walmsley #define OMAP4430_PRM_ABE_INST 0x0500 43cdb54c44SPaul Walmsley #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600 44cdb54c44SPaul Walmsley #define OMAP4430_PRM_CORE_INST 0x0700 45cdb54c44SPaul Walmsley #define OMAP4430_PRM_IVAHD_INST 0x0f00 46cdb54c44SPaul Walmsley #define OMAP4430_PRM_CAM_INST 0x1000 47cdb54c44SPaul Walmsley #define OMAP4430_PRM_DSS_INST 0x1100 48cdb54c44SPaul Walmsley #define OMAP4430_PRM_GFX_INST 0x1200 49cdb54c44SPaul Walmsley #define OMAP4430_PRM_L3INIT_INST 0x1300 50cdb54c44SPaul Walmsley #define OMAP4430_PRM_L4PER_INST 0x1400 51cdb54c44SPaul Walmsley #define OMAP4430_PRM_CEFUSE_INST 0x1600 52cdb54c44SPaul Walmsley #define OMAP4430_PRM_WKUP_INST 0x1700 53cdb54c44SPaul Walmsley #define OMAP4430_PRM_WKUP_CM_INST 0x1800 54cdb54c44SPaul Walmsley #define OMAP4430_PRM_EMU_INST 0x1900 55cdb54c44SPaul Walmsley #define OMAP4430_PRM_EMU_CM_INST 0x1a00 56cdb54c44SPaul Walmsley #define OMAP4430_PRM_DEVICE_INST 0x1b00 57cdb54c44SPaul Walmsley #define OMAP4430_PRM_INSTR_INST 0x1f00 58d198b514SPaul Walmsley 59e4156ee5SPaul Walmsley /* PRM clockdomain register offsets (from instance start) */ 60e4156ee5SPaul Walmsley #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 61e4156ee5SPaul Walmsley #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 62d198b514SPaul Walmsley 63d198b514SPaul Walmsley /* OMAP4 specific register offsets */ 64d198b514SPaul Walmsley #define OMAP4_RM_RSTCTRL 0x0000 65d198b514SPaul Walmsley #define OMAP4_RM_RSTTIME 0x0004 66d198b514SPaul Walmsley #define OMAP4_RM_RSTST 0x0008 67d198b514SPaul Walmsley #define OMAP4_PM_PWSTCTRL 0x0000 68d198b514SPaul Walmsley #define OMAP4_PM_PWSTST 0x0004 69d198b514SPaul Walmsley 70c1294045SRajendra Nayak 71c1294045SRajendra Nayak /* PRM */ 72c1294045SRajendra Nayak 73c1294045SRajendra Nayak /* PRM.OCP_SOCKET_PRM register offsets */ 742339ea99SRajendra Nayak #define OMAP4_REVISION_PRM_OFFSET 0x0000 75cdb54c44SPaul Walmsley #define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000) 762339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010 77cdb54c44SPaul Walmsley #define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010) 782339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 79cdb54c44SPaul Walmsley #define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014) 802339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018 81cdb54c44SPaul Walmsley #define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018) 822339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c 83cdb54c44SPaul Walmsley #define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c) 842339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020 85cdb54c44SPaul Walmsley #define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020) 862339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028 87cdb54c44SPaul Walmsley #define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028) 882339ea99SRajendra Nayak #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030 89cdb54c44SPaul Walmsley #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030) 902339ea99SRajendra Nayak #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 91cdb54c44SPaul Walmsley #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038) 92fdd4f409SRajendra Nayak #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 93cdb54c44SPaul Walmsley #define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040) 94c1294045SRajendra Nayak 95c1294045SRajendra Nayak /* PRM.CKGEN_PRM register offsets */ 962339ea99SRajendra Nayak #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 97cdb54c44SPaul Walmsley #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000) 982339ea99SRajendra Nayak #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 99cdb54c44SPaul Walmsley #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008) 1002339ea99SRajendra Nayak #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c 101cdb54c44SPaul Walmsley #define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c) 1022339ea99SRajendra Nayak #define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010 103cdb54c44SPaul Walmsley #define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010) 104c1294045SRajendra Nayak 105c1294045SRajendra Nayak /* PRM.MPU_PRM register offsets */ 1062339ea99SRajendra Nayak #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000 107cdb54c44SPaul Walmsley #define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000) 1082339ea99SRajendra Nayak #define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004 109cdb54c44SPaul Walmsley #define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004) 1102339ea99SRajendra Nayak #define OMAP4_RM_MPU_RSTST_OFFSET 0x0014 111cdb54c44SPaul Walmsley #define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014) 1122339ea99SRajendra Nayak #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 113cdb54c44SPaul Walmsley #define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024) 114c1294045SRajendra Nayak 115c1294045SRajendra Nayak /* PRM.TESLA_PRM register offsets */ 1162339ea99SRajendra Nayak #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000 117cdb54c44SPaul Walmsley #define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000) 1182339ea99SRajendra Nayak #define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004 119cdb54c44SPaul Walmsley #define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004) 1202339ea99SRajendra Nayak #define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010 121cdb54c44SPaul Walmsley #define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010) 1222339ea99SRajendra Nayak #define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014 123cdb54c44SPaul Walmsley #define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014) 1242339ea99SRajendra Nayak #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024 125cdb54c44SPaul Walmsley #define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024) 126c1294045SRajendra Nayak 127c1294045SRajendra Nayak /* PRM.ABE_PRM register offsets */ 1282339ea99SRajendra Nayak #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000 129cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000) 1302339ea99SRajendra Nayak #define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004 131cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004) 1322339ea99SRajendra Nayak #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c 133cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c) 1342339ea99SRajendra Nayak #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030 135cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030) 1362339ea99SRajendra Nayak #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034 137cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034) 1382339ea99SRajendra Nayak #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 139cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038) 1402339ea99SRajendra Nayak #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c 141cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c) 1422339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 143cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040) 1442339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 145cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044) 1462339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 147cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048) 1482339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c 149cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c) 1502339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 151cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050) 1522339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 153cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054) 1542339ea99SRajendra Nayak #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 155cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058) 1562339ea99SRajendra Nayak #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c 157cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c) 1582339ea99SRajendra Nayak #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060 159cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060) 1602339ea99SRajendra Nayak #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064 161cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064) 1622339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 163cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068) 1642339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c 165cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c) 1662339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 167cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070) 1682339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 169cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074) 1702339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 171cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078) 1722339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c 173cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c) 1742339ea99SRajendra Nayak #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 175cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080) 1762339ea99SRajendra Nayak #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 177cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084) 1782339ea99SRajendra Nayak #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088 179cdb54c44SPaul Walmsley #define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088) 1802339ea99SRajendra Nayak #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c 181cdb54c44SPaul Walmsley #define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c) 182c1294045SRajendra Nayak 183c1294045SRajendra Nayak /* PRM.ALWAYS_ON_PRM register offsets */ 1842339ea99SRajendra Nayak #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024 185cdb54c44SPaul Walmsley #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024) 1862339ea99SRajendra Nayak #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028 187cdb54c44SPaul Walmsley #define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028) 1882339ea99SRajendra Nayak #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c 189cdb54c44SPaul Walmsley #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c) 1902339ea99SRajendra Nayak #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030 191cdb54c44SPaul Walmsley #define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030) 1922339ea99SRajendra Nayak #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034 193cdb54c44SPaul Walmsley #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034) 1942339ea99SRajendra Nayak #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038 195cdb54c44SPaul Walmsley #define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038) 1962339ea99SRajendra Nayak #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c 197cdb54c44SPaul Walmsley #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c) 198c1294045SRajendra Nayak 199c1294045SRajendra Nayak /* PRM.CORE_PRM register offsets */ 2002339ea99SRajendra Nayak #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000 201cdb54c44SPaul Walmsley #define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000) 2022339ea99SRajendra Nayak #define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004 203cdb54c44SPaul Walmsley #define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004) 2042339ea99SRajendra Nayak #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024 205cdb54c44SPaul Walmsley #define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024) 2062339ea99SRajendra Nayak #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124 207cdb54c44SPaul Walmsley #define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124) 2082339ea99SRajendra Nayak #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c 209cdb54c44SPaul Walmsley #define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c) 2102339ea99SRajendra Nayak #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134 211cdb54c44SPaul Walmsley #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134) 2122339ea99SRajendra Nayak #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210 213cdb54c44SPaul Walmsley #define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210) 2142339ea99SRajendra Nayak #define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214 215cdb54c44SPaul Walmsley #define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214) 2162339ea99SRajendra Nayak #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224 217cdb54c44SPaul Walmsley #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224) 2182339ea99SRajendra Nayak #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324 219cdb54c44SPaul Walmsley #define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324) 2202339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424 221cdb54c44SPaul Walmsley #define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424) 2222339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c 223cdb54c44SPaul Walmsley #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c) 2242339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434 225cdb54c44SPaul Walmsley #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434) 2262339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c 227cdb54c44SPaul Walmsley #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c) 2282339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444 229cdb54c44SPaul Walmsley #define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444) 2302339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454 231cdb54c44SPaul Walmsley #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454) 2322339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c 233cdb54c44SPaul Walmsley #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c) 2342339ea99SRajendra Nayak #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464 235cdb54c44SPaul Walmsley #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464) 2362339ea99SRajendra Nayak #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 237cdb54c44SPaul Walmsley #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524) 238ad98a18bSBenoit Cousson #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c 239ad98a18bSBenoit Cousson #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c) 2402339ea99SRajendra Nayak #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 241cdb54c44SPaul Walmsley #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534) 2422339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 243cdb54c44SPaul Walmsley #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624) 2442339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c 245cdb54c44SPaul Walmsley #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c) 2462339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 247cdb54c44SPaul Walmsley #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634) 2482339ea99SRajendra Nayak #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c 249cdb54c44SPaul Walmsley #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c) 2502339ea99SRajendra Nayak #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724 251cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724) 2522339ea99SRajendra Nayak #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c 253cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c) 2542339ea99SRajendra Nayak #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744 255cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744) 256c1294045SRajendra Nayak 257c1294045SRajendra Nayak /* PRM.IVAHD_PRM register offsets */ 2582339ea99SRajendra Nayak #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000 259cdb54c44SPaul Walmsley #define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000) 2602339ea99SRajendra Nayak #define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004 261cdb54c44SPaul Walmsley #define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004) 2622339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010 263cdb54c44SPaul Walmsley #define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010) 2642339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014 265cdb54c44SPaul Walmsley #define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014) 2662339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024 267cdb54c44SPaul Walmsley #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024) 2682339ea99SRajendra Nayak #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c 269cdb54c44SPaul Walmsley #define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c) 270c1294045SRajendra Nayak 271c1294045SRajendra Nayak /* PRM.CAM_PRM register offsets */ 2722339ea99SRajendra Nayak #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000 273cdb54c44SPaul Walmsley #define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000) 2742339ea99SRajendra Nayak #define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004 275cdb54c44SPaul Walmsley #define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004) 2762339ea99SRajendra Nayak #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 277cdb54c44SPaul Walmsley #define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024) 2782339ea99SRajendra Nayak #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c 279cdb54c44SPaul Walmsley #define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c) 280c1294045SRajendra Nayak 281c1294045SRajendra Nayak /* PRM.DSS_PRM register offsets */ 2822339ea99SRajendra Nayak #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000 283cdb54c44SPaul Walmsley #define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000) 2842339ea99SRajendra Nayak #define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004 285cdb54c44SPaul Walmsley #define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004) 2862339ea99SRajendra Nayak #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020 287cdb54c44SPaul Walmsley #define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020) 2882339ea99SRajendra Nayak #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 289cdb54c44SPaul Walmsley #define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024) 2902339ea99SRajendra Nayak #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c 291cdb54c44SPaul Walmsley #define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c) 292c1294045SRajendra Nayak 293c1294045SRajendra Nayak /* PRM.GFX_PRM register offsets */ 2942339ea99SRajendra Nayak #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000 295cdb54c44SPaul Walmsley #define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000) 2962339ea99SRajendra Nayak #define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004 297cdb54c44SPaul Walmsley #define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004) 2982339ea99SRajendra Nayak #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024 299cdb54c44SPaul Walmsley #define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024) 300c1294045SRajendra Nayak 301c1294045SRajendra Nayak /* PRM.L3INIT_PRM register offsets */ 3022339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 303cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000) 3042339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004 305cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004) 3062339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 307cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028) 3082339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c 309cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c) 3102339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 311cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030) 3122339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 313cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034) 3142339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 315cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038) 3162339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c 317cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c) 3182339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040 319cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040) 3202339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044 321cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044) 3222339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058 323cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058) 3242339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c 325cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c) 3262339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060 327cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060) 3282339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064 329cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064) 3302339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068 331cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068) 3322339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c 333cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c) 3342339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c 335cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c) 3362339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084 337cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084) 3382339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 339cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088) 3402339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 341cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c) 3422339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094 343cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094) 3442339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098 345cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098) 3462339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c 347cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c) 3482339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac 349cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac) 3502339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0 351cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0) 3522339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4 353cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4) 3542339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8 355cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8) 3562339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc 357cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc) 3582339ea99SRajendra Nayak #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0 359cdb54c44SPaul Walmsley #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0) 3602339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4 361cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4) 3622339ea99SRajendra Nayak #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4 363cdb54c44SPaul Walmsley #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4) 364c1294045SRajendra Nayak 365c1294045SRajendra Nayak /* PRM.L4PER_PRM register offsets */ 3662339ea99SRajendra Nayak #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 367cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000) 3682339ea99SRajendra Nayak #define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004 369cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004) 3702339ea99SRajendra Nayak #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024 371cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024) 3722339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028 373cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028) 3742339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c 375cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c) 3762339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030 377cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030) 3782339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034 379cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034) 3802339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038 381cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038) 3822339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c 383cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c) 3842339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040 385cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040) 3862339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044 387cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044) 3882339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048 389cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048) 3902339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c 391cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c) 3922339ea99SRajendra Nayak #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050 393cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050) 3942339ea99SRajendra Nayak #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054 395cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054) 3962339ea99SRajendra Nayak #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c 397cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c) 3982339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 399cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060) 4002339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 401cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064) 4022339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 403cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068) 4042339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c 405cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c) 4062339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 407cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070) 4082339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 409cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074) 4102339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 411cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078) 4122339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c 413cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c) 4142339ea99SRajendra Nayak #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 415cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080) 4162339ea99SRajendra Nayak #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 417cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084) 4182339ea99SRajendra Nayak #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c 419cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c) 4202339ea99SRajendra Nayak #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090 421cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090) 4222339ea99SRajendra Nayak #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094 423cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094) 4242339ea99SRajendra Nayak #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098 425cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098) 4262339ea99SRajendra Nayak #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c 427cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c) 4282339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 429cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0) 4302339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 431cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4) 4322339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 433cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8) 4342339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac 435cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac) 4362339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 437cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0) 4382339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 439cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4) 4402339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 441cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8) 4422339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc 443cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc) 4442339ea99SRajendra Nayak #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0 445cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0) 4462339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0 447cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0) 4482339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4 449cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4) 4502339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8 451cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8) 4522339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc 453cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc) 4542339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0 455cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0) 4562339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4 457cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4) 4582339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec 459cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec) 4602339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 461cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0) 4622339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 463cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4) 4642339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 465cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8) 4662339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc 467cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc) 4682339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 469cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100) 4702339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 471cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104) 4722339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 473cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108) 4742339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c 475cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c) 4762339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120 477cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120) 4782339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124 479cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124) 4802339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128 481cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128) 4822339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c 483cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c) 4842339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134 485cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134) 4862339ea99SRajendra Nayak #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138 487cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138) 4882339ea99SRajendra Nayak #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c 489cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c) 4902339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 491cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140) 4922339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 493cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144) 4942339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 495cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148) 4962339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c 497cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c) 4982339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 499cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150) 5002339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 501cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154) 5022339ea99SRajendra Nayak #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 503cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158) 5042339ea99SRajendra Nayak #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c 505cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c) 5062339ea99SRajendra Nayak #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160 507cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160) 5082339ea99SRajendra Nayak #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164 509cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164) 5102339ea99SRajendra Nayak #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168 511cdb54c44SPaul Walmsley #define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168) 5122339ea99SRajendra Nayak #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c 513cdb54c44SPaul Walmsley #define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c) 5142339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 515cdb54c44SPaul Walmsley #define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4) 5162339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac 517cdb54c44SPaul Walmsley #define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac) 5182339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 519cdb54c44SPaul Walmsley #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4) 5202339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc 521cdb54c44SPaul Walmsley #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc) 5222339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 523cdb54c44SPaul Walmsley #define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4) 5242339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc 525cdb54c44SPaul Walmsley #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc) 5262339ea99SRajendra Nayak #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc 527cdb54c44SPaul Walmsley #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc) 528c1294045SRajendra Nayak 529c1294045SRajendra Nayak /* PRM.CEFUSE_PRM register offsets */ 5302339ea99SRajendra Nayak #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 531cdb54c44SPaul Walmsley #define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000) 5322339ea99SRajendra Nayak #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004 533cdb54c44SPaul Walmsley #define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004) 5342339ea99SRajendra Nayak #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024 535cdb54c44SPaul Walmsley #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024) 536c1294045SRajendra Nayak 537c1294045SRajendra Nayak /* PRM.WKUP_PRM register offsets */ 5382339ea99SRajendra Nayak #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024 539cdb54c44SPaul Walmsley #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024) 5402339ea99SRajendra Nayak #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c 541cdb54c44SPaul Walmsley #define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c) 5422339ea99SRajendra Nayak #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030 543cdb54c44SPaul Walmsley #define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030) 5442339ea99SRajendra Nayak #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034 545cdb54c44SPaul Walmsley #define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034) 5462339ea99SRajendra Nayak #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038 547cdb54c44SPaul Walmsley #define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038) 5482339ea99SRajendra Nayak #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c 549cdb54c44SPaul Walmsley #define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c) 5502339ea99SRajendra Nayak #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040 551cdb54c44SPaul Walmsley #define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040) 5522339ea99SRajendra Nayak #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044 553cdb54c44SPaul Walmsley #define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044) 5542339ea99SRajendra Nayak #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048 555cdb54c44SPaul Walmsley #define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048) 5562339ea99SRajendra Nayak #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c 557cdb54c44SPaul Walmsley #define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c) 5582339ea99SRajendra Nayak #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054 559cdb54c44SPaul Walmsley #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054) 5602339ea99SRajendra Nayak #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058 561cdb54c44SPaul Walmsley #define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058) 5622339ea99SRajendra Nayak #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c 563cdb54c44SPaul Walmsley #define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c) 5642339ea99SRajendra Nayak #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064 565cdb54c44SPaul Walmsley #define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064) 5662339ea99SRajendra Nayak #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078 567cdb54c44SPaul Walmsley #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078) 5682339ea99SRajendra Nayak #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c 569cdb54c44SPaul Walmsley #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c) 5702339ea99SRajendra Nayak #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080 571cdb54c44SPaul Walmsley #define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080) 5722339ea99SRajendra Nayak #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084 573cdb54c44SPaul Walmsley #define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084) 574c1294045SRajendra Nayak 575c1294045SRajendra Nayak /* PRM.WKUP_CM register offsets */ 5762339ea99SRajendra Nayak #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 577cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000) 5782339ea99SRajendra Nayak #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020 579cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020) 5802339ea99SRajendra Nayak #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028 581cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028) 5822339ea99SRajendra Nayak #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030 583cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030) 5842339ea99SRajendra Nayak #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038 585cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038) 5862339ea99SRajendra Nayak #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040 587cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040) 5882339ea99SRajendra Nayak #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048 589cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048) 5902339ea99SRajendra Nayak #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050 591cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050) 5922339ea99SRajendra Nayak #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058 593cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058) 5942339ea99SRajendra Nayak #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060 595cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060) 5962339ea99SRajendra Nayak #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078 597cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078) 5982339ea99SRajendra Nayak #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080 599cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080) 6002339ea99SRajendra Nayak #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088 601cdb54c44SPaul Walmsley #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088) 602c1294045SRajendra Nayak 603c1294045SRajendra Nayak /* PRM.EMU_PRM register offsets */ 6042339ea99SRajendra Nayak #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000 605cdb54c44SPaul Walmsley #define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000) 6062339ea99SRajendra Nayak #define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004 607cdb54c44SPaul Walmsley #define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004) 6082339ea99SRajendra Nayak #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 609cdb54c44SPaul Walmsley #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024) 610c1294045SRajendra Nayak 611c1294045SRajendra Nayak /* PRM.EMU_CM register offsets */ 6122339ea99SRajendra Nayak #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000 613cdb54c44SPaul Walmsley #define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000) 6142339ea99SRajendra Nayak #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008 615cdb54c44SPaul Walmsley #define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008) 6162339ea99SRajendra Nayak #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 617cdb54c44SPaul Walmsley #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020) 618c1294045SRajendra Nayak 619c1294045SRajendra Nayak /* PRM.DEVICE_PRM register offsets */ 6202339ea99SRajendra Nayak #define OMAP4_PRM_RSTCTRL_OFFSET 0x0000 621cdb54c44SPaul Walmsley #define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000) 6222339ea99SRajendra Nayak #define OMAP4_PRM_RSTST_OFFSET 0x0004 623cdb54c44SPaul Walmsley #define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004) 6242339ea99SRajendra Nayak #define OMAP4_PRM_RSTTIME_OFFSET 0x0008 625cdb54c44SPaul Walmsley #define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008) 6262339ea99SRajendra Nayak #define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c 627cdb54c44SPaul Walmsley #define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c) 6282339ea99SRajendra Nayak #define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010 629cdb54c44SPaul Walmsley #define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010) 6302339ea99SRajendra Nayak #define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014 631cdb54c44SPaul Walmsley #define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014) 6322339ea99SRajendra Nayak #define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018 633cdb54c44SPaul Walmsley #define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018) 6342339ea99SRajendra Nayak #define OMAP4_PRM_IO_COUNT_OFFSET 0x001c 635cdb54c44SPaul Walmsley #define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c) 6362339ea99SRajendra Nayak #define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020 637cdb54c44SPaul Walmsley #define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020) 6382339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 639cdb54c44SPaul Walmsley #define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024) 6402339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 641cdb54c44SPaul Walmsley #define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028) 6422339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c 643cdb54c44SPaul Walmsley #define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c) 6442339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030 645cdb54c44SPaul Walmsley #define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030) 6462339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 647cdb54c44SPaul Walmsley #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034) 6482339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 649cdb54c44SPaul Walmsley #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038) 6502339ea99SRajendra Nayak #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c 651cdb54c44SPaul Walmsley #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c) 6522339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040 653cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040) 6542339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044 655cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044) 6562339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 657cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048) 6582339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c 659cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c) 6602339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 661cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050) 6622339ea99SRajendra Nayak #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 663cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054) 6642339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058 665cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058) 6662339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c 667cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c) 6682339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 669cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060) 6702339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 671cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064) 6722339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 673cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068) 6742339ea99SRajendra Nayak #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c 675cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c) 6762339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070 677cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070) 6782339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074 679cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074) 6802339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078 681cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078) 6822339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c 683cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c) 6842339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080 685cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080) 6862339ea99SRajendra Nayak #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084 687cdb54c44SPaul Walmsley #define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084) 6882339ea99SRajendra Nayak #define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088 689cdb54c44SPaul Walmsley #define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088) 6902339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c 691cdb54c44SPaul Walmsley #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c) 6922339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090 693cdb54c44SPaul Walmsley #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090) 6942339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 695cdb54c44SPaul Walmsley #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094) 6962339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098 697cdb54c44SPaul Walmsley #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098) 6982339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c 699cdb54c44SPaul Walmsley #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c) 7002339ea99SRajendra Nayak #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 701cdb54c44SPaul Walmsley #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0) 7022339ea99SRajendra Nayak #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 703cdb54c44SPaul Walmsley #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4) 704ad98a18bSBenoit Cousson #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8 705ad98a18bSBenoit Cousson #define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8) 7062339ea99SRajendra Nayak #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac 707cdb54c44SPaul Walmsley #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac) 7082339ea99SRajendra Nayak #define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 709cdb54c44SPaul Walmsley #define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0) 7102339ea99SRajendra Nayak #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4 711cdb54c44SPaul Walmsley #define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4) 7122339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8 713cdb54c44SPaul Walmsley #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8) 7142339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc 715cdb54c44SPaul Walmsley #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc) 7162339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0 717cdb54c44SPaul Walmsley #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0) 7182339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4 719cdb54c44SPaul Walmsley #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4) 7202339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8 721cdb54c44SPaul Walmsley #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8) 7222339ea99SRajendra Nayak #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc 723cdb54c44SPaul Walmsley #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc) 7242339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0 725cdb54c44SPaul Walmsley #define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0) 7262339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4 727cdb54c44SPaul Walmsley #define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4) 7282339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8 729cdb54c44SPaul Walmsley #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8) 7302339ea99SRajendra Nayak #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc 731cdb54c44SPaul Walmsley #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc) 732fdd4f409SRajendra Nayak #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 733cdb54c44SPaul Walmsley #define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0) 7342339ea99SRajendra Nayak #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 735cdb54c44SPaul Walmsley #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4) 7362339ea99SRajendra Nayak #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 737cdb54c44SPaul Walmsley #define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8) 7382339ea99SRajendra Nayak #define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec 739cdb54c44SPaul Walmsley #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec) 7402339ea99SRajendra Nayak #define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 741cdb54c44SPaul Walmsley #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0) 742ad98a18bSBenoit Cousson #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 743ad98a18bSBenoit Cousson #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4) 744fdd4f409SRajendra Nayak #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 745cdb54c44SPaul Walmsley #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) 746c1294045SRajendra Nayak 747d198b514SPaul Walmsley /* Function prototypes */ 748d198b514SPaul Walmsley # ifndef __ASSEMBLER__ 749c1294045SRajendra Nayak 7502ace831fSPaul Walmsley extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); 7512ace831fSPaul Walmsley extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx); 7522ace831fSPaul Walmsley extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); 753c1294045SRajendra Nayak 75458aaa599SKevin Hilman /* OMAP4-specific VP functions */ 75558aaa599SKevin Hilman u32 omap4_prm_vp_check_txdone(u8 vp_id); 75658aaa599SKevin Hilman void omap4_prm_vp_clear_txdone(u8 vp_id); 75758aaa599SKevin Hilman 7584bb73adeSKevin Hilman /* 7594bb73adeSKevin Hilman * OMAP4 access functions for voltage controller (VC) and 7604bb73adeSKevin Hilman * voltage proccessor (VP) in the PRM. 7614bb73adeSKevin Hilman */ 7624bb73adeSKevin Hilman extern u32 omap4_prm_vcvp_read(u8 offset); 7634bb73adeSKevin Hilman extern void omap4_prm_vcvp_write(u32 val, u8 offset); 7644bb73adeSKevin Hilman extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 7654bb73adeSKevin Hilman 766dea6200bSRajendra Nayak extern void omap44xx_prm_reconfigure_io_chain(void); 767dea6200bSRajendra Nayak 76826c98c56SPaul Walmsley /* PRM interrupt-related functions */ 76926c98c56SPaul Walmsley extern void omap44xx_prm_read_pending_irqs(unsigned long *events); 77026c98c56SPaul Walmsley extern void omap44xx_prm_ocp_barrier(void); 77191285b6fSTero Kristo extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask); 77291285b6fSTero Kristo extern void omap44xx_prm_restore_irqen(u32 *saved_mask); 77326c98c56SPaul Walmsley 77463a293e0SPaul Walmsley extern int __init omap44xx_prm_init(void); 7752bb2a5d3SPaul Walmsley extern u32 omap44xx_prm_get_reset_sources(void); 7762bb2a5d3SPaul Walmsley 777d198b514SPaul Walmsley # endif 778c1294045SRajendra Nayak 779c1294045SRajendra Nayak #endif 780