1ddd04b98SVaibhav Hiremath /* 2ddd04b98SVaibhav Hiremath * AM33XX PRM functions 3ddd04b98SVaibhav Hiremath * 4ddd04b98SVaibhav Hiremath * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ 5ddd04b98SVaibhav Hiremath * 6ddd04b98SVaibhav Hiremath * This program is free software; you can redistribute it and/or 7ddd04b98SVaibhav Hiremath * modify it under the terms of the GNU General Public License as 8ddd04b98SVaibhav Hiremath * published by the Free Software Foundation version 2. 9ddd04b98SVaibhav Hiremath * 10ddd04b98SVaibhav Hiremath * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11ddd04b98SVaibhav Hiremath * kind, whether express or implied; without even the implied warranty 12ddd04b98SVaibhav Hiremath * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13ddd04b98SVaibhav Hiremath * GNU General Public License for more details. 14ddd04b98SVaibhav Hiremath */ 15ddd04b98SVaibhav Hiremath 16ddd04b98SVaibhav Hiremath #include <linux/kernel.h> 17ddd04b98SVaibhav Hiremath #include <linux/types.h> 18ddd04b98SVaibhav Hiremath #include <linux/errno.h> 19ddd04b98SVaibhav Hiremath #include <linux/err.h> 20ddd04b98SVaibhav Hiremath #include <linux/io.h> 21ddd04b98SVaibhav Hiremath 2249815399SPaul Walmsley #include "powerdomain.h" 23ddd04b98SVaibhav Hiremath #include "prm33xx.h" 24ddd04b98SVaibhav Hiremath #include "prm-regbits-33xx.h" 25ddd04b98SVaibhav Hiremath 26840b7eb8STero Kristo #define AM33XX_PRM_RSTCTRL_OFFSET 0x0000 27840b7eb8STero Kristo 28840b7eb8STero Kristo #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) 29840b7eb8STero Kristo 30ddd04b98SVaibhav Hiremath /* Read a register in a PRM instance */ 31ddd04b98SVaibhav Hiremath u32 am33xx_prm_read_reg(s16 inst, u16 idx) 32ddd04b98SVaibhav Hiremath { 33edfaf05cSVictor Kamensky return readl_relaxed(prm_base + inst + idx); 34ddd04b98SVaibhav Hiremath } 35ddd04b98SVaibhav Hiremath 36ddd04b98SVaibhav Hiremath /* Write into a register in a PRM instance */ 37ddd04b98SVaibhav Hiremath void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) 38ddd04b98SVaibhav Hiremath { 39edfaf05cSVictor Kamensky writel_relaxed(val, prm_base + inst + idx); 40ddd04b98SVaibhav Hiremath } 41ddd04b98SVaibhav Hiremath 42ddd04b98SVaibhav Hiremath /* Read-modify-write a register in PRM. Caller must lock */ 43ddd04b98SVaibhav Hiremath u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) 44ddd04b98SVaibhav Hiremath { 45ddd04b98SVaibhav Hiremath u32 v; 46ddd04b98SVaibhav Hiremath 47ddd04b98SVaibhav Hiremath v = am33xx_prm_read_reg(inst, idx); 48ddd04b98SVaibhav Hiremath v &= ~mask; 49ddd04b98SVaibhav Hiremath v |= bits; 50ddd04b98SVaibhav Hiremath am33xx_prm_write_reg(v, inst, idx); 51ddd04b98SVaibhav Hiremath 52ddd04b98SVaibhav Hiremath return v; 53ddd04b98SVaibhav Hiremath } 54ddd04b98SVaibhav Hiremath 55ddd04b98SVaibhav Hiremath /** 56ddd04b98SVaibhav Hiremath * am33xx_prm_is_hardreset_asserted - read the HW reset line state of 57ddd04b98SVaibhav Hiremath * submodules contained in the hwmod module 58ddd04b98SVaibhav Hiremath * @shift: register bit shift corresponding to the reset line to check 591bc28b34STero Kristo * @part: PRM partition, ignored for AM33xx 60ddd04b98SVaibhav Hiremath * @inst: CM instance register offset (*_INST macro) 61ddd04b98SVaibhav Hiremath * @rstctrl_offs: RM_RSTCTRL register address offset for this module 62ddd04b98SVaibhav Hiremath * 63ddd04b98SVaibhav Hiremath * Returns 1 if the (sub)module hardreset line is currently asserted, 64ddd04b98SVaibhav Hiremath * 0 if the (sub)module hardreset line is not currently asserted, or 65ddd04b98SVaibhav Hiremath * -EINVAL upon parameter error. 66ddd04b98SVaibhav Hiremath */ 671bc28b34STero Kristo static int am33xx_prm_is_hardreset_asserted(u8 shift, u8 part, s16 inst, 681bc28b34STero Kristo u16 rstctrl_offs) 69ddd04b98SVaibhav Hiremath { 70ddd04b98SVaibhav Hiremath u32 v; 71ddd04b98SVaibhav Hiremath 72ddd04b98SVaibhav Hiremath v = am33xx_prm_read_reg(inst, rstctrl_offs); 73ddd04b98SVaibhav Hiremath v &= 1 << shift; 74ddd04b98SVaibhav Hiremath v >>= shift; 75ddd04b98SVaibhav Hiremath 76ddd04b98SVaibhav Hiremath return v; 77ddd04b98SVaibhav Hiremath } 78ddd04b98SVaibhav Hiremath 79ddd04b98SVaibhav Hiremath /** 80ddd04b98SVaibhav Hiremath * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule 81ddd04b98SVaibhav Hiremath * @shift: register bit shift corresponding to the reset line to assert 82efd44dc3STero Kristo * @part: CM partition, ignored for AM33xx 83ddd04b98SVaibhav Hiremath * @inst: CM instance register offset (*_INST macro) 84ddd04b98SVaibhav Hiremath * @rstctrl_reg: RM_RSTCTRL register address for this module 85ddd04b98SVaibhav Hiremath * 86ddd04b98SVaibhav Hiremath * Some IPs like dsp, ipu or iva contain processors that require an HW 87ddd04b98SVaibhav Hiremath * reset line to be asserted / deasserted in order to fully enable the 88ddd04b98SVaibhav Hiremath * IP. These modules may have multiple hard-reset lines that reset 89ddd04b98SVaibhav Hiremath * different 'submodules' inside the IP block. This function will 90ddd04b98SVaibhav Hiremath * place the submodule into reset. Returns 0 upon success or -EINVAL 91ddd04b98SVaibhav Hiremath * upon an argument error. 92ddd04b98SVaibhav Hiremath */ 93efd44dc3STero Kristo static int am33xx_prm_assert_hardreset(u8 shift, u8 part, s16 inst, 94efd44dc3STero Kristo u16 rstctrl_offs) 95ddd04b98SVaibhav Hiremath { 96ddd04b98SVaibhav Hiremath u32 mask = 1 << shift; 97ddd04b98SVaibhav Hiremath 98ddd04b98SVaibhav Hiremath am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs); 99ddd04b98SVaibhav Hiremath 100ddd04b98SVaibhav Hiremath return 0; 101ddd04b98SVaibhav Hiremath } 102ddd04b98SVaibhav Hiremath 103ddd04b98SVaibhav Hiremath /** 104ddd04b98SVaibhav Hiremath * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and 105ddd04b98SVaibhav Hiremath * wait 106ddd04b98SVaibhav Hiremath * @shift: register bit shift corresponding to the reset line to deassert 10737fb59d7STero Kristo * @st_shift: reset status register bit shift corresponding to the reset line 10837fb59d7STero Kristo * @part: PRM partition, not used for AM33xx 109ddd04b98SVaibhav Hiremath * @inst: CM instance register offset (*_INST macro) 110ddd04b98SVaibhav Hiremath * @rstctrl_reg: RM_RSTCTRL register address for this module 111ddd04b98SVaibhav Hiremath * @rstst_reg: RM_RSTST register address for this module 112ddd04b98SVaibhav Hiremath * 113ddd04b98SVaibhav Hiremath * Some IPs like dsp, ipu or iva contain processors that require an HW 114ddd04b98SVaibhav Hiremath * reset line to be asserted / deasserted in order to fully enable the 115ddd04b98SVaibhav Hiremath * IP. These modules may have multiple hard-reset lines that reset 116ddd04b98SVaibhav Hiremath * different 'submodules' inside the IP block. This function will 117ddd04b98SVaibhav Hiremath * take the submodule out of reset and wait until the PRCM indicates 118ddd04b98SVaibhav Hiremath * that the reset has completed before returning. Returns 0 upon success or 119ddd04b98SVaibhav Hiremath * -EINVAL upon an argument error, -EEXIST if the submodule was already out 120ddd04b98SVaibhav Hiremath * of reset, or -EBUSY if the submodule did not exit reset promptly. 121ddd04b98SVaibhav Hiremath */ 12237fb59d7STero Kristo static int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, 12337fb59d7STero Kristo s16 inst, u16 rstctrl_offs, 12437fb59d7STero Kristo u16 rstst_offs) 125ddd04b98SVaibhav Hiremath { 126ddd04b98SVaibhav Hiremath int c; 1273c06f1b8SVaibhav Bedia u32 mask = 1 << st_shift; 128ddd04b98SVaibhav Hiremath 129ddd04b98SVaibhav Hiremath /* Check the current status to avoid de-asserting the line twice */ 1301bc28b34STero Kristo if (am33xx_prm_is_hardreset_asserted(shift, 0, inst, rstctrl_offs) == 0) 131ddd04b98SVaibhav Hiremath return -EEXIST; 132ddd04b98SVaibhav Hiremath 133ddd04b98SVaibhav Hiremath /* Clear the reset status by writing 1 to the status bit */ 134ddd04b98SVaibhav Hiremath am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs); 135ddd04b98SVaibhav Hiremath 1363c06f1b8SVaibhav Bedia /* de-assert the reset control line */ 1373c06f1b8SVaibhav Bedia mask = 1 << shift; 1383c06f1b8SVaibhav Bedia 1393c06f1b8SVaibhav Bedia am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs); 1403c06f1b8SVaibhav Bedia 1413c06f1b8SVaibhav Bedia /* wait the status to be set */ 1421bc28b34STero Kristo omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, 0, inst, 143ddd04b98SVaibhav Hiremath rstst_offs), 144ddd04b98SVaibhav Hiremath MAX_MODULE_HARDRESET_WAIT, c); 145ddd04b98SVaibhav Hiremath 146ddd04b98SVaibhav Hiremath return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; 147ddd04b98SVaibhav Hiremath } 14849815399SPaul Walmsley 14949815399SPaul Walmsley static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) 15049815399SPaul Walmsley { 15149815399SPaul Walmsley am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK, 15249815399SPaul Walmsley (pwrst << OMAP_POWERSTATE_SHIFT), 15349815399SPaul Walmsley pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 15449815399SPaul Walmsley return 0; 15549815399SPaul Walmsley } 15649815399SPaul Walmsley 15749815399SPaul Walmsley static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) 15849815399SPaul Walmsley { 15949815399SPaul Walmsley u32 v; 16049815399SPaul Walmsley 16149815399SPaul Walmsley v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 16249815399SPaul Walmsley v &= OMAP_POWERSTATE_MASK; 16349815399SPaul Walmsley v >>= OMAP_POWERSTATE_SHIFT; 16449815399SPaul Walmsley 16549815399SPaul Walmsley return v; 16649815399SPaul Walmsley } 16749815399SPaul Walmsley 16849815399SPaul Walmsley static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) 16949815399SPaul Walmsley { 17049815399SPaul Walmsley u32 v; 17149815399SPaul Walmsley 17249815399SPaul Walmsley v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); 17349815399SPaul Walmsley v &= OMAP_POWERSTATEST_MASK; 17449815399SPaul Walmsley v >>= OMAP_POWERSTATEST_SHIFT; 17549815399SPaul Walmsley 17649815399SPaul Walmsley return v; 17749815399SPaul Walmsley } 17849815399SPaul Walmsley 17949815399SPaul Walmsley static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) 18049815399SPaul Walmsley { 18149815399SPaul Walmsley u32 v; 18249815399SPaul Walmsley 18349815399SPaul Walmsley v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); 18449815399SPaul Walmsley v &= AM33XX_LASTPOWERSTATEENTERED_MASK; 18549815399SPaul Walmsley v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT; 18649815399SPaul Walmsley 18749815399SPaul Walmsley return v; 18849815399SPaul Walmsley } 18949815399SPaul Walmsley 19049815399SPaul Walmsley static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) 19149815399SPaul Walmsley { 19249815399SPaul Walmsley am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, 19349815399SPaul Walmsley (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT), 19449815399SPaul Walmsley pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 19549815399SPaul Walmsley return 0; 19649815399SPaul Walmsley } 19749815399SPaul Walmsley 19849815399SPaul Walmsley static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) 19949815399SPaul Walmsley { 20049815399SPaul Walmsley am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK, 20149815399SPaul Walmsley AM33XX_LASTPOWERSTATEENTERED_MASK, 20249815399SPaul Walmsley pwrdm->prcm_offs, pwrdm->pwrstst_offs); 20349815399SPaul Walmsley return 0; 20449815399SPaul Walmsley } 20549815399SPaul Walmsley 20649815399SPaul Walmsley static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) 20749815399SPaul Walmsley { 20849815399SPaul Walmsley u32 m; 20949815399SPaul Walmsley 21049815399SPaul Walmsley m = pwrdm->logicretstate_mask; 21149815399SPaul Walmsley if (!m) 21249815399SPaul Walmsley return -EINVAL; 21349815399SPaul Walmsley 21449815399SPaul Walmsley am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), 21549815399SPaul Walmsley pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 21649815399SPaul Walmsley 21749815399SPaul Walmsley return 0; 21849815399SPaul Walmsley } 21949815399SPaul Walmsley 22049815399SPaul Walmsley static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) 22149815399SPaul Walmsley { 22249815399SPaul Walmsley u32 v; 22349815399SPaul Walmsley 22449815399SPaul Walmsley v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); 22549815399SPaul Walmsley v &= AM33XX_LOGICSTATEST_MASK; 22649815399SPaul Walmsley v >>= AM33XX_LOGICSTATEST_SHIFT; 22749815399SPaul Walmsley 22849815399SPaul Walmsley return v; 22949815399SPaul Walmsley } 23049815399SPaul Walmsley 23149815399SPaul Walmsley static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) 23249815399SPaul Walmsley { 23349815399SPaul Walmsley u32 v, m; 23449815399SPaul Walmsley 23549815399SPaul Walmsley m = pwrdm->logicretstate_mask; 23649815399SPaul Walmsley if (!m) 23749815399SPaul Walmsley return -EINVAL; 23849815399SPaul Walmsley 23949815399SPaul Walmsley v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 24049815399SPaul Walmsley v &= m; 24149815399SPaul Walmsley v >>= __ffs(m); 24249815399SPaul Walmsley 24349815399SPaul Walmsley return v; 24449815399SPaul Walmsley } 24549815399SPaul Walmsley 24649815399SPaul Walmsley static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, 24749815399SPaul Walmsley u8 pwrst) 24849815399SPaul Walmsley { 24949815399SPaul Walmsley u32 m; 25049815399SPaul Walmsley 25149815399SPaul Walmsley m = pwrdm->mem_on_mask[bank]; 25249815399SPaul Walmsley if (!m) 25349815399SPaul Walmsley return -EINVAL; 25449815399SPaul Walmsley 25549815399SPaul Walmsley am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), 25649815399SPaul Walmsley pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 25749815399SPaul Walmsley 25849815399SPaul Walmsley return 0; 25949815399SPaul Walmsley } 26049815399SPaul Walmsley 26149815399SPaul Walmsley static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, 26249815399SPaul Walmsley u8 pwrst) 26349815399SPaul Walmsley { 26449815399SPaul Walmsley u32 m; 26549815399SPaul Walmsley 26649815399SPaul Walmsley m = pwrdm->mem_ret_mask[bank]; 26749815399SPaul Walmsley if (!m) 26849815399SPaul Walmsley return -EINVAL; 26949815399SPaul Walmsley 27049815399SPaul Walmsley am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), 27149815399SPaul Walmsley pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 27249815399SPaul Walmsley 27349815399SPaul Walmsley return 0; 27449815399SPaul Walmsley } 27549815399SPaul Walmsley 27649815399SPaul Walmsley static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) 27749815399SPaul Walmsley { 27849815399SPaul Walmsley u32 m, v; 27949815399SPaul Walmsley 28049815399SPaul Walmsley m = pwrdm->mem_pwrst_mask[bank]; 28149815399SPaul Walmsley if (!m) 28249815399SPaul Walmsley return -EINVAL; 28349815399SPaul Walmsley 28449815399SPaul Walmsley v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); 28549815399SPaul Walmsley v &= m; 28649815399SPaul Walmsley v >>= __ffs(m); 28749815399SPaul Walmsley 28849815399SPaul Walmsley return v; 28949815399SPaul Walmsley } 29049815399SPaul Walmsley 29149815399SPaul Walmsley static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) 29249815399SPaul Walmsley { 29349815399SPaul Walmsley u32 m, v; 29449815399SPaul Walmsley 29549815399SPaul Walmsley m = pwrdm->mem_retst_mask[bank]; 29649815399SPaul Walmsley if (!m) 29749815399SPaul Walmsley return -EINVAL; 29849815399SPaul Walmsley 29949815399SPaul Walmsley v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 30049815399SPaul Walmsley v &= m; 30149815399SPaul Walmsley v >>= __ffs(m); 30249815399SPaul Walmsley 30349815399SPaul Walmsley return v; 30449815399SPaul Walmsley } 30549815399SPaul Walmsley 30649815399SPaul Walmsley static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) 30749815399SPaul Walmsley { 30849815399SPaul Walmsley u32 c = 0; 30949815399SPaul Walmsley 31049815399SPaul Walmsley /* 31149815399SPaul Walmsley * REVISIT: pwrdm_wait_transition() may be better implemented 31249815399SPaul Walmsley * via a callback and a periodic timer check -- how long do we expect 31349815399SPaul Walmsley * powerdomain transitions to take? 31449815399SPaul Walmsley */ 31549815399SPaul Walmsley 31649815399SPaul Walmsley /* XXX Is this udelay() value meaningful? */ 31749815399SPaul Walmsley while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs) 31849815399SPaul Walmsley & OMAP_INTRANSITION_MASK) && 31949815399SPaul Walmsley (c++ < PWRDM_TRANSITION_BAILOUT)) 32049815399SPaul Walmsley udelay(1); 32149815399SPaul Walmsley 32249815399SPaul Walmsley if (c > PWRDM_TRANSITION_BAILOUT) { 32349815399SPaul Walmsley pr_err("powerdomain: %s: waited too long to complete transition\n", 32449815399SPaul Walmsley pwrdm->name); 32549815399SPaul Walmsley return -EAGAIN; 32649815399SPaul Walmsley } 32749815399SPaul Walmsley 32849815399SPaul Walmsley pr_debug("powerdomain: completed transition in %d loops\n", c); 32949815399SPaul Walmsley 33049815399SPaul Walmsley return 0; 33149815399SPaul Walmsley } 33249815399SPaul Walmsley 33363b0420cSRajendra Nayak static int am33xx_check_vcvp(void) 33463b0420cSRajendra Nayak { 33563b0420cSRajendra Nayak /* No VC/VP on am33xx devices */ 33663b0420cSRajendra Nayak return 0; 33763b0420cSRajendra Nayak } 33863b0420cSRajendra Nayak 339840b7eb8STero Kristo /** 340840b7eb8STero Kristo * am33xx_prm_global_warm_sw_reset - reboot the device via warm reset 341840b7eb8STero Kristo * 342840b7eb8STero Kristo * Immediately reboots the device through warm reset. 343840b7eb8STero Kristo */ 344840b7eb8STero Kristo void am33xx_prm_global_warm_sw_reset(void) 345840b7eb8STero Kristo { 346840b7eb8STero Kristo am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK, 347840b7eb8STero Kristo AM33XX_RST_GLOBAL_WARM_SW_MASK, 348840b7eb8STero Kristo AM33XX_PRM_DEVICE_MOD, 349840b7eb8STero Kristo AM33XX_PRM_RSTCTRL_OFFSET); 350840b7eb8STero Kristo 351840b7eb8STero Kristo /* OCP barrier */ 352840b7eb8STero Kristo (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD, 353840b7eb8STero Kristo AM33XX_PRM_RSTCTRL_OFFSET); 354840b7eb8STero Kristo } 355840b7eb8STero Kristo 35649815399SPaul Walmsley struct pwrdm_ops am33xx_pwrdm_operations = { 35749815399SPaul Walmsley .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, 35849815399SPaul Walmsley .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, 35949815399SPaul Walmsley .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst, 36049815399SPaul Walmsley .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst, 36149815399SPaul Walmsley .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst, 36249815399SPaul Walmsley .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst, 36349815399SPaul Walmsley .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst, 36449815399SPaul Walmsley .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst, 36549815399SPaul Walmsley .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange, 36649815399SPaul Walmsley .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst, 36749815399SPaul Walmsley .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst, 36849815399SPaul Walmsley .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, 36949815399SPaul Walmsley .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, 37049815399SPaul Walmsley .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, 37163b0420cSRajendra Nayak .pwrdm_has_voltdm = am33xx_check_vcvp, 37249815399SPaul Walmsley }; 373d9bbe84fSTero Kristo 374efd44dc3STero Kristo static struct prm_ll_data am33xx_prm_ll_data = { 375efd44dc3STero Kristo .assert_hardreset = am33xx_prm_assert_hardreset, 37637fb59d7STero Kristo .deassert_hardreset = am33xx_prm_deassert_hardreset, 3771bc28b34STero Kristo .is_hardreset_asserted = am33xx_prm_is_hardreset_asserted, 378efd44dc3STero Kristo }; 379d9bbe84fSTero Kristo 380d9bbe84fSTero Kristo int __init am33xx_prm_init(void) 381d9bbe84fSTero Kristo { 382d9bbe84fSTero Kristo return prm_register(&am33xx_prm_ll_data); 383d9bbe84fSTero Kristo } 384d9bbe84fSTero Kristo 385d9bbe84fSTero Kristo static void __exit am33xx_prm_exit(void) 386d9bbe84fSTero Kristo { 387d9bbe84fSTero Kristo prm_unregister(&am33xx_prm_ll_data); 388d9bbe84fSTero Kristo } 389d9bbe84fSTero Kristo __exitcall(am33xx_prm_exit); 390