1 /* 2 * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions 3 * 4 * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc. 5 * Copyright (C) 2008-2010 Nokia Corporation 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * The PRM hardware modules on the OMAP2/3 are quite similar to each 13 * other. The PRM on OMAP4 has a new register layout, and is handled 14 * in a separate file. 15 */ 16 #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H 17 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H 18 19 #include "prcm-common.h" 20 #include "prm.h" 21 22 /* 23 * Module specific PRM register offsets from PRM_BASE + domain offset 24 * 25 * Use prm_{read,write}_mod_reg() with these registers. 26 * 27 * With a few exceptions, these are the register names beginning with 28 * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the 29 * IRQSTATUS and IRQENABLE bits.) 30 */ 31 32 /* Register offsets appearing on both OMAP2 and OMAP3 */ 33 34 #define OMAP2_RM_RSTCTRL 0x0050 35 #define OMAP2_RM_RSTTIME 0x0054 36 #define OMAP2_RM_RSTST 0x0058 37 #define OMAP2_PM_PWSTCTRL 0x00e0 38 #define OMAP2_PM_PWSTST 0x00e4 39 40 #define PM_WKEN 0x00a0 41 #define PM_WKEN1 PM_WKEN 42 #define PM_WKST 0x00b0 43 #define PM_WKST1 PM_WKST 44 #define PM_WKDEP 0x00c8 45 #define PM_EVGENCTRL 0x00d4 46 #define PM_EVGENONTIM 0x00d8 47 #define PM_EVGENOFFTIM 0x00dc 48 49 50 #ifndef __ASSEMBLER__ 51 52 #include <linux/io.h> 53 #include "powerdomain.h" 54 55 /* Power/reset management domain register get/set */ 56 static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) 57 { 58 return readl_relaxed(prm_base + module + idx); 59 } 60 61 static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) 62 { 63 writel_relaxed(val, prm_base + module + idx); 64 } 65 66 /* Read-modify-write a register in a PRM module. Caller must lock */ 67 static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, 68 s16 idx) 69 { 70 u32 v; 71 72 v = omap2_prm_read_mod_reg(module, idx); 73 v &= ~mask; 74 v |= bits; 75 omap2_prm_write_mod_reg(v, module, idx); 76 77 return v; 78 } 79 80 /* Read a PRM register, AND it, and shift the result down to bit 0 */ 81 static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) 82 { 83 u32 v; 84 85 v = omap2_prm_read_mod_reg(domain, idx); 86 v &= mask; 87 v >>= __ffs(mask); 88 89 return v; 90 } 91 92 static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) 93 { 94 return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx); 95 } 96 97 static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) 98 { 99 return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx); 100 } 101 102 /* These omap2_ PRM functions apply to both OMAP2 and 3 */ 103 int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset); 104 int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, 105 u16 offset); 106 int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part, 107 s16 prm_mod, u16 reset_offset, 108 u16 st_offset); 109 110 extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); 111 extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm); 112 extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm); 113 extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, 114 u8 pwrst); 115 extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, 116 u8 pwrst); 117 extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); 118 extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); 119 extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); 120 extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm); 121 122 extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1, 123 struct clockdomain *clkdm2); 124 extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1, 125 struct clockdomain *clkdm2); 126 extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1, 127 struct clockdomain *clkdm2); 128 extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm); 129 130 #endif /* __ASSEMBLER */ 131 132 /* 133 * Bits common to specific registers 134 * 135 * The 3430 register and bit names are generally used, 136 * since they tend to make more sense 137 */ 138 139 /* PM_EVGENONTIM_MPU */ 140 /* Named PM_EVEGENONTIM_MPU on the 24XX */ 141 #define OMAP_ONTIMEVAL_SHIFT 0 142 #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) 143 144 /* PM_EVGENOFFTIM_MPU */ 145 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */ 146 #define OMAP_OFFTIMEVAL_SHIFT 0 147 #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) 148 149 /* PRM_CLKSETUP and PRCM_VOLTSETUP */ 150 /* Named PRCM_CLKSSETUP on the 24XX */ 151 #define OMAP_SETUP_TIME_SHIFT 0 152 #define OMAP_SETUP_TIME_MASK (0xffff << 0) 153 154 /* PRM_CLKSRC_CTRL */ 155 /* Named PRCM_CLKSRC_CTRL on the 24XX */ 156 #define OMAP_SYSCLKDIV_SHIFT 6 157 #define OMAP_SYSCLKDIV_MASK (0x3 << 6) 158 #define OMAP_SYSCLKDIV_WIDTH 2 159 #define OMAP_AUTOEXTCLKMODE_SHIFT 3 160 #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) 161 #define OMAP_SYSCLKSEL_SHIFT 0 162 #define OMAP_SYSCLKSEL_MASK (0x3 << 0) 163 164 /* PM_EVGENCTRL_MPU */ 165 #define OMAP_OFFLOADMODE_SHIFT 3 166 #define OMAP_OFFLOADMODE_MASK (0x3 << 3) 167 #define OMAP_ONLOADMODE_SHIFT 1 168 #define OMAP_ONLOADMODE_MASK (0x3 << 1) 169 #define OMAP_ENABLE_MASK (1 << 0) 170 171 /* PRM_RSTTIME */ 172 /* Named RM_RSTTIME_WKUP on the 24xx */ 173 #define OMAP_RSTTIME2_SHIFT 8 174 #define OMAP_RSTTIME2_MASK (0x1f << 8) 175 #define OMAP_RSTTIME1_SHIFT 0 176 #define OMAP_RSTTIME1_MASK (0xff << 0) 177 178 /* PRM_RSTCTRL */ 179 /* Named RM_RSTCTRL_WKUP on the 24xx */ 180 /* 2420 calls RST_DPLL3 'RST_DPLL' */ 181 #define OMAP_RST_DPLL3_MASK (1 << 2) 182 #define OMAP_RST_GS_MASK (1 << 1) 183 184 185 /* 186 * Bits common to module-shared registers 187 * 188 * Not all registers of a particular type support all of these bits - 189 * check TRM if you are unsure 190 */ 191 192 /* 193 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is 194 * called 'COREWKUP_RST' 195 * 196 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, 197 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON 198 */ 199 #define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3) 200 201 /* 202 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP 203 * 204 * 2430: RM_RSTST_MDM 205 * 206 * 3430: RM_RSTST_CORE, RM_RSTST_EMU 207 */ 208 #define OMAP_DOMAINWKUP_RST_MASK (1 << 2) 209 210 /* 211 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP 212 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. 213 * 214 * 2430: RM_RSTST_MDM 215 * 216 * 3430: RM_RSTST_CORE, RM_RSTST_EMU 217 */ 218 #define OMAP_GLOBALWARM_RST_SHIFT 1 219 #define OMAP_GLOBALWARM_RST_MASK (1 << 1) 220 #define OMAP_GLOBALCOLD_RST_SHIFT 0 221 #define OMAP_GLOBALCOLD_RST_MASK (1 << 0) 222 223 /* 224 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP 225 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" 226 * 227 * 2430: PM_WKDEP_MDM 228 * 229 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, 230 * PM_WKDEP_PER 231 */ 232 #define OMAP_EN_WKUP_SHIFT 4 233 #define OMAP_EN_WKUP_MASK (1 << 4) 234 235 /* 236 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 237 * PM_PWSTCTRL_DSP 238 * 239 * 2430: PM_PWSTCTRL_MDM 240 * 241 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 242 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, 243 * PM_PWSTCTRL_NEON 244 */ 245 #define OMAP_LOGICRETSTATE_MASK (1 << 2) 246 247 248 #endif 249