1 /* 2 * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions 3 * 4 * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc. 5 * Copyright (C) 2008-2010 Nokia Corporation 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * The PRM hardware modules on the OMAP2/3 are quite similar to each 13 * other. The PRM on OMAP4 has a new register layout, and is handled 14 * in a separate file. 15 */ 16 #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H 17 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H 18 19 #include "prcm-common.h" 20 #include "prm.h" 21 22 /* 23 * Module specific PRM register offsets from PRM_BASE + domain offset 24 * 25 * Use prm_{read,write}_mod_reg() with these registers. 26 * 27 * With a few exceptions, these are the register names beginning with 28 * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the 29 * IRQSTATUS and IRQENABLE bits.) 30 */ 31 32 /* Register offsets appearing on both OMAP2 and OMAP3 */ 33 34 #define OMAP2_RM_RSTCTRL 0x0050 35 #define OMAP2_RM_RSTTIME 0x0054 36 #define OMAP2_RM_RSTST 0x0058 37 #define OMAP2_PM_PWSTCTRL 0x00e0 38 #define OMAP2_PM_PWSTST 0x00e4 39 40 #define PM_WKEN 0x00a0 41 #define PM_WKEN1 PM_WKEN 42 #define PM_WKST 0x00b0 43 #define PM_WKST1 PM_WKST 44 #define PM_WKDEP 0x00c8 45 #define PM_EVGENCTRL 0x00d4 46 #define PM_EVGENONTIM 0x00d8 47 #define PM_EVGENOFFTIM 0x00dc 48 49 50 #ifndef __ASSEMBLER__ 51 52 #include <linux/io.h> 53 54 /* Power/reset management domain register get/set */ 55 static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) 56 { 57 return __raw_readl(prm_base + module + idx); 58 } 59 60 static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) 61 { 62 __raw_writel(val, prm_base + module + idx); 63 } 64 65 /* Read-modify-write a register in a PRM module. Caller must lock */ 66 static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, 67 s16 idx) 68 { 69 u32 v; 70 71 v = omap2_prm_read_mod_reg(module, idx); 72 v &= ~mask; 73 v |= bits; 74 omap2_prm_write_mod_reg(v, module, idx); 75 76 return v; 77 } 78 79 /* Read a PRM register, AND it, and shift the result down to bit 0 */ 80 static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) 81 { 82 u32 v; 83 84 v = omap2_prm_read_mod_reg(domain, idx); 85 v &= mask; 86 v >>= __ffs(mask); 87 88 return v; 89 } 90 91 static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) 92 { 93 return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx); 94 } 95 96 static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) 97 { 98 return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx); 99 } 100 101 /* These omap2_ PRM functions apply to both OMAP2 and 3 */ 102 extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); 103 extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); 104 extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift); 105 106 #endif /* __ASSEMBLER */ 107 108 /* 109 * Bits common to specific registers 110 * 111 * The 3430 register and bit names are generally used, 112 * since they tend to make more sense 113 */ 114 115 /* PM_EVGENONTIM_MPU */ 116 /* Named PM_EVEGENONTIM_MPU on the 24XX */ 117 #define OMAP_ONTIMEVAL_SHIFT 0 118 #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) 119 120 /* PM_EVGENOFFTIM_MPU */ 121 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */ 122 #define OMAP_OFFTIMEVAL_SHIFT 0 123 #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) 124 125 /* PRM_CLKSETUP and PRCM_VOLTSETUP */ 126 /* Named PRCM_CLKSSETUP on the 24XX */ 127 #define OMAP_SETUP_TIME_SHIFT 0 128 #define OMAP_SETUP_TIME_MASK (0xffff << 0) 129 130 /* PRM_CLKSRC_CTRL */ 131 /* Named PRCM_CLKSRC_CTRL on the 24XX */ 132 #define OMAP_SYSCLKDIV_SHIFT 6 133 #define OMAP_SYSCLKDIV_MASK (0x3 << 6) 134 #define OMAP_AUTOEXTCLKMODE_SHIFT 3 135 #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) 136 #define OMAP_SYSCLKSEL_SHIFT 0 137 #define OMAP_SYSCLKSEL_MASK (0x3 << 0) 138 139 /* PM_EVGENCTRL_MPU */ 140 #define OMAP_OFFLOADMODE_SHIFT 3 141 #define OMAP_OFFLOADMODE_MASK (0x3 << 3) 142 #define OMAP_ONLOADMODE_SHIFT 1 143 #define OMAP_ONLOADMODE_MASK (0x3 << 1) 144 #define OMAP_ENABLE_MASK (1 << 0) 145 146 /* PRM_RSTTIME */ 147 /* Named RM_RSTTIME_WKUP on the 24xx */ 148 #define OMAP_RSTTIME2_SHIFT 8 149 #define OMAP_RSTTIME2_MASK (0x1f << 8) 150 #define OMAP_RSTTIME1_SHIFT 0 151 #define OMAP_RSTTIME1_MASK (0xff << 0) 152 153 /* PRM_RSTCTRL */ 154 /* Named RM_RSTCTRL_WKUP on the 24xx */ 155 /* 2420 calls RST_DPLL3 'RST_DPLL' */ 156 #define OMAP_RST_DPLL3_MASK (1 << 2) 157 #define OMAP_RST_GS_MASK (1 << 1) 158 159 160 /* 161 * Bits common to module-shared registers 162 * 163 * Not all registers of a particular type support all of these bits - 164 * check TRM if you are unsure 165 */ 166 167 /* 168 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is 169 * called 'COREWKUP_RST' 170 * 171 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, 172 * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON 173 */ 174 #define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3) 175 176 /* 177 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP 178 * 179 * 2430: RM_RSTST_MDM 180 * 181 * 3430: RM_RSTST_CORE, RM_RSTST_EMU 182 */ 183 #define OMAP_DOMAINWKUP_RST_MASK (1 << 2) 184 185 /* 186 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP 187 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. 188 * 189 * 2430: RM_RSTST_MDM 190 * 191 * 3430: RM_RSTST_CORE, RM_RSTST_EMU 192 */ 193 #define OMAP_GLOBALWARM_RST_MASK (1 << 1) 194 #define OMAP_GLOBALCOLD_RST_MASK (1 << 0) 195 196 /* 197 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP 198 * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" 199 * 200 * 2430: PM_WKDEP_MDM 201 * 202 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, 203 * PM_WKDEP_PER 204 */ 205 #define OMAP_EN_WKUP_SHIFT 4 206 #define OMAP_EN_WKUP_MASK (1 << 4) 207 208 /* 209 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 210 * PM_PWSTCTRL_DSP 211 * 212 * 2430: PM_PWSTCTRL_MDM 213 * 214 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 215 * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, 216 * PM_PWSTCTRL_NEON 217 */ 218 #define OMAP_LOGICRETSTATE_MASK (1 << 2) 219 220 221 /* 222 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP 223 * submodule to exit hardreset 224 */ 225 #define MAX_MODULE_HARDRESET_WAIT 10000 226 227 228 #endif 229