1 /* 2 * OMAP2xxx Power/Reset Management (PRM) register definitions 3 * 4 * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc. 5 * Copyright (C) 2008-2010 Nokia Corporation 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * The PRM hardware modules on the OMAP2/3 are quite similar to each 13 * other. The PRM on OMAP4 has a new register layout, and is handled 14 * in a separate file. 15 */ 16 #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H 17 #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H 18 19 #include "prcm-common.h" 20 #include "prm.h" 21 #include "prm2xxx_3xxx.h" 22 23 #define OMAP2420_PRM_REGADDR(module, reg) \ 24 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) 25 #define OMAP2430_PRM_REGADDR(module, reg) \ 26 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) 27 28 /* 29 * OMAP2-specific global PRM registers 30 * Use {read,write}l_relaxed() with these registers. 31 * 32 * With a few exceptions, these are the register names beginning with 33 * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE 34 * bits.) 35 * 36 */ 37 38 #define OMAP2_PRCM_REVISION_OFFSET 0x0000 39 #define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) 40 #define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 41 #define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) 42 43 #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 44 #define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) 45 #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c 46 #define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) 47 48 #define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 49 #define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) 50 #define OMAP2_PRCM_VOLTST_OFFSET 0x0054 51 #define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) 52 #define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 53 #define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) 54 #define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 55 #define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) 56 #define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 57 #define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) 58 #define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 59 #define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) 60 #define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 61 #define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) 62 #define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 63 #define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) 64 #define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 65 #define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) 66 #define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 67 #define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) 68 69 #define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) 70 #define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) 71 72 #define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) 73 #define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) 74 75 #define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) 76 #define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) 77 #define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) 78 #define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) 79 #define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) 80 #define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) 81 #define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) 82 #define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) 83 #define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) 84 #define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) 85 86 /* 87 * Module specific PRM register offsets from PRM_BASE + domain offset 88 * 89 * Use prm_{read,write}_mod_reg() with these registers. 90 * 91 * With a few exceptions, these are the register names beginning with 92 * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the 93 * IRQSTATUS and IRQENABLE bits.) 94 */ 95 96 /* Register offsets appearing on both OMAP2 and OMAP3 */ 97 98 #define OMAP2_RM_RSTCTRL 0x0050 99 #define OMAP2_RM_RSTTIME 0x0054 100 #define OMAP2_RM_RSTST 0x0058 101 #define OMAP2_PM_PWSTCTRL 0x00e0 102 #define OMAP2_PM_PWSTST 0x00e4 103 104 #define PM_WKEN 0x00a0 105 #define PM_WKEN1 PM_WKEN 106 #define PM_WKST 0x00b0 107 #define PM_WKST1 PM_WKST 108 #define PM_WKDEP 0x00c8 109 #define PM_EVGENCTRL 0x00d4 110 #define PM_EVGENONTIM 0x00d8 111 #define PM_EVGENOFFTIM 0x00dc 112 113 /* OMAP2xxx specific register offsets */ 114 #define OMAP24XX_PM_WKEN2 0x00a4 115 #define OMAP24XX_PM_WKST2 0x00b4 116 117 #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ 118 #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ 119 #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 120 #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc 121 122 #ifndef __ASSEMBLER__ 123 /* Function prototypes */ 124 extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm); 125 extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); 126 127 void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask); 128 129 extern int __init omap2xxx_prm_init(void); 130 131 #endif 132 133 #endif 134