1 /* 2 * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions 3 * 4 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. 5 * Copyright (C) 2010 Nokia Corporation 6 * 7 * Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H 14 #define __ARCH_ARM_MACH_OMAP2_PRM_H 15 16 #include "prcm-common.h" 17 18 # ifndef __ASSEMBLER__ 19 extern struct omap_domain_base prm_base; 20 extern u16 prm_features; 21 extern void omap2_set_globals_prm(void __iomem *prm); 22 int omap_prcm_init(void); 23 int omap2_prm_base_init(void); 24 int omap2_prcm_base_init(void); 25 # endif 26 27 /* 28 * prm_features flag values 29 * 30 * PRM_HAS_IO_WAKEUP: has IO wakeup capability 31 * PRM_HAS_VOLTAGE: has voltage domains 32 * PRM_IRQ_DEFAULT: use default irq number for PRM irq 33 */ 34 #define PRM_HAS_IO_WAKEUP BIT(0) 35 #define PRM_HAS_VOLTAGE BIT(1) 36 #define PRM_IRQ_DEFAULT BIT(2) 37 38 /* 39 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP 40 * module to softreset 41 */ 42 #define MAX_MODULE_SOFTRESET_WAIT 10000 43 44 /* 45 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP 46 * submodule to exit hardreset 47 */ 48 #define MAX_MODULE_HARDRESET_WAIT 10000 49 50 /* 51 * Register bitfields 52 */ 53 54 /* 55 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP 56 * 57 * 2430: PM_PWSTST_MDM 58 * 59 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, 60 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, 61 * PM_PWSTST_NEON 62 */ 63 #define OMAP_INTRANSITION_MASK (1 << 20) 64 65 66 /* 67 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP 68 * 69 * 2430: PM_PWSTST_MDM 70 * 71 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, 72 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, 73 * PM_PWSTST_NEON 74 */ 75 #define OMAP_POWERSTATEST_SHIFT 0 76 #define OMAP_POWERSTATEST_MASK (0x3 << 0) 77 78 /* 79 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 80 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU 81 * 82 * 2430: PM_PWSTCTRL_MDM shared bits 83 * 84 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, 85 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, 86 * PM_PWSTCTRL_NEON shared bits 87 */ 88 #define OMAP_POWERSTATE_SHIFT 0 89 #define OMAP_POWERSTATE_MASK (0x3 << 0) 90 91 /* 92 * Standardized OMAP reset source bits 93 * 94 * To the extent these happen to match the hardware register bit 95 * shifts, it's purely coincidental. Used by omap-wdt.c. 96 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever 97 * there are any bits remaining in the global PRM_RSTST register that 98 * haven't been identified, or when the PRM code for the current SoC 99 * doesn't know how to interpret the register. 100 */ 101 #define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0 102 #define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1 103 #define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2 104 #define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3 105 #define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4 106 #define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5 107 #define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6 108 #define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7 109 #define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8 110 #define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9 111 #define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10 112 #define OMAP_C2C_RST_SRC_ID_SHIFT 11 113 #define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12 114 115 #ifndef __ASSEMBLER__ 116 117 /** 118 * struct prm_reset_src_map - map register bitshifts to standard bitshifts 119 * @reg_shift: bitshift in the PRM reset source register 120 * @std_shift: bitshift equivalent in the standard reset source list 121 * 122 * The fields are signed because -1 is used as a terminator. 123 */ 124 struct prm_reset_src_map { 125 s8 reg_shift; 126 s8 std_shift; 127 }; 128 129 /** 130 * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations 131 * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl 132 * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn 133 * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn 134 * @late_init: ptr to the late init function 135 * @assert_hardreset: ptr to the SoC PRM hardreset assert impl 136 * @deassert_hardreset: ptr to the SoC PRM hardreset deassert impl 137 * 138 * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are 139 * deprecated. 140 */ 141 struct prm_ll_data { 142 u32 (*read_reset_sources)(void); 143 bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx); 144 void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx); 145 int (*late_init)(void); 146 int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset); 147 int (*deassert_hardreset)(u8 shift, u8 st_shift, u8 part, s16 prm_mod, 148 u16 offset, u16 st_offset); 149 int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod, 150 u16 offset); 151 void (*reset_system)(void); 152 int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask); 153 u32 (*vp_check_txdone)(u8 vp_id); 154 void (*vp_clear_txdone)(u8 vp_id); 155 }; 156 157 extern int prm_register(struct prm_ll_data *pld); 158 extern int prm_unregister(struct prm_ll_data *pld); 159 160 int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset); 161 int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod, 162 u16 offset, u16 st_offset); 163 int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset); 164 extern u32 prm_read_reset_sources(void); 165 extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx); 166 extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx); 167 void omap_prm_reset_system(void); 168 169 void omap_prm_reconfigure_io_chain(void); 170 int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask); 171 172 /* 173 * Voltage Processor (VP) identifiers 174 */ 175 #define OMAP3_VP_VDD_MPU_ID 0 176 #define OMAP3_VP_VDD_CORE_ID 1 177 #define OMAP4_VP_VDD_CORE_ID 0 178 #define OMAP4_VP_VDD_IVA_ID 1 179 #define OMAP4_VP_VDD_MPU_ID 2 180 181 u32 omap_prm_vp_check_txdone(u8 vp_id); 182 void omap_prm_vp_clear_txdone(u8 vp_id); 183 184 #endif 185 186 187 #endif 188