1 /* 2 * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions 3 * 4 * Copyright (C) 2007-2009 Texas Instruments, Inc. 5 * Copyright (C) 2010 Nokia Corporation 6 * 7 * Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H 14 #define __ARCH_ARM_MACH_OMAP2_PRM_H 15 16 #include "prcm-common.h" 17 18 /* 19 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP 20 * 21 * 2430: PM_PWSTST_MDM 22 * 23 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, 24 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, 25 * PM_PWSTST_NEON 26 */ 27 #define OMAP_INTRANSITION_MASK (1 << 20) 28 29 30 /* 31 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP 32 * 33 * 2430: PM_PWSTST_MDM 34 * 35 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, 36 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, 37 * PM_PWSTST_NEON 38 */ 39 #define OMAP_POWERSTATEST_SHIFT 0 40 #define OMAP_POWERSTATEST_MASK (0x3 << 0) 41 42 /* 43 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 44 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU 45 * 46 * 2430: PM_PWSTCTRL_MDM shared bits 47 * 48 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, 49 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, 50 * PM_PWSTCTRL_NEON shared bits 51 */ 52 #define OMAP_POWERSTATE_SHIFT 0 53 #define OMAP_POWERSTATE_MASK (0x3 << 0) 54 55 /* 56 * Standardized OMAP reset source bits 57 * 58 * To the extent these happen to match the hardware register bit 59 * shifts, it's purely coincidental. Used by omap-wdt.c. 60 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever 61 * there are any bits remaining in the global PRM_RSTST register that 62 * haven't been identified, or when the PRM code for the current SoC 63 * doesn't know how to interpret the register. 64 */ 65 #define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0 66 #define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1 67 #define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2 68 #define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3 69 #define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4 70 #define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5 71 #define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6 72 #define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7 73 #define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8 74 #define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9 75 #define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10 76 #define OMAP_C2C_RST_SRC_ID_SHIFT 11 77 #define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12 78 79 #ifndef __ASSEMBLER__ 80 81 /** 82 * struct prm_reset_src_map - map register bitshifts to standard bitshifts 83 * @reg_shift: bitshift in the PRM reset source register 84 * @std_shift: bitshift equivalent in the standard reset source list 85 * 86 * The fields are signed because -1 is used as a terminator. 87 */ 88 struct prm_reset_src_map { 89 s8 reg_shift; 90 s8 std_shift; 91 }; 92 93 /** 94 * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations 95 * @read_reset_sources: ptr to the Soc PRM-specific get_reset_source impl 96 */ 97 struct prm_ll_data { 98 u32 (*read_reset_sources)(void); 99 }; 100 101 extern int prm_register(struct prm_ll_data *pld); 102 extern int prm_unregister(struct prm_ll_data *pld); 103 104 extern u32 prm_read_reset_sources(void); 105 106 #endif 107 108 109 #endif 110