1 /* 2 * OMAP44xx Power Management register bits 3 * 4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 5 * Copyright (C) 2009-2010 Nokia Corporation 6 * 7 * Paul Walmsley (paul@pwsan.com) 8 * Rajendra Nayak (rnayak@ti.com) 9 * Benoit Cousson (b-cousson@ti.com) 10 * 11 * This file is automatically generated from the OMAP hardware databases. 12 * We respectfully ask that any modifications to this file be coordinated 13 * with the public linux-omap@vger.kernel.org mailing list and the 14 * authors above to ensure that the autogeneration scripts are kept 15 * up-to-date with the file contents. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20 */ 21 22 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 23 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 24 25 #include "prm.h" 26 27 28 /* 29 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 30 * PRM_LDO_SRAM_MPU_SETUP 31 */ 32 #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 33 #define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) 34 35 /* 36 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 37 * PRM_LDO_SRAM_MPU_SETUP 38 */ 39 #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 40 #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) 41 42 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 43 #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 44 #define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) 45 46 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 47 #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 48 #define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) 49 50 /* Used by PRM_IRQENABLE_MPU_2 */ 51 #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 52 #define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) 53 54 /* Used by PRM_IRQSTATUS_MPU_2 */ 55 #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 56 #define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) 57 58 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 59 #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 60 #define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) 61 62 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 63 #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 64 #define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) 65 66 /* Used by PM_ABE_PWRSTCTRL */ 67 #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 68 #define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) 69 70 /* Used by PM_ABE_PWRSTCTRL */ 71 #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 72 #define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) 73 74 /* Used by PM_ABE_PWRSTST */ 75 #define OMAP4430_AESSMEM_STATEST_SHIFT 4 76 #define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) 77 78 /* 79 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 80 * PRM_LDO_SRAM_MPU_SETUP 81 */ 82 #define OMAP4430_AIPOFF_SHIFT 8 83 #define OMAP4430_AIPOFF_MASK (1 << 8) 84 85 /* Used by PRM_VOLTCTRL */ 86 #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 87 #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) 88 89 /* Used by PRM_VOLTCTRL */ 90 #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 91 #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) 92 93 /* Used by PRM_VOLTCTRL */ 94 #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 95 #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) 96 97 /* Used by PRM_VC_ERRST */ 98 #define OMAP4430_BYPS_RA_ERR_SHIFT 25 99 #define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) 100 101 /* Used by PRM_VC_ERRST */ 102 #define OMAP4430_BYPS_SA_ERR_SHIFT 24 103 #define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) 104 105 /* Used by PRM_VC_ERRST */ 106 #define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 107 #define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) 108 109 /* Used by PRM_RSTST */ 110 #define OMAP4430_C2C_RST_SHIFT 10 111 #define OMAP4430_C2C_RST_MASK (1 << 10) 112 113 /* Used by PM_CAM_PWRSTCTRL */ 114 #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 115 #define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) 116 117 /* Used by PM_CAM_PWRSTST */ 118 #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 119 #define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) 120 121 /* Used by PRM_CLKREQCTRL */ 122 #define OMAP4430_CLKREQ_COND_SHIFT 0 123 #define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) 124 125 /* Used by PRM_VC_VAL_SMPS_RA_CMD */ 126 #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 127 #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) 128 129 /* Used by PRM_VC_VAL_SMPS_RA_CMD */ 130 #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 131 #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) 132 133 /* Used by PRM_VC_VAL_SMPS_RA_CMD */ 134 #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 135 #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) 136 137 /* Used by PRM_VC_CFG_CHANNEL */ 138 #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 139 #define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) 140 141 /* Used by PRM_VC_CFG_CHANNEL */ 142 #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 143 #define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) 144 145 /* Used by PRM_VC_CFG_CHANNEL */ 146 #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 147 #define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) 148 149 /* Used by PM_CORE_PWRSTCTRL */ 150 #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 151 #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) 152 153 /* Used by PM_CORE_PWRSTCTRL */ 154 #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 155 #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) 156 157 /* Used by PM_CORE_PWRSTST */ 158 #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 159 #define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) 160 161 /* Used by PM_CORE_PWRSTCTRL */ 162 #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 163 #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) 164 165 /* Used by PM_CORE_PWRSTCTRL */ 166 #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 167 #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) 168 169 /* Used by PM_CORE_PWRSTST */ 170 #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 171 #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) 172 173 /* Used by REVISION_PRM */ 174 #define OMAP4430_CUSTOM_SHIFT 6 175 #define OMAP4430_CUSTOM_MASK (0x3 << 6) 176 177 /* Used by PRM_VC_VAL_BYPASS */ 178 #define OMAP4430_DATA_SHIFT 16 179 #define OMAP4430_DATA_MASK (0xff << 16) 180 181 /* Used by PRM_DEVICE_OFF_CTRL */ 182 #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 183 #define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) 184 185 /* Used by PRM_VC_CFG_I2C_MODE */ 186 #define OMAP4430_DFILTEREN_SHIFT 6 187 #define OMAP4430_DFILTEREN_MASK (1 << 6) 188 189 /* 190 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 191 * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP 192 */ 193 #define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 194 #define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) 195 196 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ 197 #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 198 #define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) 199 200 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ 201 #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 202 #define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) 203 204 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 205 #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 206 #define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) 207 208 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 209 #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 210 #define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) 211 212 /* Used by PRM_IRQENABLE_MPU */ 213 #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 214 #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) 215 216 /* Used by PRM_IRQSTATUS_MPU */ 217 #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 218 #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) 219 220 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ 221 #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 222 #define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) 223 224 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ 225 #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 226 #define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) 227 228 /* Used by PRM_IRQENABLE_MPU */ 229 #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 230 #define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) 231 232 /* Used by PRM_IRQSTATUS_MPU */ 233 #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 234 #define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) 235 236 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 237 #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 238 #define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) 239 240 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 241 #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 242 #define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) 243 244 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 245 #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 246 #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) 247 248 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 249 #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 250 #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) 251 252 /* Used by PM_DSS_PWRSTCTRL */ 253 #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 254 #define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) 255 256 /* Used by PM_DSS_PWRSTCTRL */ 257 #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 258 #define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) 259 260 /* Used by PM_DSS_PWRSTST */ 261 #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 262 #define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) 263 264 /* Used by PM_CORE_PWRSTCTRL */ 265 #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 266 #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) 267 268 /* Used by PM_CORE_PWRSTCTRL */ 269 #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 270 #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) 271 272 /* Used by PM_CORE_PWRSTST */ 273 #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 274 #define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) 275 276 /* Used by PM_CORE_PWRSTCTRL */ 277 #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 278 #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) 279 280 /* Used by PM_CORE_PWRSTCTRL */ 281 #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 282 #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) 283 284 /* Used by PM_CORE_PWRSTST */ 285 #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 286 #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) 287 288 /* Used by RM_MPU_RSTST */ 289 #define OMAP4430_EMULATION_RST_SHIFT 0 290 #define OMAP4430_EMULATION_RST_MASK (1 << 0) 291 292 /* Used by RM_DUCATI_RSTST */ 293 #define OMAP4430_EMULATION_RST1ST_SHIFT 3 294 #define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) 295 296 /* Used by RM_DUCATI_RSTST */ 297 #define OMAP4430_EMULATION_RST2ST_SHIFT 4 298 #define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) 299 300 /* Used by RM_IVAHD_RSTST */ 301 #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 302 #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) 303 304 /* Used by RM_IVAHD_RSTST */ 305 #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 306 #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) 307 308 /* Used by PM_EMU_PWRSTCTRL */ 309 #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 310 #define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) 311 312 /* Used by PM_EMU_PWRSTST */ 313 #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 314 #define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) 315 316 /* 317 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 318 * PRM_LDO_SRAM_MPU_SETUP 319 */ 320 #define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 321 #define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) 322 323 /* 324 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 325 * PRM_LDO_SRAM_MPU_SETUP 326 */ 327 #define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 328 #define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) 329 330 /* 331 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 332 * PRM_LDO_SRAM_MPU_SETUP 333 */ 334 #define OMAP4430_ENFUNC4_SHIFT 6 335 #define OMAP4430_ENFUNC4_MASK (1 << 6) 336 337 /* 338 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 339 * PRM_LDO_SRAM_MPU_SETUP 340 */ 341 #define OMAP4430_ENFUNC5_SHIFT 7 342 #define OMAP4430_ENFUNC5_MASK (1 << 7) 343 344 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 345 #define OMAP4430_ERRORGAIN_SHIFT 16 346 #define OMAP4430_ERRORGAIN_MASK (0xff << 16) 347 348 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 349 #define OMAP4430_ERROROFFSET_SHIFT 24 350 #define OMAP4430_ERROROFFSET_MASK (0xff << 24) 351 352 /* Used by PRM_RSTST */ 353 #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 354 #define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) 355 356 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 357 #define OMAP4430_FORCEUPDATE_SHIFT 1 358 #define OMAP4430_FORCEUPDATE_MASK (1 << 1) 359 360 /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ 361 #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 362 #define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) 363 364 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ 365 #define OMAP4430_FORCEWKUP_EN_SHIFT 10 366 #define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) 367 368 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ 369 #define OMAP4430_FORCEWKUP_ST_SHIFT 10 370 #define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) 371 372 /* Used by REVISION_PRM */ 373 #define OMAP4430_FUNC_SHIFT 16 374 #define OMAP4430_FUNC_MASK (0xfff << 16) 375 376 /* Used by PM_GFX_PWRSTCTRL */ 377 #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 378 #define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) 379 380 /* Used by PM_GFX_PWRSTST */ 381 #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 382 #define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) 383 384 /* Used by PRM_RSTST */ 385 #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 386 #define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) 387 388 /* Used by PRM_RSTST */ 389 #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 390 #define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) 391 392 /* Used by PRM_IO_PMCTRL */ 393 #define OMAP4430_GLOBAL_WUEN_SHIFT 16 394 #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) 395 396 /* Used by PRM_VC_CFG_I2C_MODE */ 397 #define OMAP4430_HSMCODE_SHIFT 0 398 #define OMAP4430_HSMCODE_MASK (0x7 << 0) 399 400 /* Used by PRM_VC_CFG_I2C_MODE */ 401 #define OMAP4430_HSMODEEN_SHIFT 3 402 #define OMAP4430_HSMODEEN_MASK (1 << 3) 403 404 /* Used by PRM_VC_CFG_I2C_CLK */ 405 #define OMAP4430_HSSCLH_SHIFT 16 406 #define OMAP4430_HSSCLH_MASK (0xff << 16) 407 408 /* Used by PRM_VC_CFG_I2C_CLK */ 409 #define OMAP4430_HSSCLL_SHIFT 24 410 #define OMAP4430_HSSCLL_MASK (0xff << 24) 411 412 /* Used by PM_IVAHD_PWRSTCTRL */ 413 #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 414 #define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) 415 416 /* Used by PM_IVAHD_PWRSTCTRL */ 417 #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 418 #define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) 419 420 /* Used by PM_IVAHD_PWRSTST */ 421 #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 422 #define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) 423 424 /* Used by RM_MPU_RSTST */ 425 #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 426 #define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) 427 428 /* Used by RM_DUCATI_RSTST */ 429 #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 430 #define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) 431 432 /* Used by RM_DUCATI_RSTST */ 433 #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 434 #define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) 435 436 /* Used by RM_IVAHD_RSTST */ 437 #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 438 #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) 439 440 /* Used by RM_IVAHD_RSTST */ 441 #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 442 #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) 443 444 /* Used by PRM_RSTST */ 445 #define OMAP4430_ICEPICK_RST_SHIFT 9 446 #define OMAP4430_ICEPICK_RST_MASK (1 << 9) 447 448 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 449 #define OMAP4430_INITVDD_SHIFT 2 450 #define OMAP4430_INITVDD_MASK (1 << 2) 451 452 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 453 #define OMAP4430_INITVOLTAGE_SHIFT 8 454 #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) 455 456 /* 457 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, 458 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, 459 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST 460 */ 461 #define OMAP4430_INTRANSITION_SHIFT 20 462 #define OMAP4430_INTRANSITION_MASK (1 << 20) 463 464 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 465 #define OMAP4430_IO_EN_SHIFT 9 466 #define OMAP4430_IO_EN_MASK (1 << 9) 467 468 /* Used by PRM_IO_PMCTRL */ 469 #define OMAP4430_IO_ON_STATUS_SHIFT 5 470 #define OMAP4430_IO_ON_STATUS_MASK (1 << 5) 471 472 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 473 #define OMAP4430_IO_ST_SHIFT 9 474 #define OMAP4430_IO_ST_MASK (1 << 9) 475 476 /* Used by PRM_IO_PMCTRL */ 477 #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 478 #define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) 479 480 /* Used by PRM_IO_PMCTRL */ 481 #define OMAP4430_ISOCLK_STATUS_SHIFT 1 482 #define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) 483 484 /* Used by PRM_IO_PMCTRL */ 485 #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 486 #define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) 487 488 /* Used by PRM_IO_COUNT */ 489 #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 490 #define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) 491 492 /* Used by PM_L3INIT_PWRSTCTRL */ 493 #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 494 #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) 495 496 /* Used by PM_L3INIT_PWRSTCTRL */ 497 #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 498 #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) 499 500 /* Used by PM_L3INIT_PWRSTST */ 501 #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 502 #define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) 503 504 /* 505 * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, 506 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST 507 */ 508 #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 509 #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) 510 511 /* 512 * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, 513 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, 514 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL 515 */ 516 #define OMAP4430_LOGICRETSTATE_SHIFT 2 517 #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) 518 519 /* 520 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, 521 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, 522 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST 523 */ 524 #define OMAP4430_LOGICSTATEST_SHIFT 2 525 #define OMAP4430_LOGICSTATEST_MASK (1 << 2) 526 527 /* 528 * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, 529 * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, 530 * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, 531 * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, 532 * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, 533 * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, 534 * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, 535 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, 536 * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, 537 * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, 538 * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, 539 * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, 540 * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, 541 * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, 542 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, 543 * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, 544 * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, 545 * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, 546 * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, 547 * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, 548 * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, 549 * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, 550 * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, 551 * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, 552 * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, 553 * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, 554 * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, 555 * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, 556 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, 557 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, 558 * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, 559 * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, 560 * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, 561 * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT 562 */ 563 #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 564 #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) 565 566 /* 567 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, 568 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, 569 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, 570 * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, 571 * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, 572 * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, 573 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, 574 * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, 575 * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, 576 * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, 577 * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, 578 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, 579 * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, 580 * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, 581 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, 582 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, 583 * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT 584 */ 585 #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 586 #define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) 587 588 /* Used by RM_ABE_AESS_CONTEXT */ 589 #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 590 #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) 591 592 /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ 593 #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 594 #define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) 595 596 /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ 597 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 598 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) 599 600 /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ 601 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 602 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) 603 604 /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ 605 #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 606 #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) 607 608 /* 609 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, 610 * RM_SDMA_SDMA_CONTEXT 611 */ 612 #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 613 #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) 614 615 /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ 616 #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 617 #define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) 618 619 /* Used by RM_DUCATI_DUCATI_CONTEXT */ 620 #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 621 #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) 622 623 /* Used by RM_DUCATI_DUCATI_CONTEXT */ 624 #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 625 #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) 626 627 /* Used by RM_EMU_DEBUGSS_CONTEXT */ 628 #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 629 #define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) 630 631 /* Used by RM_GFX_GFX_CONTEXT */ 632 #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 633 #define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) 634 635 /* Used by RM_IVAHD_IVAHD_CONTEXT */ 636 #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 637 #define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) 638 639 /* 640 * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, 641 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, 642 * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT, 643 * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, 644 * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT 645 */ 646 #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 647 #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) 648 649 /* Used by RM_MPU_MPU_CONTEXT */ 650 #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 651 #define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) 652 653 /* Used by RM_MPU_MPU_CONTEXT */ 654 #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 655 #define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) 656 657 /* Used by RM_MPU_MPU_CONTEXT */ 658 #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 659 #define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) 660 661 /* 662 * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, 663 * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, 664 * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT 665 */ 666 #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 667 #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) 668 669 /* 670 * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, 671 * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT 672 */ 673 #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 674 #define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) 675 676 /* 677 * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, 678 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, 679 * RM_L4SEC_CRYPTODMA_CONTEXT 680 */ 681 #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 682 #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) 683 684 /* Used by RM_IVAHD_SL2_CONTEXT */ 685 #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 686 #define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) 687 688 /* Used by RM_IVAHD_IVAHD_CONTEXT */ 689 #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 690 #define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) 691 692 /* Used by RM_IVAHD_IVAHD_CONTEXT */ 693 #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 694 #define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) 695 696 /* Used by RM_TESLA_TESLA_CONTEXT */ 697 #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 698 #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) 699 700 /* Used by RM_TESLA_TESLA_CONTEXT */ 701 #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 702 #define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) 703 704 /* Used by RM_TESLA_TESLA_CONTEXT */ 705 #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 706 #define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) 707 708 /* Used by RM_WKUP_SARRAM_CONTEXT */ 709 #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 710 #define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) 711 712 /* 713 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, 714 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, 715 * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL 716 */ 717 #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 718 #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) 719 720 /* Used by PRM_MODEM_IF_CTRL */ 721 #define OMAP4430_MODEM_READY_SHIFT 1 722 #define OMAP4430_MODEM_READY_MASK (1 << 1) 723 724 /* Used by PRM_MODEM_IF_CTRL */ 725 #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 726 #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) 727 728 /* Used by PRM_MODEM_IF_CTRL */ 729 #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 730 #define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) 731 732 /* Used by PRM_MODEM_IF_CTRL */ 733 #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 734 #define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) 735 736 /* Used by PM_MPU_PWRSTCTRL */ 737 #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 738 #define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) 739 740 /* Used by PM_MPU_PWRSTCTRL */ 741 #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 742 #define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) 743 744 /* Used by PM_MPU_PWRSTST */ 745 #define OMAP4430_MPU_L1_STATEST_SHIFT 4 746 #define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) 747 748 /* Used by PM_MPU_PWRSTCTRL */ 749 #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 750 #define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) 751 752 /* Used by PM_MPU_PWRSTCTRL */ 753 #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 754 #define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) 755 756 /* Used by PM_MPU_PWRSTST */ 757 #define OMAP4430_MPU_L2_STATEST_SHIFT 6 758 #define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) 759 760 /* Used by PM_MPU_PWRSTCTRL */ 761 #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 762 #define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) 763 764 /* Used by PM_MPU_PWRSTCTRL */ 765 #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 766 #define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) 767 768 /* Used by PM_MPU_PWRSTST */ 769 #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 770 #define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) 771 772 /* Used by PRM_RSTST */ 773 #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 774 #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) 775 776 /* Used by PRM_RSTST */ 777 #define OMAP4430_MPU_WDT_RST_SHIFT 3 778 #define OMAP4430_MPU_WDT_RST_MASK (1 << 3) 779 780 /* Used by PM_L4PER_PWRSTCTRL */ 781 #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 782 #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) 783 784 /* Used by PM_L4PER_PWRSTCTRL */ 785 #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 786 #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) 787 788 /* Used by PM_L4PER_PWRSTST */ 789 #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 790 #define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) 791 792 /* Used by PM_CORE_PWRSTCTRL */ 793 #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 794 #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) 795 796 /* Used by PM_CORE_PWRSTCTRL */ 797 #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 798 #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) 799 800 /* Used by PM_CORE_PWRSTST */ 801 #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 802 #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) 803 804 /* 805 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 806 * PRM_VC_VAL_CMD_VDD_MPU_L 807 */ 808 #define OMAP4430_OFF_SHIFT 0 809 #define OMAP4430_OFF_MASK (0xff << 0) 810 811 /* 812 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 813 * PRM_VC_VAL_CMD_VDD_MPU_L 814 */ 815 #define OMAP4430_ON_SHIFT 24 816 #define OMAP4430_ON_MASK (0xff << 24) 817 818 /* 819 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 820 * PRM_VC_VAL_CMD_VDD_MPU_L 821 */ 822 #define OMAP4430_ONLP_SHIFT 16 823 #define OMAP4430_ONLP_MASK (0xff << 16) 824 825 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 826 #define OMAP4430_OPP_CHANGE_SHIFT 2 827 #define OMAP4430_OPP_CHANGE_MASK (1 << 2) 828 829 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 830 #define OMAP4430_OPP_SEL_SHIFT 0 831 #define OMAP4430_OPP_SEL_MASK (0x3 << 0) 832 833 /* Used by PRM_SRAM_COUNT */ 834 #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 835 #define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) 836 837 /* Used by PRM_PSCON_COUNT */ 838 #define OMAP4430_PCHARGE_TIME_SHIFT 0 839 #define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) 840 841 /* Used by PM_ABE_PWRSTCTRL */ 842 #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 843 #define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) 844 845 /* Used by PM_ABE_PWRSTCTRL */ 846 #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 847 #define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) 848 849 /* Used by PM_ABE_PWRSTST */ 850 #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 851 #define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) 852 853 /* Used by PRM_PHASE1_CNDP */ 854 #define OMAP4430_PHASE1_CNDP_SHIFT 0 855 #define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) 856 857 /* Used by PRM_PHASE2A_CNDP */ 858 #define OMAP4430_PHASE2A_CNDP_SHIFT 0 859 #define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) 860 861 /* Used by PRM_PHASE2B_CNDP */ 862 #define OMAP4430_PHASE2B_CNDP_SHIFT 0 863 #define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) 864 865 /* Used by PRM_PSCON_COUNT */ 866 #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 867 #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) 868 869 /* 870 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, 871 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, 872 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, 873 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL 874 */ 875 #define OMAP4430_POWERSTATE_SHIFT 0 876 #define OMAP4430_POWERSTATE_MASK (0x3 << 0) 877 878 /* 879 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, 880 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, 881 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST 882 */ 883 #define OMAP4430_POWERSTATEST_SHIFT 0 884 #define OMAP4430_POWERSTATEST_MASK (0x3 << 0) 885 886 /* Used by PRM_PWRREQCTRL */ 887 #define OMAP4430_PWRREQ_COND_SHIFT 0 888 #define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) 889 890 /* Used by PRM_VC_CFG_CHANNEL */ 891 #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 892 #define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) 893 894 /* Used by PRM_VC_CFG_CHANNEL */ 895 #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 896 #define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) 897 898 /* Used by PRM_VC_CFG_CHANNEL */ 899 #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 900 #define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) 901 902 /* Used by PRM_VC_CFG_CHANNEL */ 903 #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 904 #define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) 905 906 /* Used by PRM_VC_CFG_CHANNEL */ 907 #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 908 #define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) 909 910 /* Used by PRM_VC_CFG_CHANNEL */ 911 #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 912 #define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) 913 914 /* 915 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 916 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 917 * PRM_VOLTSETUP_MPU_RET_SLEEP 918 */ 919 #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 920 #define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) 921 922 /* 923 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 924 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 925 * PRM_VOLTSETUP_MPU_RET_SLEEP 926 */ 927 #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 928 #define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) 929 930 /* 931 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 932 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 933 * PRM_VOLTSETUP_MPU_RET_SLEEP 934 */ 935 #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 936 #define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) 937 938 /* 939 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 940 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 941 * PRM_VOLTSETUP_MPU_RET_SLEEP 942 */ 943 #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 944 #define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) 945 946 /* Used by PRM_VC_CFG_CHANNEL */ 947 #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 948 #define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) 949 950 /* Used by PRM_VC_CFG_CHANNEL */ 951 #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 952 #define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) 953 954 /* Used by PRM_VC_CFG_CHANNEL */ 955 #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 956 #define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) 957 958 /* Used by PRM_VC_VAL_BYPASS */ 959 #define OMAP4430_REGADDR_SHIFT 8 960 #define OMAP4430_REGADDR_MASK (0xff << 8) 961 962 /* 963 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 964 * PRM_VC_VAL_CMD_VDD_MPU_L 965 */ 966 #define OMAP4430_RET_SHIFT 8 967 #define OMAP4430_RET_MASK (0xff << 8) 968 969 /* Used by PM_L4PER_PWRSTCTRL */ 970 #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 971 #define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) 972 973 /* Used by PM_L4PER_PWRSTCTRL */ 974 #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 975 #define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) 976 977 /* Used by PM_L4PER_PWRSTST */ 978 #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 979 #define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) 980 981 /* 982 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 983 * PRM_LDO_SRAM_MPU_CTRL 984 */ 985 #define OMAP4430_RETMODE_ENABLE_SHIFT 0 986 #define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) 987 988 /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ 989 #define OMAP4430_RST1_SHIFT 0 990 #define OMAP4430_RST1_MASK (1 << 0) 991 992 /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ 993 #define OMAP4430_RST1ST_SHIFT 0 994 #define OMAP4430_RST1ST_MASK (1 << 0) 995 996 /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ 997 #define OMAP4430_RST2_SHIFT 1 998 #define OMAP4430_RST2_MASK (1 << 1) 999 1000 /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ 1001 #define OMAP4430_RST2ST_SHIFT 1 1002 #define OMAP4430_RST2ST_MASK (1 << 1) 1003 1004 /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ 1005 #define OMAP4430_RST3_SHIFT 2 1006 #define OMAP4430_RST3_MASK (1 << 2) 1007 1008 /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ 1009 #define OMAP4430_RST3ST_SHIFT 2 1010 #define OMAP4430_RST3ST_MASK (1 << 2) 1011 1012 /* Used by PRM_RSTTIME */ 1013 #define OMAP4430_RSTTIME1_SHIFT 0 1014 #define OMAP4430_RSTTIME1_MASK (0x3ff << 0) 1015 1016 /* Used by PRM_RSTTIME */ 1017 #define OMAP4430_RSTTIME2_SHIFT 10 1018 #define OMAP4430_RSTTIME2_MASK (0x1f << 10) 1019 1020 /* Used by PRM_RSTCTRL */ 1021 #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 1022 #define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) 1023 1024 /* Used by PRM_RSTCTRL */ 1025 #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 1026 #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) 1027 1028 /* Used by REVISION_PRM */ 1029 #define OMAP4430_R_RTL_SHIFT 11 1030 #define OMAP4430_R_RTL_MASK (0x1f << 11) 1031 1032 /* Used by PRM_VC_CFG_CHANNEL */ 1033 #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 1034 #define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) 1035 1036 /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ 1037 #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 1038 #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) 1039 1040 /* Used by PRM_VC_CFG_CHANNEL */ 1041 #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 1042 #define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) 1043 1044 /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ 1045 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 1046 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) 1047 1048 /* Used by PRM_VC_CFG_CHANNEL */ 1049 #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 1050 #define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) 1051 1052 /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ 1053 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 1054 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) 1055 1056 /* Used by REVISION_PRM */ 1057 #define OMAP4430_SCHEME_SHIFT 30 1058 #define OMAP4430_SCHEME_MASK (0x3 << 30) 1059 1060 /* Used by PRM_VC_CFG_I2C_CLK */ 1061 #define OMAP4430_SCLH_SHIFT 0 1062 #define OMAP4430_SCLH_MASK (0xff << 0) 1063 1064 /* Used by PRM_VC_CFG_I2C_CLK */ 1065 #define OMAP4430_SCLL_SHIFT 8 1066 #define OMAP4430_SCLL_MASK (0xff << 8) 1067 1068 /* Used by PRM_RSTST */ 1069 #define OMAP4430_SECURE_WDT_RST_SHIFT 4 1070 #define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) 1071 1072 /* Used by PM_IVAHD_PWRSTCTRL */ 1073 #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 1074 #define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) 1075 1076 /* Used by PM_IVAHD_PWRSTCTRL */ 1077 #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 1078 #define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) 1079 1080 /* Used by PM_IVAHD_PWRSTST */ 1081 #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 1082 #define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) 1083 1084 /* Used by PRM_VC_VAL_BYPASS */ 1085 #define OMAP4430_SLAVEADDR_SHIFT 0 1086 #define OMAP4430_SLAVEADDR_MASK (0x7f << 0) 1087 1088 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 1089 #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 1090 #define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) 1091 1092 /* Used by PRM_SRAM_COUNT */ 1093 #define OMAP4430_SLPCNT_VALUE_SHIFT 16 1094 #define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) 1095 1096 /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ 1097 #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 1098 #define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) 1099 1100 /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ 1101 #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 1102 #define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) 1103 1104 /* Used by PRM_VC_ERRST */ 1105 #define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 1106 #define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) 1107 1108 /* Used by PRM_VC_ERRST */ 1109 #define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 1110 #define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) 1111 1112 /* Used by PRM_VC_ERRST */ 1113 #define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 1114 #define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) 1115 1116 /* Used by PRM_VC_ERRST */ 1117 #define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 1118 #define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) 1119 1120 /* Used by PRM_VC_ERRST */ 1121 #define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 1122 #define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) 1123 1124 /* Used by PRM_VC_ERRST */ 1125 #define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 1126 #define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) 1127 1128 /* Used by PRM_VC_ERRST */ 1129 #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 1130 #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) 1131 1132 /* Used by PRM_VC_ERRST */ 1133 #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 1134 #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) 1135 1136 /* Used by PRM_VC_ERRST */ 1137 #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 1138 #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) 1139 1140 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 1141 #define OMAP4430_SR2EN_SHIFT 0 1142 #define OMAP4430_SR2EN_MASK (1 << 0) 1143 1144 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 1145 #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 1146 #define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) 1147 1148 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 1149 #define OMAP4430_SR2_STATUS_SHIFT 3 1150 #define OMAP4430_SR2_STATUS_MASK (0x3 << 3) 1151 1152 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 1153 #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 1154 #define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) 1155 1156 /* 1157 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 1158 * PRM_LDO_SRAM_MPU_CTRL 1159 */ 1160 #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 1161 #define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) 1162 1163 /* 1164 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 1165 * PRM_LDO_SRAM_MPU_CTRL 1166 */ 1167 #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 1168 #define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) 1169 1170 /* Used by PRM_VC_CFG_I2C_MODE */ 1171 #define OMAP4430_SRMODEEN_SHIFT 4 1172 #define OMAP4430_SRMODEEN_MASK (1 << 4) 1173 1174 /* Used by PRM_VOLTSETUP_WARMRESET */ 1175 #define OMAP4430_STABLE_COUNT_SHIFT 0 1176 #define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) 1177 1178 /* Used by PRM_VOLTSETUP_WARMRESET */ 1179 #define OMAP4430_STABLE_PRESCAL_SHIFT 8 1180 #define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) 1181 1182 /* Used by PRM_LDO_BANDGAP_SETUP */ 1183 #define OMAP4430_STARTUP_COUNT_SHIFT 0 1184 #define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) 1185 1186 /* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ 1187 #define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 1188 #define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) 1189 1190 /* Used by PM_IVAHD_PWRSTCTRL */ 1191 #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 1192 #define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) 1193 1194 /* Used by PM_IVAHD_PWRSTCTRL */ 1195 #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 1196 #define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) 1197 1198 /* Used by PM_IVAHD_PWRSTST */ 1199 #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 1200 #define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) 1201 1202 /* Used by PM_IVAHD_PWRSTCTRL */ 1203 #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 1204 #define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) 1205 1206 /* Used by PM_IVAHD_PWRSTCTRL */ 1207 #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 1208 #define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) 1209 1210 /* Used by PM_IVAHD_PWRSTST */ 1211 #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 1212 #define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) 1213 1214 /* Used by RM_TESLA_RSTST */ 1215 #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 1216 #define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) 1217 1218 /* Used by RM_TESLA_RSTST */ 1219 #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 1220 #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) 1221 1222 /* Used by PM_TESLA_PWRSTCTRL */ 1223 #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 1224 #define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) 1225 1226 /* Used by PM_TESLA_PWRSTCTRL */ 1227 #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 1228 #define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) 1229 1230 /* Used by PM_TESLA_PWRSTST */ 1231 #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 1232 #define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) 1233 1234 /* Used by PM_TESLA_PWRSTCTRL */ 1235 #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 1236 #define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) 1237 1238 /* Used by PM_TESLA_PWRSTCTRL */ 1239 #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 1240 #define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) 1241 1242 /* Used by PM_TESLA_PWRSTST */ 1243 #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 1244 #define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) 1245 1246 /* Used by PM_TESLA_PWRSTCTRL */ 1247 #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 1248 #define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) 1249 1250 /* Used by PM_TESLA_PWRSTCTRL */ 1251 #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 1252 #define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) 1253 1254 /* Used by PM_TESLA_PWRSTST */ 1255 #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 1256 #define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) 1257 1258 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 1259 #define OMAP4430_TIMEOUT_SHIFT 0 1260 #define OMAP4430_TIMEOUT_MASK (0xffff << 0) 1261 1262 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 1263 #define OMAP4430_TIMEOUTEN_SHIFT 3 1264 #define OMAP4430_TIMEOUTEN_MASK (1 << 3) 1265 1266 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1267 #define OMAP4430_TRANSITION_EN_SHIFT 8 1268 #define OMAP4430_TRANSITION_EN_MASK (1 << 8) 1269 1270 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1271 #define OMAP4430_TRANSITION_ST_SHIFT 8 1272 #define OMAP4430_TRANSITION_ST_MASK (1 << 8) 1273 1274 /* Used by PRM_VC_VAL_BYPASS */ 1275 #define OMAP4430_VALID_SHIFT 24 1276 #define OMAP4430_VALID_MASK (1 << 24) 1277 1278 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1279 #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 1280 #define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) 1281 1282 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1283 #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 1284 #define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) 1285 1286 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1287 #define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 1288 #define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) 1289 1290 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1291 #define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 1292 #define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) 1293 1294 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1295 #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 1296 #define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) 1297 1298 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1299 #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 1300 #define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) 1301 1302 /* Used by PRM_IRQENABLE_MPU_2 */ 1303 #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 1304 #define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) 1305 1306 /* Used by PRM_IRQSTATUS_MPU_2 */ 1307 #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 1308 #define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) 1309 1310 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1311 #define OMAP4430_VC_RAERR_EN_SHIFT 12 1312 #define OMAP4430_VC_RAERR_EN_MASK (1 << 12) 1313 1314 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1315 #define OMAP4430_VC_RAERR_ST_SHIFT 12 1316 #define OMAP4430_VC_RAERR_ST_MASK (1 << 12) 1317 1318 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1319 #define OMAP4430_VC_SAERR_EN_SHIFT 11 1320 #define OMAP4430_VC_SAERR_EN_MASK (1 << 11) 1321 1322 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1323 #define OMAP4430_VC_SAERR_ST_SHIFT 11 1324 #define OMAP4430_VC_SAERR_ST_MASK (1 << 11) 1325 1326 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1327 #define OMAP4430_VC_TOERR_EN_SHIFT 13 1328 #define OMAP4430_VC_TOERR_EN_MASK (1 << 13) 1329 1330 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1331 #define OMAP4430_VC_TOERR_ST_SHIFT 13 1332 #define OMAP4430_VC_TOERR_ST_MASK (1 << 13) 1333 1334 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 1335 #define OMAP4430_VDDMAX_SHIFT 24 1336 #define OMAP4430_VDDMAX_MASK (0xff << 24) 1337 1338 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 1339 #define OMAP4430_VDDMIN_SHIFT 16 1340 #define OMAP4430_VDDMIN_MASK (0xff << 16) 1341 1342 /* Used by PRM_VOLTCTRL */ 1343 #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 1344 #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) 1345 1346 /* Used by PRM_RSTST */ 1347 #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 1348 #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) 1349 1350 /* Used by PRM_VOLTCTRL */ 1351 #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 1352 #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) 1353 1354 /* Used by PRM_VOLTCTRL */ 1355 #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 1356 #define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) 1357 1358 /* Used by PRM_RSTST */ 1359 #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 1360 #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) 1361 1362 /* Used by PRM_VOLTCTRL */ 1363 #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 1364 #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) 1365 1366 /* Used by PRM_VOLTCTRL */ 1367 #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 1368 #define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) 1369 1370 /* Used by PRM_RSTST */ 1371 #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 1372 #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) 1373 1374 /* Used by PRM_VC_ERRST */ 1375 #define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 1376 #define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) 1377 1378 /* Used by PRM_VC_ERRST */ 1379 #define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 1380 #define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) 1381 1382 /* Used by PRM_VC_ERRST */ 1383 #define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 1384 #define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) 1385 1386 /* Used by PRM_VC_ERRST */ 1387 #define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 1388 #define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) 1389 1390 /* Used by PRM_VC_ERRST */ 1391 #define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 1392 #define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) 1393 1394 /* Used by PRM_VC_ERRST */ 1395 #define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 1396 #define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) 1397 1398 /* Used by PRM_VC_ERRST */ 1399 #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 1400 #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) 1401 1402 /* Used by PRM_VC_ERRST */ 1403 #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 1404 #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) 1405 1406 /* Used by PRM_VC_ERRST */ 1407 #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 1408 #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) 1409 1410 /* Used by PRM_VC_VAL_SMPS_RA_VOL */ 1411 #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 1412 #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) 1413 1414 /* Used by PRM_VC_VAL_SMPS_RA_VOL */ 1415 #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 1416 #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) 1417 1418 /* Used by PRM_VC_VAL_SMPS_RA_VOL */ 1419 #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 1420 #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) 1421 1422 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 1423 #define OMAP4430_VPENABLE_SHIFT 0 1424 #define OMAP4430_VPENABLE_MASK (1 << 0) 1425 1426 /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ 1427 #define OMAP4430_VPINIDLE_SHIFT 0 1428 #define OMAP4430_VPINIDLE_MASK (1 << 0) 1429 1430 /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ 1431 #define OMAP4430_VPVOLTAGE_SHIFT 0 1432 #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) 1433 1434 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1435 #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 1436 #define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) 1437 1438 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1439 #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 1440 #define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) 1441 1442 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1443 #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 1444 #define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) 1445 1446 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1447 #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 1448 #define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) 1449 1450 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1451 #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 1452 #define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) 1453 1454 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1455 #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 1456 #define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) 1457 1458 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1459 #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 1460 #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) 1461 1462 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1463 #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 1464 #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) 1465 1466 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1467 #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 1468 #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) 1469 1470 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1471 #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 1472 #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) 1473 1474 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1475 #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 1476 #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) 1477 1478 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1479 #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 1480 #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) 1481 1482 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1483 #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 1484 #define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) 1485 1486 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1487 #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 1488 #define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) 1489 1490 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1491 #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 1492 #define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) 1493 1494 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1495 #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 1496 #define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) 1497 1498 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1499 #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 1500 #define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) 1501 1502 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1503 #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 1504 #define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) 1505 1506 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1507 #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 1508 #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) 1509 1510 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1511 #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 1512 #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) 1513 1514 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1515 #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 1516 #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) 1517 1518 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1519 #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 1520 #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) 1521 1522 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1523 #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 1524 #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) 1525 1526 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1527 #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 1528 #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) 1529 1530 /* Used by PRM_IRQENABLE_MPU_2 */ 1531 #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 1532 #define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) 1533 1534 /* Used by PRM_IRQSTATUS_MPU_2 */ 1535 #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 1536 #define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) 1537 1538 /* Used by PRM_IRQENABLE_MPU_2 */ 1539 #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 1540 #define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) 1541 1542 /* Used by PRM_IRQSTATUS_MPU_2 */ 1543 #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 1544 #define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) 1545 1546 /* Used by PRM_IRQENABLE_MPU_2 */ 1547 #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 1548 #define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) 1549 1550 /* Used by PRM_IRQSTATUS_MPU_2 */ 1551 #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 1552 #define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) 1553 1554 /* Used by PRM_IRQENABLE_MPU_2 */ 1555 #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 1556 #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) 1557 1558 /* Used by PRM_IRQSTATUS_MPU_2 */ 1559 #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 1560 #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) 1561 1562 /* Used by PRM_IRQENABLE_MPU_2 */ 1563 #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 1564 #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) 1565 1566 /* Used by PRM_IRQSTATUS_MPU_2 */ 1567 #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 1568 #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) 1569 1570 /* Used by PRM_IRQENABLE_MPU_2 */ 1571 #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 1572 #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) 1573 1574 /* Used by PRM_IRQSTATUS_MPU_2 */ 1575 #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 1576 #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) 1577 1578 /* Used by PRM_SRAM_COUNT */ 1579 #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 1580 #define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) 1581 1582 /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ 1583 #define OMAP4430_VSTEPMAX_SHIFT 0 1584 #define OMAP4430_VSTEPMAX_MASK (0xff << 0) 1585 1586 /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ 1587 #define OMAP4430_VSTEPMIN_SHIFT 0 1588 #define OMAP4430_VSTEPMIN_MASK (0xff << 0) 1589 1590 /* Used by PRM_MODEM_IF_CTRL */ 1591 #define OMAP4430_WAKE_MODEM_SHIFT 0 1592 #define OMAP4430_WAKE_MODEM_MASK (1 << 0) 1593 1594 /* Used by PM_DSS_DSS_WKDEP */ 1595 #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 1596 #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) 1597 1598 /* Used by PM_DSS_DSS_WKDEP */ 1599 #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 1600 #define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) 1601 1602 /* Used by PM_DSS_DSS_WKDEP */ 1603 #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 1604 #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) 1605 1606 /* Used by PM_DSS_DSS_WKDEP */ 1607 #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 1608 #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) 1609 1610 /* Used by PM_ABE_DMIC_WKDEP */ 1611 #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 1612 #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) 1613 1614 /* Used by PM_ABE_DMIC_WKDEP */ 1615 #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 1616 #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) 1617 1618 /* Used by PM_ABE_DMIC_WKDEP */ 1619 #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 1620 #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) 1621 1622 /* Used by PM_ABE_DMIC_WKDEP */ 1623 #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 1624 #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) 1625 1626 /* Used by PM_L4PER_DMTIMER10_WKDEP */ 1627 #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 1628 #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) 1629 1630 /* Used by PM_L4PER_DMTIMER11_WKDEP */ 1631 #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 1632 #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) 1633 1634 /* Used by PM_L4PER_DMTIMER11_WKDEP */ 1635 #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 1636 #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) 1637 1638 /* Used by PM_L4PER_DMTIMER2_WKDEP */ 1639 #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 1640 #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) 1641 1642 /* Used by PM_L4PER_DMTIMER3_WKDEP */ 1643 #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 1644 #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) 1645 1646 /* Used by PM_L4PER_DMTIMER3_WKDEP */ 1647 #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 1648 #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) 1649 1650 /* Used by PM_L4PER_DMTIMER4_WKDEP */ 1651 #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 1652 #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) 1653 1654 /* Used by PM_L4PER_DMTIMER4_WKDEP */ 1655 #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 1656 #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) 1657 1658 /* Used by PM_L4PER_DMTIMER9_WKDEP */ 1659 #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 1660 #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) 1661 1662 /* Used by PM_L4PER_DMTIMER9_WKDEP */ 1663 #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 1664 #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) 1665 1666 /* Used by PM_DSS_DSS_WKDEP */ 1667 #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 1668 #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) 1669 1670 /* Used by PM_DSS_DSS_WKDEP */ 1671 #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 1672 #define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) 1673 1674 /* Used by PM_DSS_DSS_WKDEP */ 1675 #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 1676 #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) 1677 1678 /* Used by PM_DSS_DSS_WKDEP */ 1679 #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 1680 #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) 1681 1682 /* Used by PM_DSS_DSS_WKDEP */ 1683 #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 1684 #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) 1685 1686 /* Used by PM_DSS_DSS_WKDEP */ 1687 #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 1688 #define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) 1689 1690 /* Used by PM_DSS_DSS_WKDEP */ 1691 #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 1692 #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) 1693 1694 /* Used by PM_DSS_DSS_WKDEP */ 1695 #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 1696 #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) 1697 1698 /* Used by PM_WKUP_GPIO1_WKDEP */ 1699 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 1700 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) 1701 1702 /* Used by PM_WKUP_GPIO1_WKDEP */ 1703 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 1704 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) 1705 1706 /* Used by PM_WKUP_GPIO1_WKDEP */ 1707 #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 1708 #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) 1709 1710 /* Used by PM_L4PER_GPIO2_WKDEP */ 1711 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 1712 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) 1713 1714 /* Used by PM_L4PER_GPIO2_WKDEP */ 1715 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 1716 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) 1717 1718 /* Used by PM_L4PER_GPIO2_WKDEP */ 1719 #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 1720 #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) 1721 1722 /* Used by PM_L4PER_GPIO3_WKDEP */ 1723 #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 1724 #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) 1725 1726 /* Used by PM_L4PER_GPIO3_WKDEP */ 1727 #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 1728 #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) 1729 1730 /* Used by PM_L4PER_GPIO4_WKDEP */ 1731 #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 1732 #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) 1733 1734 /* Used by PM_L4PER_GPIO4_WKDEP */ 1735 #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 1736 #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) 1737 1738 /* Used by PM_L4PER_GPIO5_WKDEP */ 1739 #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 1740 #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) 1741 1742 /* Used by PM_L4PER_GPIO5_WKDEP */ 1743 #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 1744 #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) 1745 1746 /* Used by PM_L4PER_GPIO6_WKDEP */ 1747 #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 1748 #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) 1749 1750 /* Used by PM_L4PER_GPIO6_WKDEP */ 1751 #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 1752 #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) 1753 1754 /* Used by PM_DSS_DSS_WKDEP */ 1755 #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 1756 #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) 1757 1758 /* Used by PM_DSS_DSS_WKDEP */ 1759 #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 1760 #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) 1761 1762 /* Used by PM_DSS_DSS_WKDEP */ 1763 #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 1764 #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) 1765 1766 /* Used by PM_DSS_DSS_WKDEP */ 1767 #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 1768 #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) 1769 1770 /* Used by PM_L4PER_HECC1_WKDEP */ 1771 #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 1772 #define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) 1773 1774 /* Used by PM_L4PER_HECC2_WKDEP */ 1775 #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 1776 #define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) 1777 1778 /* Used by PM_L3INIT_HSI_WKDEP */ 1779 #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 1780 #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) 1781 1782 /* Used by PM_L3INIT_HSI_WKDEP */ 1783 #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 1784 #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) 1785 1786 /* Used by PM_L3INIT_HSI_WKDEP */ 1787 #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 1788 #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) 1789 1790 /* Used by PM_L4PER_I2C1_WKDEP */ 1791 #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 1792 #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) 1793 1794 /* Used by PM_L4PER_I2C1_WKDEP */ 1795 #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 1796 #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) 1797 1798 /* Used by PM_L4PER_I2C1_WKDEP */ 1799 #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 1800 #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) 1801 1802 /* Used by PM_L4PER_I2C2_WKDEP */ 1803 #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 1804 #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) 1805 1806 /* Used by PM_L4PER_I2C2_WKDEP */ 1807 #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 1808 #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) 1809 1810 /* Used by PM_L4PER_I2C2_WKDEP */ 1811 #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 1812 #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) 1813 1814 /* Used by PM_L4PER_I2C3_WKDEP */ 1815 #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 1816 #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) 1817 1818 /* Used by PM_L4PER_I2C3_WKDEP */ 1819 #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 1820 #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) 1821 1822 /* Used by PM_L4PER_I2C3_WKDEP */ 1823 #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 1824 #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) 1825 1826 /* Used by PM_L4PER_I2C4_WKDEP */ 1827 #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 1828 #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) 1829 1830 /* Used by PM_L4PER_I2C4_WKDEP */ 1831 #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 1832 #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) 1833 1834 /* Used by PM_L4PER_I2C4_WKDEP */ 1835 #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 1836 #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) 1837 1838 /* Used by PM_L4PER_I2C5_WKDEP */ 1839 #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 1840 #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) 1841 1842 /* Used by PM_L4PER_I2C5_WKDEP */ 1843 #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 1844 #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) 1845 1846 /* Used by PM_WKUP_KEYBOARD_WKDEP */ 1847 #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 1848 #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) 1849 1850 /* Used by PM_ABE_MCASP_WKDEP */ 1851 #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 1852 #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) 1853 1854 /* Used by PM_ABE_MCASP_WKDEP */ 1855 #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 1856 #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) 1857 1858 /* Used by PM_ABE_MCASP_WKDEP */ 1859 #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 1860 #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) 1861 1862 /* Used by PM_ABE_MCASP_WKDEP */ 1863 #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 1864 #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) 1865 1866 /* Used by PM_L4PER_MCASP2_WKDEP */ 1867 #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 1868 #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) 1869 1870 /* Used by PM_L4PER_MCASP2_WKDEP */ 1871 #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 1872 #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) 1873 1874 /* Used by PM_L4PER_MCASP2_WKDEP */ 1875 #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 1876 #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) 1877 1878 /* Used by PM_L4PER_MCASP2_WKDEP */ 1879 #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 1880 #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) 1881 1882 /* Used by PM_L4PER_MCASP3_WKDEP */ 1883 #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 1884 #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) 1885 1886 /* Used by PM_L4PER_MCASP3_WKDEP */ 1887 #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 1888 #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) 1889 1890 /* Used by PM_L4PER_MCASP3_WKDEP */ 1891 #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 1892 #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) 1893 1894 /* Used by PM_L4PER_MCASP3_WKDEP */ 1895 #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 1896 #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) 1897 1898 /* Used by PM_ABE_MCBSP1_WKDEP */ 1899 #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 1900 #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) 1901 1902 /* Used by PM_ABE_MCBSP1_WKDEP */ 1903 #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 1904 #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) 1905 1906 /* Used by PM_ABE_MCBSP1_WKDEP */ 1907 #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 1908 #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) 1909 1910 /* Used by PM_ABE_MCBSP2_WKDEP */ 1911 #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 1912 #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) 1913 1914 /* Used by PM_ABE_MCBSP2_WKDEP */ 1915 #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 1916 #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) 1917 1918 /* Used by PM_ABE_MCBSP2_WKDEP */ 1919 #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 1920 #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) 1921 1922 /* Used by PM_ABE_MCBSP3_WKDEP */ 1923 #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 1924 #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) 1925 1926 /* Used by PM_ABE_MCBSP3_WKDEP */ 1927 #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 1928 #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) 1929 1930 /* Used by PM_ABE_MCBSP3_WKDEP */ 1931 #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 1932 #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) 1933 1934 /* Used by PM_L4PER_MCBSP4_WKDEP */ 1935 #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 1936 #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) 1937 1938 /* Used by PM_L4PER_MCBSP4_WKDEP */ 1939 #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 1940 #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) 1941 1942 /* Used by PM_L4PER_MCBSP4_WKDEP */ 1943 #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 1944 #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) 1945 1946 /* Used by PM_L4PER_MCSPI1_WKDEP */ 1947 #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 1948 #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) 1949 1950 /* Used by PM_L4PER_MCSPI1_WKDEP */ 1951 #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 1952 #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) 1953 1954 /* Used by PM_L4PER_MCSPI1_WKDEP */ 1955 #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 1956 #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) 1957 1958 /* Used by PM_L4PER_MCSPI1_WKDEP */ 1959 #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 1960 #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) 1961 1962 /* Used by PM_L4PER_MCSPI2_WKDEP */ 1963 #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 1964 #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) 1965 1966 /* Used by PM_L4PER_MCSPI2_WKDEP */ 1967 #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 1968 #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) 1969 1970 /* Used by PM_L4PER_MCSPI2_WKDEP */ 1971 #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 1972 #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) 1973 1974 /* Used by PM_L4PER_MCSPI3_WKDEP */ 1975 #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 1976 #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) 1977 1978 /* Used by PM_L4PER_MCSPI3_WKDEP */ 1979 #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 1980 #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) 1981 1982 /* Used by PM_L4PER_MCSPI4_WKDEP */ 1983 #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 1984 #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) 1985 1986 /* Used by PM_L4PER_MCSPI4_WKDEP */ 1987 #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 1988 #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) 1989 1990 /* Used by PM_L3INIT_MMC1_WKDEP */ 1991 #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 1992 #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) 1993 1994 /* Used by PM_L3INIT_MMC1_WKDEP */ 1995 #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 1996 #define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) 1997 1998 /* Used by PM_L3INIT_MMC1_WKDEP */ 1999 #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 2000 #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) 2001 2002 /* Used by PM_L3INIT_MMC1_WKDEP */ 2003 #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 2004 #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) 2005 2006 /* Used by PM_L3INIT_MMC2_WKDEP */ 2007 #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 2008 #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) 2009 2010 /* Used by PM_L3INIT_MMC2_WKDEP */ 2011 #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 2012 #define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) 2013 2014 /* Used by PM_L3INIT_MMC2_WKDEP */ 2015 #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 2016 #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) 2017 2018 /* Used by PM_L3INIT_MMC2_WKDEP */ 2019 #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 2020 #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) 2021 2022 /* Used by PM_L3INIT_MMC6_WKDEP */ 2023 #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 2024 #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) 2025 2026 /* Used by PM_L3INIT_MMC6_WKDEP */ 2027 #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 2028 #define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) 2029 2030 /* Used by PM_L3INIT_MMC6_WKDEP */ 2031 #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 2032 #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) 2033 2034 /* Used by PM_L4PER_MMCSD3_WKDEP */ 2035 #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 2036 #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) 2037 2038 /* Used by PM_L4PER_MMCSD3_WKDEP */ 2039 #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 2040 #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) 2041 2042 /* Used by PM_L4PER_MMCSD3_WKDEP */ 2043 #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 2044 #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) 2045 2046 /* Used by PM_L4PER_MMCSD4_WKDEP */ 2047 #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 2048 #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) 2049 2050 /* Used by PM_L4PER_MMCSD4_WKDEP */ 2051 #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 2052 #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) 2053 2054 /* Used by PM_L4PER_MMCSD4_WKDEP */ 2055 #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 2056 #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) 2057 2058 /* Used by PM_L4PER_MMCSD5_WKDEP */ 2059 #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 2060 #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) 2061 2062 /* Used by PM_L4PER_MMCSD5_WKDEP */ 2063 #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 2064 #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) 2065 2066 /* Used by PM_L4PER_MMCSD5_WKDEP */ 2067 #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 2068 #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) 2069 2070 /* Used by PM_L3INIT_PCIESS_WKDEP */ 2071 #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 2072 #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) 2073 2074 /* Used by PM_L3INIT_PCIESS_WKDEP */ 2075 #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 2076 #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) 2077 2078 /* Used by PM_ABE_PDM_WKDEP */ 2079 #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 2080 #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) 2081 2082 /* Used by PM_ABE_PDM_WKDEP */ 2083 #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 2084 #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) 2085 2086 /* Used by PM_ABE_PDM_WKDEP */ 2087 #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 2088 #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) 2089 2090 /* Used by PM_ABE_PDM_WKDEP */ 2091 #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 2092 #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) 2093 2094 /* Used by PM_WKUP_RTC_WKDEP */ 2095 #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 2096 #define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) 2097 2098 /* Used by PM_L3INIT_SATA_WKDEP */ 2099 #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 2100 #define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) 2101 2102 /* Used by PM_L3INIT_SATA_WKDEP */ 2103 #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 2104 #define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) 2105 2106 /* Used by PM_ABE_SLIMBUS_WKDEP */ 2107 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 2108 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) 2109 2110 /* Used by PM_ABE_SLIMBUS_WKDEP */ 2111 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 2112 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) 2113 2114 /* Used by PM_ABE_SLIMBUS_WKDEP */ 2115 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 2116 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) 2117 2118 /* Used by PM_ABE_SLIMBUS_WKDEP */ 2119 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 2120 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) 2121 2122 /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 2123 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 2124 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) 2125 2126 /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 2127 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 2128 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) 2129 2130 /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 2131 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 2132 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) 2133 2134 /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 2135 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 2136 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) 2137 2138 /* Used by PM_ALWON_SR_CORE_WKDEP */ 2139 #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 2140 #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) 2141 2142 /* Used by PM_ALWON_SR_CORE_WKDEP */ 2143 #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 2144 #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) 2145 2146 /* Used by PM_ALWON_SR_IVA_WKDEP */ 2147 #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 2148 #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) 2149 2150 /* Used by PM_ALWON_SR_IVA_WKDEP */ 2151 #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 2152 #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) 2153 2154 /* Used by PM_ALWON_SR_MPU_WKDEP */ 2155 #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 2156 #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) 2157 2158 /* Used by PM_WKUP_TIMER12_WKDEP */ 2159 #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 2160 #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) 2161 2162 /* Used by PM_WKUP_TIMER1_WKDEP */ 2163 #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 2164 #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) 2165 2166 /* Used by PM_ABE_TIMER5_WKDEP */ 2167 #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 2168 #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) 2169 2170 /* Used by PM_ABE_TIMER5_WKDEP */ 2171 #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 2172 #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) 2173 2174 /* Used by PM_ABE_TIMER6_WKDEP */ 2175 #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 2176 #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) 2177 2178 /* Used by PM_ABE_TIMER6_WKDEP */ 2179 #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 2180 #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) 2181 2182 /* Used by PM_ABE_TIMER7_WKDEP */ 2183 #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 2184 #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) 2185 2186 /* Used by PM_ABE_TIMER7_WKDEP */ 2187 #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 2188 #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) 2189 2190 /* Used by PM_ABE_TIMER8_WKDEP */ 2191 #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 2192 #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) 2193 2194 /* Used by PM_ABE_TIMER8_WKDEP */ 2195 #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 2196 #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) 2197 2198 /* Used by PM_L4PER_UART1_WKDEP */ 2199 #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 2200 #define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) 2201 2202 /* Used by PM_L4PER_UART1_WKDEP */ 2203 #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 2204 #define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) 2205 2206 /* Used by PM_L4PER_UART2_WKDEP */ 2207 #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 2208 #define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) 2209 2210 /* Used by PM_L4PER_UART2_WKDEP */ 2211 #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 2212 #define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) 2213 2214 /* Used by PM_L4PER_UART3_WKDEP */ 2215 #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 2216 #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) 2217 2218 /* Used by PM_L4PER_UART3_WKDEP */ 2219 #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 2220 #define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) 2221 2222 /* Used by PM_L4PER_UART3_WKDEP */ 2223 #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 2224 #define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) 2225 2226 /* Used by PM_L4PER_UART3_WKDEP */ 2227 #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 2228 #define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) 2229 2230 /* Used by PM_L4PER_UART4_WKDEP */ 2231 #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 2232 #define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) 2233 2234 /* Used by PM_L4PER_UART4_WKDEP */ 2235 #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 2236 #define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) 2237 2238 /* Used by PM_L3INIT_UNIPRO1_WKDEP */ 2239 #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 2240 #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) 2241 2242 /* Used by PM_L3INIT_UNIPRO1_WKDEP */ 2243 #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 2244 #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) 2245 2246 /* Used by PM_L3INIT_USB_HOST_WKDEP */ 2247 #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 2248 #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) 2249 2250 /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ 2251 #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 2252 #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) 2253 2254 /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ 2255 #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 2256 #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) 2257 2258 /* Used by PM_L3INIT_USB_HOST_WKDEP */ 2259 #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 2260 #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) 2261 2262 /* Used by PM_L3INIT_USB_OTG_WKDEP */ 2263 #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 2264 #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) 2265 2266 /* Used by PM_L3INIT_USB_OTG_WKDEP */ 2267 #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 2268 #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) 2269 2270 /* Used by PM_L3INIT_USB_TLL_WKDEP */ 2271 #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 2272 #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) 2273 2274 /* Used by PM_L3INIT_USB_TLL_WKDEP */ 2275 #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 2276 #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) 2277 2278 /* Used by PM_WKUP_USIM_WKDEP */ 2279 #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 2280 #define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) 2281 2282 /* Used by PM_WKUP_USIM_WKDEP */ 2283 #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 2284 #define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) 2285 2286 /* Used by PM_WKUP_WDT2_WKDEP */ 2287 #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 2288 #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) 2289 2290 /* Used by PM_WKUP_WDT2_WKDEP */ 2291 #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 2292 #define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) 2293 2294 /* Used by PM_ABE_WDT3_WKDEP */ 2295 #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 2296 #define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) 2297 2298 /* Used by PM_L3INIT_HSI_WKDEP */ 2299 #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 2300 #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) 2301 2302 /* Used by PM_L3INIT_XHPI_WKDEP */ 2303 #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 2304 #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) 2305 2306 /* Used by PRM_IO_PMCTRL */ 2307 #define OMAP4430_WUCLK_CTRL_SHIFT 8 2308 #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) 2309 2310 /* Used by PRM_IO_PMCTRL */ 2311 #define OMAP4430_WUCLK_STATUS_SHIFT 9 2312 #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) 2313 2314 /* Used by REVISION_PRM */ 2315 #define OMAP4430_X_MAJOR_SHIFT 8 2316 #define OMAP4430_X_MAJOR_MASK (0x7 << 8) 2317 2318 /* Used by REVISION_PRM */ 2319 #define OMAP4430_Y_MINOR_SHIFT 0 2320 #define OMAP4430_Y_MINOR_MASK (0x3f << 0) 2321 #endif 2322