1234f0c4cSRajendra Nayak /* 2234f0c4cSRajendra Nayak * OMAP44xx Power Management register bits 3234f0c4cSRajendra Nayak * 4234f0c4cSRajendra Nayak * Copyright (C) 2009 Texas Instruments, Inc. 5234f0c4cSRajendra Nayak * Copyright (C) 2009 Nokia Corporation 6234f0c4cSRajendra Nayak * 7234f0c4cSRajendra Nayak * Paul Walmsley (paul@pwsan.com) 8234f0c4cSRajendra Nayak * Rajendra Nayak (rnayak@ti.com) 9234f0c4cSRajendra Nayak * Benoit Cousson (b-cousson@ti.com) 10234f0c4cSRajendra Nayak * 11234f0c4cSRajendra Nayak * This file is automatically generated from the OMAP hardware databases. 12234f0c4cSRajendra Nayak * We respectfully ask that any modifications to this file be coordinated 13234f0c4cSRajendra Nayak * with the public linux-omap@vger.kernel.org mailing list and the 14234f0c4cSRajendra Nayak * authors above to ensure that the autogeneration scripts are kept 15234f0c4cSRajendra Nayak * up-to-date with the file contents. 16234f0c4cSRajendra Nayak * 17234f0c4cSRajendra Nayak * This program is free software; you can redistribute it and/or modify 18234f0c4cSRajendra Nayak * it under the terms of the GNU General Public License version 2 as 19234f0c4cSRajendra Nayak * published by the Free Software Foundation. 20234f0c4cSRajendra Nayak */ 21234f0c4cSRajendra Nayak 22234f0c4cSRajendra Nayak #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 23234f0c4cSRajendra Nayak #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 24234f0c4cSRajendra Nayak 25234f0c4cSRajendra Nayak #include "prm.h" 26234f0c4cSRajendra Nayak 27234f0c4cSRajendra Nayak 28234f0c4cSRajendra Nayak /* 29234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 30234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 31234f0c4cSRajendra Nayak */ 3256ef28acSRajendra Nayak #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 33234f0c4cSRajendra Nayak #define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) 34234f0c4cSRajendra Nayak 35234f0c4cSRajendra Nayak /* 36234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 37234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 38234f0c4cSRajendra Nayak */ 3956ef28acSRajendra Nayak #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 40234f0c4cSRajendra Nayak #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) 41234f0c4cSRajendra Nayak 42234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 4356ef28acSRajendra Nayak #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 44234f0c4cSRajendra Nayak #define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) 45234f0c4cSRajendra Nayak 46234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 4756ef28acSRajendra Nayak #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 48234f0c4cSRajendra Nayak #define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) 49234f0c4cSRajendra Nayak 50234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 5156ef28acSRajendra Nayak #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 52234f0c4cSRajendra Nayak #define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) 53234f0c4cSRajendra Nayak 54234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 5556ef28acSRajendra Nayak #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 56234f0c4cSRajendra Nayak #define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) 57234f0c4cSRajendra Nayak 58234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 5956ef28acSRajendra Nayak #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 60234f0c4cSRajendra Nayak #define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) 61234f0c4cSRajendra Nayak 62234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 6356ef28acSRajendra Nayak #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 64234f0c4cSRajendra Nayak #define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) 65234f0c4cSRajendra Nayak 66234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTCTRL */ 6756ef28acSRajendra Nayak #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 68234f0c4cSRajendra Nayak #define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) 69234f0c4cSRajendra Nayak 70234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTCTRL */ 7156ef28acSRajendra Nayak #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 72234f0c4cSRajendra Nayak #define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) 73234f0c4cSRajendra Nayak 74234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTST */ 7556ef28acSRajendra Nayak #define OMAP4430_AESSMEM_STATEST_SHIFT 4 76234f0c4cSRajendra Nayak #define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) 77234f0c4cSRajendra Nayak 78234f0c4cSRajendra Nayak /* 79234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 80234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 81234f0c4cSRajendra Nayak */ 8256ef28acSRajendra Nayak #define OMAP4430_AIPOFF_SHIFT 8 83234f0c4cSRajendra Nayak #define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) 84234f0c4cSRajendra Nayak 85234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 8656ef28acSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 87234f0c4cSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) 88234f0c4cSRajendra Nayak 89234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 9056ef28acSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 91234f0c4cSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) 92234f0c4cSRajendra Nayak 93234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 9456ef28acSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 95234f0c4cSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) 96234f0c4cSRajendra Nayak 97234f0c4cSRajendra Nayak /* Used by PM_CAM_PWRSTCTRL */ 9856ef28acSRajendra Nayak #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 99234f0c4cSRajendra Nayak #define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) 100234f0c4cSRajendra Nayak 101234f0c4cSRajendra Nayak /* Used by PM_CAM_PWRSTST */ 10256ef28acSRajendra Nayak #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 103234f0c4cSRajendra Nayak #define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) 104234f0c4cSRajendra Nayak 105234f0c4cSRajendra Nayak /* Used by PRM_CLKREQCTRL */ 10656ef28acSRajendra Nayak #define OMAP4430_CLKREQ_COND_SHIFT 0 107234f0c4cSRajendra Nayak #define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) 108234f0c4cSRajendra Nayak 109234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_CMD */ 11056ef28acSRajendra Nayak #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 111234f0c4cSRajendra Nayak #define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) 112234f0c4cSRajendra Nayak 113234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_CMD */ 11456ef28acSRajendra Nayak #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 115234f0c4cSRajendra Nayak #define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) 116234f0c4cSRajendra Nayak 117234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_CMD */ 11856ef28acSRajendra Nayak #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 119234f0c4cSRajendra Nayak #define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) 120234f0c4cSRajendra Nayak 121234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 12256ef28acSRajendra Nayak #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 123234f0c4cSRajendra Nayak #define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) 124234f0c4cSRajendra Nayak 125234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 12656ef28acSRajendra Nayak #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 127234f0c4cSRajendra Nayak #define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) 128234f0c4cSRajendra Nayak 129234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 13056ef28acSRajendra Nayak #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 131234f0c4cSRajendra Nayak #define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) 132234f0c4cSRajendra Nayak 133234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 13456ef28acSRajendra Nayak #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 135234f0c4cSRajendra Nayak #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) 136234f0c4cSRajendra Nayak 137234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 13856ef28acSRajendra Nayak #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 139234f0c4cSRajendra Nayak #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) 140234f0c4cSRajendra Nayak 141234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTST */ 14256ef28acSRajendra Nayak #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 143234f0c4cSRajendra Nayak #define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) 144234f0c4cSRajendra Nayak 145234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 14656ef28acSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 147234f0c4cSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) 148234f0c4cSRajendra Nayak 149234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 15056ef28acSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 151234f0c4cSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) 152234f0c4cSRajendra Nayak 153234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTST */ 15456ef28acSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 155234f0c4cSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) 156234f0c4cSRajendra Nayak 157234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_BYPASS */ 15856ef28acSRajendra Nayak #define OMAP4430_DATA_SHIFT 16 159234f0c4cSRajendra Nayak #define OMAP4430_DATA_MASK BITFIELD(16, 23) 160234f0c4cSRajendra Nayak 161234f0c4cSRajendra Nayak /* Used by PRM_DEVICE_OFF_CTRL */ 16256ef28acSRajendra Nayak #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 163234f0c4cSRajendra Nayak #define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) 164234f0c4cSRajendra Nayak 165234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_MODE */ 16656ef28acSRajendra Nayak #define OMAP4430_DFILTEREN_SHIFT 6 167234f0c4cSRajendra Nayak #define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) 168234f0c4cSRajendra Nayak 169234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ 17056ef28acSRajendra Nayak #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 171234f0c4cSRajendra Nayak #define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) 172234f0c4cSRajendra Nayak 173234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ 17456ef28acSRajendra Nayak #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 175234f0c4cSRajendra Nayak #define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) 176234f0c4cSRajendra Nayak 177234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 17856ef28acSRajendra Nayak #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 179234f0c4cSRajendra Nayak #define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) 180234f0c4cSRajendra Nayak 181234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 18256ef28acSRajendra Nayak #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 183234f0c4cSRajendra Nayak #define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) 184234f0c4cSRajendra Nayak 185234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU */ 18656ef28acSRajendra Nayak #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 187234f0c4cSRajendra Nayak #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) 188234f0c4cSRajendra Nayak 189234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU */ 19056ef28acSRajendra Nayak #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 191234f0c4cSRajendra Nayak #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) 192234f0c4cSRajendra Nayak 193234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ 19456ef28acSRajendra Nayak #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 195234f0c4cSRajendra Nayak #define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) 196234f0c4cSRajendra Nayak 197234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ 19856ef28acSRajendra Nayak #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 199234f0c4cSRajendra Nayak #define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) 200234f0c4cSRajendra Nayak 201234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU */ 20256ef28acSRajendra Nayak #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 203234f0c4cSRajendra Nayak #define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) 204234f0c4cSRajendra Nayak 205234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU */ 20656ef28acSRajendra Nayak #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 207234f0c4cSRajendra Nayak #define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) 208234f0c4cSRajendra Nayak 209234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 21056ef28acSRajendra Nayak #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 211234f0c4cSRajendra Nayak #define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) 212234f0c4cSRajendra Nayak 213234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 21456ef28acSRajendra Nayak #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 215234f0c4cSRajendra Nayak #define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) 216234f0c4cSRajendra Nayak 217234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 21856ef28acSRajendra Nayak #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 219234f0c4cSRajendra Nayak #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) 220234f0c4cSRajendra Nayak 221234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 22256ef28acSRajendra Nayak #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 223234f0c4cSRajendra Nayak #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) 224234f0c4cSRajendra Nayak 225234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU */ 22656ef28acSRajendra Nayak #define OMAP4430_DPLL_USB_RECAL_EN_SHIFT 5 227234f0c4cSRajendra Nayak #define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5) 228234f0c4cSRajendra Nayak 229234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU */ 23056ef28acSRajendra Nayak #define OMAP4430_DPLL_USB_RECAL_ST_SHIFT 5 231234f0c4cSRajendra Nayak #define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5) 232234f0c4cSRajendra Nayak 233234f0c4cSRajendra Nayak /* Used by PM_DSS_PWRSTCTRL */ 23456ef28acSRajendra Nayak #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 235234f0c4cSRajendra Nayak #define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) 236234f0c4cSRajendra Nayak 237234f0c4cSRajendra Nayak /* Used by PM_DSS_PWRSTCTRL */ 23856ef28acSRajendra Nayak #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 239234f0c4cSRajendra Nayak #define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) 240234f0c4cSRajendra Nayak 241234f0c4cSRajendra Nayak /* Used by PM_DSS_PWRSTST */ 24256ef28acSRajendra Nayak #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 243234f0c4cSRajendra Nayak #define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) 244234f0c4cSRajendra Nayak 245234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 24656ef28acSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 247234f0c4cSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) 248234f0c4cSRajendra Nayak 249234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 25056ef28acSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 251234f0c4cSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) 252234f0c4cSRajendra Nayak 253234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTST */ 25456ef28acSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 255234f0c4cSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) 256234f0c4cSRajendra Nayak 257234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 25856ef28acSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 259234f0c4cSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) 260234f0c4cSRajendra Nayak 261234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 26256ef28acSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 263234f0c4cSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) 264234f0c4cSRajendra Nayak 265234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTST */ 26656ef28acSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 267234f0c4cSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) 268234f0c4cSRajendra Nayak 269234f0c4cSRajendra Nayak /* Used by RM_MPU_RSTST */ 27056ef28acSRajendra Nayak #define OMAP4430_EMULATION_RST_SHIFT 0 271234f0c4cSRajendra Nayak #define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) 272234f0c4cSRajendra Nayak 273234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTST */ 27456ef28acSRajendra Nayak #define OMAP4430_EMULATION_RST1ST_SHIFT 3 275234f0c4cSRajendra Nayak #define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) 276234f0c4cSRajendra Nayak 277234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTST */ 27856ef28acSRajendra Nayak #define OMAP4430_EMULATION_RST2ST_SHIFT 4 279234f0c4cSRajendra Nayak #define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) 280234f0c4cSRajendra Nayak 281234f0c4cSRajendra Nayak /* Used by RM_IVAHD_RSTST */ 28256ef28acSRajendra Nayak #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 283234f0c4cSRajendra Nayak #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) 284234f0c4cSRajendra Nayak 285234f0c4cSRajendra Nayak /* Used by RM_IVAHD_RSTST */ 28656ef28acSRajendra Nayak #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 287234f0c4cSRajendra Nayak #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) 288234f0c4cSRajendra Nayak 289234f0c4cSRajendra Nayak /* Used by PM_EMU_PWRSTCTRL */ 29056ef28acSRajendra Nayak #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 291234f0c4cSRajendra Nayak #define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) 292234f0c4cSRajendra Nayak 293234f0c4cSRajendra Nayak /* Used by PM_EMU_PWRSTST */ 29456ef28acSRajendra Nayak #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 295234f0c4cSRajendra Nayak #define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) 296234f0c4cSRajendra Nayak 297234f0c4cSRajendra Nayak /* 298234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 299234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP 300234f0c4cSRajendra Nayak */ 30156ef28acSRajendra Nayak #define OMAP4430_ENABLE_RTA_EXPORT_SHIFT 0 302234f0c4cSRajendra Nayak #define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0) 303234f0c4cSRajendra Nayak 304234f0c4cSRajendra Nayak /* 305234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 306234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 307234f0c4cSRajendra Nayak */ 30856ef28acSRajendra Nayak #define OMAP4430_ENFUNC1_SHIFT 3 309234f0c4cSRajendra Nayak #define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) 310234f0c4cSRajendra Nayak 311234f0c4cSRajendra Nayak /* 312234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 313234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 314234f0c4cSRajendra Nayak */ 31556ef28acSRajendra Nayak #define OMAP4430_ENFUNC3_SHIFT 5 316234f0c4cSRajendra Nayak #define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) 317234f0c4cSRajendra Nayak 318234f0c4cSRajendra Nayak /* 319234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 320234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 321234f0c4cSRajendra Nayak */ 32256ef28acSRajendra Nayak #define OMAP4430_ENFUNC4_SHIFT 6 323234f0c4cSRajendra Nayak #define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) 324234f0c4cSRajendra Nayak 325234f0c4cSRajendra Nayak /* 326234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 327234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 328234f0c4cSRajendra Nayak */ 32956ef28acSRajendra Nayak #define OMAP4430_ENFUNC5_SHIFT 7 330234f0c4cSRajendra Nayak #define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) 331234f0c4cSRajendra Nayak 332234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 33356ef28acSRajendra Nayak #define OMAP4430_ERRORGAIN_SHIFT 16 334234f0c4cSRajendra Nayak #define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) 335234f0c4cSRajendra Nayak 336234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 33756ef28acSRajendra Nayak #define OMAP4430_ERROROFFSET_SHIFT 24 338234f0c4cSRajendra Nayak #define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) 339234f0c4cSRajendra Nayak 340234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 34156ef28acSRajendra Nayak #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 342234f0c4cSRajendra Nayak #define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) 343234f0c4cSRajendra Nayak 344234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 34556ef28acSRajendra Nayak #define OMAP4430_FORCEUPDATE_SHIFT 1 346234f0c4cSRajendra Nayak #define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) 347234f0c4cSRajendra Nayak 348234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ 34956ef28acSRajendra Nayak #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 350234f0c4cSRajendra Nayak #define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) 351234f0c4cSRajendra Nayak 352234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ 35356ef28acSRajendra Nayak #define OMAP4430_FORCEWKUP_EN_SHIFT 10 354234f0c4cSRajendra Nayak #define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) 355234f0c4cSRajendra Nayak 356234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ 35756ef28acSRajendra Nayak #define OMAP4430_FORCEWKUP_ST_SHIFT 10 358234f0c4cSRajendra Nayak #define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) 359234f0c4cSRajendra Nayak 360234f0c4cSRajendra Nayak /* Used by PM_GFX_PWRSTCTRL */ 36156ef28acSRajendra Nayak #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 362234f0c4cSRajendra Nayak #define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) 363234f0c4cSRajendra Nayak 364234f0c4cSRajendra Nayak /* Used by PM_GFX_PWRSTST */ 36556ef28acSRajendra Nayak #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 366234f0c4cSRajendra Nayak #define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) 367234f0c4cSRajendra Nayak 368234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 36956ef28acSRajendra Nayak #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 370234f0c4cSRajendra Nayak #define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) 371234f0c4cSRajendra Nayak 372234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 37356ef28acSRajendra Nayak #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 374234f0c4cSRajendra Nayak #define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) 375234f0c4cSRajendra Nayak 376234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 37756ef28acSRajendra Nayak #define OMAP4430_GLOBAL_WUEN_SHIFT 16 378234f0c4cSRajendra Nayak #define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) 379234f0c4cSRajendra Nayak 380234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_MODE */ 38156ef28acSRajendra Nayak #define OMAP4430_HSMCODE_SHIFT 0 382234f0c4cSRajendra Nayak #define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) 383234f0c4cSRajendra Nayak 384234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_MODE */ 38556ef28acSRajendra Nayak #define OMAP4430_HSMODEEN_SHIFT 3 386234f0c4cSRajendra Nayak #define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) 387234f0c4cSRajendra Nayak 388234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_CLK */ 38956ef28acSRajendra Nayak #define OMAP4430_HSSCLH_SHIFT 16 390234f0c4cSRajendra Nayak #define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) 391234f0c4cSRajendra Nayak 392234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_CLK */ 39356ef28acSRajendra Nayak #define OMAP4430_HSSCLL_SHIFT 24 394234f0c4cSRajendra Nayak #define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) 395234f0c4cSRajendra Nayak 396234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 39756ef28acSRajendra Nayak #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 398234f0c4cSRajendra Nayak #define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) 399234f0c4cSRajendra Nayak 400234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 40156ef28acSRajendra Nayak #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 402234f0c4cSRajendra Nayak #define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) 403234f0c4cSRajendra Nayak 404234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTST */ 40556ef28acSRajendra Nayak #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 406234f0c4cSRajendra Nayak #define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) 407234f0c4cSRajendra Nayak 408234f0c4cSRajendra Nayak /* Used by RM_MPU_RSTST */ 40956ef28acSRajendra Nayak #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 410234f0c4cSRajendra Nayak #define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) 411234f0c4cSRajendra Nayak 412234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTST */ 41356ef28acSRajendra Nayak #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 414234f0c4cSRajendra Nayak #define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) 415234f0c4cSRajendra Nayak 416234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTST */ 41756ef28acSRajendra Nayak #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 418234f0c4cSRajendra Nayak #define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) 419234f0c4cSRajendra Nayak 420234f0c4cSRajendra Nayak /* Used by RM_IVAHD_RSTST */ 42156ef28acSRajendra Nayak #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 422234f0c4cSRajendra Nayak #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) 423234f0c4cSRajendra Nayak 424234f0c4cSRajendra Nayak /* Used by RM_IVAHD_RSTST */ 42556ef28acSRajendra Nayak #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 426234f0c4cSRajendra Nayak #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) 427234f0c4cSRajendra Nayak 428234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 42956ef28acSRajendra Nayak #define OMAP4430_ICEPICK_RST_SHIFT 9 430234f0c4cSRajendra Nayak #define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) 431234f0c4cSRajendra Nayak 432234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 43356ef28acSRajendra Nayak #define OMAP4430_INITVDD_SHIFT 2 434234f0c4cSRajendra Nayak #define OMAP4430_INITVDD_MASK BITFIELD(2, 2) 435234f0c4cSRajendra Nayak 436234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 43756ef28acSRajendra Nayak #define OMAP4430_INITVOLTAGE_SHIFT 8 438234f0c4cSRajendra Nayak #define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) 439234f0c4cSRajendra Nayak 440234f0c4cSRajendra Nayak /* 441234f0c4cSRajendra Nayak * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, 442234f0c4cSRajendra Nayak * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, 443234f0c4cSRajendra Nayak * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST 444234f0c4cSRajendra Nayak */ 44556ef28acSRajendra Nayak #define OMAP4430_INTRANSITION_SHIFT 20 446234f0c4cSRajendra Nayak #define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) 447234f0c4cSRajendra Nayak 448234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 44956ef28acSRajendra Nayak #define OMAP4430_IO_EN_SHIFT 9 450234f0c4cSRajendra Nayak #define OMAP4430_IO_EN_MASK BITFIELD(9, 9) 451234f0c4cSRajendra Nayak 452234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 45356ef28acSRajendra Nayak #define OMAP4430_IO_ON_STATUS_SHIFT 5 454234f0c4cSRajendra Nayak #define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) 455234f0c4cSRajendra Nayak 456234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 45756ef28acSRajendra Nayak #define OMAP4430_IO_ST_SHIFT 9 458234f0c4cSRajendra Nayak #define OMAP4430_IO_ST_MASK BITFIELD(9, 9) 459234f0c4cSRajendra Nayak 460234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 46156ef28acSRajendra Nayak #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 462234f0c4cSRajendra Nayak #define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) 463234f0c4cSRajendra Nayak 464234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 46556ef28acSRajendra Nayak #define OMAP4430_ISOCLK_STATUS_SHIFT 1 466234f0c4cSRajendra Nayak #define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) 467234f0c4cSRajendra Nayak 468234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 46956ef28acSRajendra Nayak #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 470234f0c4cSRajendra Nayak #define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) 471234f0c4cSRajendra Nayak 472234f0c4cSRajendra Nayak /* Used by PRM_IO_COUNT */ 47356ef28acSRajendra Nayak #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 474234f0c4cSRajendra Nayak #define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) 475234f0c4cSRajendra Nayak 476234f0c4cSRajendra Nayak /* Used by PM_L3INIT_PWRSTCTRL */ 47756ef28acSRajendra Nayak #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 478234f0c4cSRajendra Nayak #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) 479234f0c4cSRajendra Nayak 480234f0c4cSRajendra Nayak /* Used by PM_L3INIT_PWRSTCTRL */ 48156ef28acSRajendra Nayak #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 482234f0c4cSRajendra Nayak #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) 483234f0c4cSRajendra Nayak 484234f0c4cSRajendra Nayak /* Used by PM_L3INIT_PWRSTST */ 48556ef28acSRajendra Nayak #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 486234f0c4cSRajendra Nayak #define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) 487234f0c4cSRajendra Nayak 488234f0c4cSRajendra Nayak /* 489234f0c4cSRajendra Nayak * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, 490234f0c4cSRajendra Nayak * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, 491234f0c4cSRajendra Nayak * PM_IVAHD_PWRSTCTRL 492234f0c4cSRajendra Nayak */ 49356ef28acSRajendra Nayak #define OMAP4430_LOGICRETSTATE_SHIFT 2 494234f0c4cSRajendra Nayak #define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) 495234f0c4cSRajendra Nayak 496234f0c4cSRajendra Nayak /* 497234f0c4cSRajendra Nayak * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, 498234f0c4cSRajendra Nayak * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, 499234f0c4cSRajendra Nayak * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST 500234f0c4cSRajendra Nayak */ 50156ef28acSRajendra Nayak #define OMAP4430_LOGICSTATEST_SHIFT 2 502234f0c4cSRajendra Nayak #define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) 503234f0c4cSRajendra Nayak 504234f0c4cSRajendra Nayak /* 505234f0c4cSRajendra Nayak * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, 506234f0c4cSRajendra Nayak * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, 507234f0c4cSRajendra Nayak * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, 508234f0c4cSRajendra Nayak * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT, 509234f0c4cSRajendra Nayak * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT, 510234f0c4cSRajendra Nayak * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, 511234f0c4cSRajendra Nayak * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT, 512234f0c4cSRajendra Nayak * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT, 513234f0c4cSRajendra Nayak * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT, 514234f0c4cSRajendra Nayak * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, 515234f0c4cSRajendra Nayak * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, 516234f0c4cSRajendra Nayak * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, 517234f0c4cSRajendra Nayak * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, 518234f0c4cSRajendra Nayak * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, 519234f0c4cSRajendra Nayak * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, 520234f0c4cSRajendra Nayak * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, 521234f0c4cSRajendra Nayak * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, 522234f0c4cSRajendra Nayak * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, 523234f0c4cSRajendra Nayak * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT, 524234f0c4cSRajendra Nayak * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, 525234f0c4cSRajendra Nayak * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, 526234f0c4cSRajendra Nayak * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT, 527234f0c4cSRajendra Nayak * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT, 528234f0c4cSRajendra Nayak * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT, 529234f0c4cSRajendra Nayak * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, 530234f0c4cSRajendra Nayak * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, 531234f0c4cSRajendra Nayak * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, 532234f0c4cSRajendra Nayak * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, 533234f0c4cSRajendra Nayak * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, 534234f0c4cSRajendra Nayak * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, 535234f0c4cSRajendra Nayak * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, 536234f0c4cSRajendra Nayak * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT, 537234f0c4cSRajendra Nayak * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, 538234f0c4cSRajendra Nayak * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT 539234f0c4cSRajendra Nayak */ 54056ef28acSRajendra Nayak #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 541234f0c4cSRajendra Nayak #define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) 542234f0c4cSRajendra Nayak 543234f0c4cSRajendra Nayak /* 544234f0c4cSRajendra Nayak * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, 545234f0c4cSRajendra Nayak * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, 546234f0c4cSRajendra Nayak * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, 547234f0c4cSRajendra Nayak * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, 548234f0c4cSRajendra Nayak * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, 549234f0c4cSRajendra Nayak * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, 550234f0c4cSRajendra Nayak * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT, 551234f0c4cSRajendra Nayak * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT, 552234f0c4cSRajendra Nayak * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT, 553234f0c4cSRajendra Nayak * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT, 554234f0c4cSRajendra Nayak * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, 555234f0c4cSRajendra Nayak * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT, 556234f0c4cSRajendra Nayak * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, 557234f0c4cSRajendra Nayak * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT, 558234f0c4cSRajendra Nayak * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT, 559234f0c4cSRajendra Nayak * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT 560234f0c4cSRajendra Nayak */ 56156ef28acSRajendra Nayak #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 562234f0c4cSRajendra Nayak #define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) 563234f0c4cSRajendra Nayak 564234f0c4cSRajendra Nayak /* Used by RM_ABE_AESS_CONTEXT */ 56556ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 566234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) 567234f0c4cSRajendra Nayak 568234f0c4cSRajendra Nayak /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ 56956ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 570234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) 571234f0c4cSRajendra Nayak 572234f0c4cSRajendra Nayak /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ 57356ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 574234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) 575234f0c4cSRajendra Nayak 576234f0c4cSRajendra Nayak /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ 57756ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 578234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) 579234f0c4cSRajendra Nayak 580234f0c4cSRajendra Nayak /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ 58156ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 582234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) 583234f0c4cSRajendra Nayak 584234f0c4cSRajendra Nayak /* 585234f0c4cSRajendra Nayak * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, 586234f0c4cSRajendra Nayak * RM_SDMA_SDMA_CONTEXT 587234f0c4cSRajendra Nayak */ 58856ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 589234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) 590234f0c4cSRajendra Nayak 591234f0c4cSRajendra Nayak /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ 59256ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 593234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) 594234f0c4cSRajendra Nayak 595234f0c4cSRajendra Nayak /* Used by RM_DUCATI_DUCATI_CONTEXT */ 59656ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 597234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) 598234f0c4cSRajendra Nayak 599234f0c4cSRajendra Nayak /* Used by RM_DUCATI_DUCATI_CONTEXT */ 60056ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 601234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) 602234f0c4cSRajendra Nayak 603234f0c4cSRajendra Nayak /* Used by RM_EMU_DEBUGSS_CONTEXT */ 60456ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 605234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) 606234f0c4cSRajendra Nayak 607234f0c4cSRajendra Nayak /* Used by RM_GFX_GFX_CONTEXT */ 60856ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 609234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) 610234f0c4cSRajendra Nayak 611234f0c4cSRajendra Nayak /* Used by RM_IVAHD_IVAHD_CONTEXT */ 61256ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 613234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) 614234f0c4cSRajendra Nayak 615234f0c4cSRajendra Nayak /* 616234f0c4cSRajendra Nayak * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, 617234f0c4cSRajendra Nayak * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, 618234f0c4cSRajendra Nayak * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT, 619234f0c4cSRajendra Nayak * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, 620234f0c4cSRajendra Nayak * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT 621234f0c4cSRajendra Nayak */ 62256ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 623234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) 624234f0c4cSRajendra Nayak 625234f0c4cSRajendra Nayak /* Used by RM_MPU_MPU_CONTEXT */ 62656ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 627234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) 628234f0c4cSRajendra Nayak 629234f0c4cSRajendra Nayak /* Used by RM_MPU_MPU_CONTEXT */ 63056ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 631234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) 632234f0c4cSRajendra Nayak 633234f0c4cSRajendra Nayak /* Used by RM_MPU_MPU_CONTEXT */ 63456ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 635234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) 636234f0c4cSRajendra Nayak 637234f0c4cSRajendra Nayak /* 638234f0c4cSRajendra Nayak * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, 639234f0c4cSRajendra Nayak * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, 640234f0c4cSRajendra Nayak * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT 641234f0c4cSRajendra Nayak */ 64256ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 643234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) 644234f0c4cSRajendra Nayak 645234f0c4cSRajendra Nayak /* 646234f0c4cSRajendra Nayak * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, 647234f0c4cSRajendra Nayak * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT 648234f0c4cSRajendra Nayak */ 64956ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 650234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) 651234f0c4cSRajendra Nayak 652234f0c4cSRajendra Nayak /* 653234f0c4cSRajendra Nayak * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, 654234f0c4cSRajendra Nayak * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, 655234f0c4cSRajendra Nayak * RM_L4SEC_CRYPTODMA_CONTEXT 656234f0c4cSRajendra Nayak */ 65756ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 658234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) 659234f0c4cSRajendra Nayak 660234f0c4cSRajendra Nayak /* Used by RM_IVAHD_SL2_CONTEXT */ 66156ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 662234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) 663234f0c4cSRajendra Nayak 664234f0c4cSRajendra Nayak /* Used by RM_IVAHD_IVAHD_CONTEXT */ 66556ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 666234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) 667234f0c4cSRajendra Nayak 668234f0c4cSRajendra Nayak /* Used by RM_IVAHD_IVAHD_CONTEXT */ 66956ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 670234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) 671234f0c4cSRajendra Nayak 672234f0c4cSRajendra Nayak /* Used by RM_TESLA_TESLA_CONTEXT */ 67356ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 674234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) 675234f0c4cSRajendra Nayak 676234f0c4cSRajendra Nayak /* Used by RM_TESLA_TESLA_CONTEXT */ 67756ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 678234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) 679234f0c4cSRajendra Nayak 680234f0c4cSRajendra Nayak /* Used by RM_TESLA_TESLA_CONTEXT */ 68156ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 682234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) 683234f0c4cSRajendra Nayak 684234f0c4cSRajendra Nayak /* Used by RM_WKUP_SARRAM_CONTEXT */ 68556ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 686234f0c4cSRajendra Nayak #define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) 687234f0c4cSRajendra Nayak 688234f0c4cSRajendra Nayak /* 689234f0c4cSRajendra Nayak * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, 690234f0c4cSRajendra Nayak * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, 691234f0c4cSRajendra Nayak * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL 692234f0c4cSRajendra Nayak */ 69356ef28acSRajendra Nayak #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 694234f0c4cSRajendra Nayak #define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) 695234f0c4cSRajendra Nayak 696234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 69756ef28acSRajendra Nayak #define OMAP4430_MEMORYCHANGE_SHIFT 3 698234f0c4cSRajendra Nayak #define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3) 699234f0c4cSRajendra Nayak 700234f0c4cSRajendra Nayak /* Used by PRM_MODEM_IF_CTRL */ 70156ef28acSRajendra Nayak #define OMAP4430_MODEM_READY_SHIFT 1 702234f0c4cSRajendra Nayak #define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) 703234f0c4cSRajendra Nayak 704234f0c4cSRajendra Nayak /* Used by PRM_MODEM_IF_CTRL */ 70556ef28acSRajendra Nayak #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 706234f0c4cSRajendra Nayak #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) 707234f0c4cSRajendra Nayak 708234f0c4cSRajendra Nayak /* Used by PRM_MODEM_IF_CTRL */ 70956ef28acSRajendra Nayak #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 710234f0c4cSRajendra Nayak #define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) 711234f0c4cSRajendra Nayak 712234f0c4cSRajendra Nayak /* Used by PRM_MODEM_IF_CTRL */ 71356ef28acSRajendra Nayak #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 714234f0c4cSRajendra Nayak #define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) 715234f0c4cSRajendra Nayak 716234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 71756ef28acSRajendra Nayak #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 718234f0c4cSRajendra Nayak #define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) 719234f0c4cSRajendra Nayak 720234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 72156ef28acSRajendra Nayak #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 722234f0c4cSRajendra Nayak #define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) 723234f0c4cSRajendra Nayak 724234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTST */ 72556ef28acSRajendra Nayak #define OMAP4430_MPU_L1_STATEST_SHIFT 4 726234f0c4cSRajendra Nayak #define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) 727234f0c4cSRajendra Nayak 728234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 72956ef28acSRajendra Nayak #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 730234f0c4cSRajendra Nayak #define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) 731234f0c4cSRajendra Nayak 732234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 73356ef28acSRajendra Nayak #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 734234f0c4cSRajendra Nayak #define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) 735234f0c4cSRajendra Nayak 736234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTST */ 73756ef28acSRajendra Nayak #define OMAP4430_MPU_L2_STATEST_SHIFT 6 738234f0c4cSRajendra Nayak #define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) 739234f0c4cSRajendra Nayak 740234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 74156ef28acSRajendra Nayak #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 742234f0c4cSRajendra Nayak #define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) 743234f0c4cSRajendra Nayak 744234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 74556ef28acSRajendra Nayak #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 746234f0c4cSRajendra Nayak #define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) 747234f0c4cSRajendra Nayak 748234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTST */ 74956ef28acSRajendra Nayak #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 750234f0c4cSRajendra Nayak #define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) 751234f0c4cSRajendra Nayak 752234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 75356ef28acSRajendra Nayak #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 754234f0c4cSRajendra Nayak #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) 755234f0c4cSRajendra Nayak 756234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 75756ef28acSRajendra Nayak #define OMAP4430_MPU_WDT_RST_SHIFT 3 758234f0c4cSRajendra Nayak #define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) 759234f0c4cSRajendra Nayak 760234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTCTRL */ 76156ef28acSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 762234f0c4cSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) 763234f0c4cSRajendra Nayak 764234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTCTRL */ 76556ef28acSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 766234f0c4cSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) 767234f0c4cSRajendra Nayak 768234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTST */ 76956ef28acSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 770234f0c4cSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) 771234f0c4cSRajendra Nayak 772234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 77356ef28acSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 774234f0c4cSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) 775234f0c4cSRajendra Nayak 776234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 77756ef28acSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 778234f0c4cSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) 779234f0c4cSRajendra Nayak 780234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTST */ 78156ef28acSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 782234f0c4cSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) 783234f0c4cSRajendra Nayak 784234f0c4cSRajendra Nayak /* 785234f0c4cSRajendra Nayak * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 786234f0c4cSRajendra Nayak * PRM_VC_VAL_CMD_VDD_MPU_L 787234f0c4cSRajendra Nayak */ 78856ef28acSRajendra Nayak #define OMAP4430_OFF_SHIFT 0 789234f0c4cSRajendra Nayak #define OMAP4430_OFF_MASK BITFIELD(0, 7) 790234f0c4cSRajendra Nayak 791234f0c4cSRajendra Nayak /* Used by PRM_LDO_BANDGAP_CTRL */ 79256ef28acSRajendra Nayak #define OMAP4430_OFF_ENABLE_SHIFT 0 793234f0c4cSRajendra Nayak #define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0) 794234f0c4cSRajendra Nayak 795234f0c4cSRajendra Nayak /* 796234f0c4cSRajendra Nayak * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 797234f0c4cSRajendra Nayak * PRM_VC_VAL_CMD_VDD_MPU_L 798234f0c4cSRajendra Nayak */ 79956ef28acSRajendra Nayak #define OMAP4430_ON_SHIFT 24 800234f0c4cSRajendra Nayak #define OMAP4430_ON_MASK BITFIELD(24, 31) 801234f0c4cSRajendra Nayak 802234f0c4cSRajendra Nayak /* 803234f0c4cSRajendra Nayak * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 804234f0c4cSRajendra Nayak * PRM_VC_VAL_CMD_VDD_MPU_L 805234f0c4cSRajendra Nayak */ 80656ef28acSRajendra Nayak #define OMAP4430_ONLP_SHIFT 16 807234f0c4cSRajendra Nayak #define OMAP4430_ONLP_MASK BITFIELD(16, 23) 808234f0c4cSRajendra Nayak 809234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 81056ef28acSRajendra Nayak #define OMAP4430_OPP_CHANGE_SHIFT 2 811234f0c4cSRajendra Nayak #define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) 812234f0c4cSRajendra Nayak 813234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 81456ef28acSRajendra Nayak #define OMAP4430_OPP_SEL_SHIFT 0 815234f0c4cSRajendra Nayak #define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) 816234f0c4cSRajendra Nayak 817234f0c4cSRajendra Nayak /* Used by PRM_SRAM_COUNT */ 81856ef28acSRajendra Nayak #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 819234f0c4cSRajendra Nayak #define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) 820234f0c4cSRajendra Nayak 821234f0c4cSRajendra Nayak /* Used by PRM_PSCON_COUNT */ 82256ef28acSRajendra Nayak #define OMAP4430_PCHARGE_TIME_SHIFT 0 823234f0c4cSRajendra Nayak #define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) 824234f0c4cSRajendra Nayak 825234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTCTRL */ 82656ef28acSRajendra Nayak #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 827234f0c4cSRajendra Nayak #define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) 828234f0c4cSRajendra Nayak 829234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTCTRL */ 83056ef28acSRajendra Nayak #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 831234f0c4cSRajendra Nayak #define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) 832234f0c4cSRajendra Nayak 833234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTST */ 83456ef28acSRajendra Nayak #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 835234f0c4cSRajendra Nayak #define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) 836234f0c4cSRajendra Nayak 837234f0c4cSRajendra Nayak /* Used by PRM_PHASE1_CNDP */ 83856ef28acSRajendra Nayak #define OMAP4430_PHASE1_CNDP_SHIFT 0 839234f0c4cSRajendra Nayak #define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) 840234f0c4cSRajendra Nayak 841234f0c4cSRajendra Nayak /* Used by PRM_PHASE2A_CNDP */ 84256ef28acSRajendra Nayak #define OMAP4430_PHASE2A_CNDP_SHIFT 0 843234f0c4cSRajendra Nayak #define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) 844234f0c4cSRajendra Nayak 845234f0c4cSRajendra Nayak /* Used by PRM_PHASE2B_CNDP */ 84656ef28acSRajendra Nayak #define OMAP4430_PHASE2B_CNDP_SHIFT 0 847234f0c4cSRajendra Nayak #define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) 848234f0c4cSRajendra Nayak 849234f0c4cSRajendra Nayak /* Used by PRM_PSCON_COUNT */ 85056ef28acSRajendra Nayak #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 851234f0c4cSRajendra Nayak #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) 852234f0c4cSRajendra Nayak 853234f0c4cSRajendra Nayak /* 854234f0c4cSRajendra Nayak * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, 855234f0c4cSRajendra Nayak * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, 856234f0c4cSRajendra Nayak * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, 857234f0c4cSRajendra Nayak * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL 858234f0c4cSRajendra Nayak */ 85956ef28acSRajendra Nayak #define OMAP4430_POWERSTATE_SHIFT 0 860234f0c4cSRajendra Nayak #define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) 861234f0c4cSRajendra Nayak 862234f0c4cSRajendra Nayak /* 863234f0c4cSRajendra Nayak * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, 864234f0c4cSRajendra Nayak * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, 865234f0c4cSRajendra Nayak * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST 866234f0c4cSRajendra Nayak */ 86756ef28acSRajendra Nayak #define OMAP4430_POWERSTATEST_SHIFT 0 868234f0c4cSRajendra Nayak #define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) 869234f0c4cSRajendra Nayak 870234f0c4cSRajendra Nayak /* Used by PRM_PWRREQCTRL */ 87156ef28acSRajendra Nayak #define OMAP4430_PWRREQ_COND_SHIFT 0 872234f0c4cSRajendra Nayak #define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) 873234f0c4cSRajendra Nayak 874234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 87556ef28acSRajendra Nayak #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 876234f0c4cSRajendra Nayak #define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) 877234f0c4cSRajendra Nayak 878234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 87956ef28acSRajendra Nayak #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 880234f0c4cSRajendra Nayak #define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) 881234f0c4cSRajendra Nayak 882234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 88356ef28acSRajendra Nayak #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 884234f0c4cSRajendra Nayak #define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) 885234f0c4cSRajendra Nayak 886234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 88756ef28acSRajendra Nayak #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 888234f0c4cSRajendra Nayak #define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) 889234f0c4cSRajendra Nayak 890234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 89156ef28acSRajendra Nayak #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 892234f0c4cSRajendra Nayak #define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) 893234f0c4cSRajendra Nayak 894234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 89556ef28acSRajendra Nayak #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 896234f0c4cSRajendra Nayak #define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) 897234f0c4cSRajendra Nayak 898234f0c4cSRajendra Nayak /* 899234f0c4cSRajendra Nayak * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 900234f0c4cSRajendra Nayak * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 901234f0c4cSRajendra Nayak * PRM_VOLTSETUP_MPU_RET_SLEEP 902234f0c4cSRajendra Nayak */ 90356ef28acSRajendra Nayak #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 904234f0c4cSRajendra Nayak #define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) 905234f0c4cSRajendra Nayak 906234f0c4cSRajendra Nayak /* 907234f0c4cSRajendra Nayak * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 908234f0c4cSRajendra Nayak * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 909234f0c4cSRajendra Nayak * PRM_VOLTSETUP_MPU_RET_SLEEP 910234f0c4cSRajendra Nayak */ 91156ef28acSRajendra Nayak #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 912234f0c4cSRajendra Nayak #define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) 913234f0c4cSRajendra Nayak 914234f0c4cSRajendra Nayak /* 915234f0c4cSRajendra Nayak * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 916234f0c4cSRajendra Nayak * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 917234f0c4cSRajendra Nayak * PRM_VOLTSETUP_MPU_RET_SLEEP 918234f0c4cSRajendra Nayak */ 91956ef28acSRajendra Nayak #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 920234f0c4cSRajendra Nayak #define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) 921234f0c4cSRajendra Nayak 922234f0c4cSRajendra Nayak /* 923234f0c4cSRajendra Nayak * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 924234f0c4cSRajendra Nayak * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 925234f0c4cSRajendra Nayak * PRM_VOLTSETUP_MPU_RET_SLEEP 926234f0c4cSRajendra Nayak */ 92756ef28acSRajendra Nayak #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 928234f0c4cSRajendra Nayak #define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) 929234f0c4cSRajendra Nayak 930234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 93156ef28acSRajendra Nayak #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 932234f0c4cSRajendra Nayak #define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) 933234f0c4cSRajendra Nayak 934234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 93556ef28acSRajendra Nayak #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 936234f0c4cSRajendra Nayak #define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) 937234f0c4cSRajendra Nayak 938234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 93956ef28acSRajendra Nayak #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 940234f0c4cSRajendra Nayak #define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) 941234f0c4cSRajendra Nayak 942234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_BYPASS */ 94356ef28acSRajendra Nayak #define OMAP4430_REGADDR_SHIFT 8 944234f0c4cSRajendra Nayak #define OMAP4430_REGADDR_MASK BITFIELD(8, 15) 945234f0c4cSRajendra Nayak 946234f0c4cSRajendra Nayak /* 947234f0c4cSRajendra Nayak * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 948234f0c4cSRajendra Nayak * PRM_VC_VAL_CMD_VDD_MPU_L 949234f0c4cSRajendra Nayak */ 95056ef28acSRajendra Nayak #define OMAP4430_RET_SHIFT 8 951234f0c4cSRajendra Nayak #define OMAP4430_RET_MASK BITFIELD(8, 15) 952234f0c4cSRajendra Nayak 953234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTCTRL */ 95456ef28acSRajendra Nayak #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 955234f0c4cSRajendra Nayak #define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) 956234f0c4cSRajendra Nayak 957234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTCTRL */ 95856ef28acSRajendra Nayak #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 959234f0c4cSRajendra Nayak #define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) 960234f0c4cSRajendra Nayak 961234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTST */ 96256ef28acSRajendra Nayak #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 963234f0c4cSRajendra Nayak #define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) 964234f0c4cSRajendra Nayak 965234f0c4cSRajendra Nayak /* 966234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 967234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_CTRL 968234f0c4cSRajendra Nayak */ 96956ef28acSRajendra Nayak #define OMAP4430_RETMODE_ENABLE_SHIFT 0 970234f0c4cSRajendra Nayak #define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) 971234f0c4cSRajendra Nayak 972234f0c4cSRajendra Nayak /* Used by REVISION_PRM */ 97356ef28acSRajendra Nayak #define OMAP4430_REV_SHIFT 0 974234f0c4cSRajendra Nayak #define OMAP4430_REV_MASK BITFIELD(0, 7) 975234f0c4cSRajendra Nayak 976234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ 97756ef28acSRajendra Nayak #define OMAP4430_RST1_SHIFT 0 978234f0c4cSRajendra Nayak #define OMAP4430_RST1_MASK BITFIELD(0, 0) 979234f0c4cSRajendra Nayak 980234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ 98156ef28acSRajendra Nayak #define OMAP4430_RST1ST_SHIFT 0 982234f0c4cSRajendra Nayak #define OMAP4430_RST1ST_MASK BITFIELD(0, 0) 983234f0c4cSRajendra Nayak 984234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ 98556ef28acSRajendra Nayak #define OMAP4430_RST2_SHIFT 1 986234f0c4cSRajendra Nayak #define OMAP4430_RST2_MASK BITFIELD(1, 1) 987234f0c4cSRajendra Nayak 988234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ 98956ef28acSRajendra Nayak #define OMAP4430_RST2ST_SHIFT 1 990234f0c4cSRajendra Nayak #define OMAP4430_RST2ST_MASK BITFIELD(1, 1) 991234f0c4cSRajendra Nayak 992234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ 99356ef28acSRajendra Nayak #define OMAP4430_RST3_SHIFT 2 994234f0c4cSRajendra Nayak #define OMAP4430_RST3_MASK BITFIELD(2, 2) 995234f0c4cSRajendra Nayak 996234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ 99756ef28acSRajendra Nayak #define OMAP4430_RST3ST_SHIFT 2 998234f0c4cSRajendra Nayak #define OMAP4430_RST3ST_MASK BITFIELD(2, 2) 999234f0c4cSRajendra Nayak 1000234f0c4cSRajendra Nayak /* Used by PRM_RSTTIME */ 100156ef28acSRajendra Nayak #define OMAP4430_RSTTIME1_SHIFT 0 1002234f0c4cSRajendra Nayak #define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) 1003234f0c4cSRajendra Nayak 1004234f0c4cSRajendra Nayak /* Used by PRM_RSTTIME */ 100556ef28acSRajendra Nayak #define OMAP4430_RSTTIME2_SHIFT 10 1006234f0c4cSRajendra Nayak #define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) 1007234f0c4cSRajendra Nayak 1008234f0c4cSRajendra Nayak /* Used by PRM_RSTCTRL */ 100956ef28acSRajendra Nayak #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 1010234f0c4cSRajendra Nayak #define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) 1011234f0c4cSRajendra Nayak 1012234f0c4cSRajendra Nayak /* Used by PRM_RSTCTRL */ 101356ef28acSRajendra Nayak #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 1014234f0c4cSRajendra Nayak #define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) 1015234f0c4cSRajendra Nayak 1016234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 101756ef28acSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 1018234f0c4cSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) 1019234f0c4cSRajendra Nayak 1020234f0c4cSRajendra Nayak /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ 102156ef28acSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 1022234f0c4cSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) 1023234f0c4cSRajendra Nayak 1024234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 102556ef28acSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 1026234f0c4cSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) 1027234f0c4cSRajendra Nayak 1028234f0c4cSRajendra Nayak /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ 102956ef28acSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 1030234f0c4cSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) 1031234f0c4cSRajendra Nayak 1032234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 103356ef28acSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 1034234f0c4cSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) 1035234f0c4cSRajendra Nayak 1036234f0c4cSRajendra Nayak /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ 103756ef28acSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 1038234f0c4cSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) 1039234f0c4cSRajendra Nayak 1040234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_CLK */ 104156ef28acSRajendra Nayak #define OMAP4430_SCLH_SHIFT 0 1042234f0c4cSRajendra Nayak #define OMAP4430_SCLH_MASK BITFIELD(0, 7) 1043234f0c4cSRajendra Nayak 1044234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_CLK */ 104556ef28acSRajendra Nayak #define OMAP4430_SCLL_SHIFT 8 1046234f0c4cSRajendra Nayak #define OMAP4430_SCLL_MASK BITFIELD(8, 15) 1047234f0c4cSRajendra Nayak 1048234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 104956ef28acSRajendra Nayak #define OMAP4430_SECURE_WDT_RST_SHIFT 4 1050234f0c4cSRajendra Nayak #define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) 1051234f0c4cSRajendra Nayak 1052234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 105356ef28acSRajendra Nayak #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 1054234f0c4cSRajendra Nayak #define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) 1055234f0c4cSRajendra Nayak 1056234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 105756ef28acSRajendra Nayak #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 1058234f0c4cSRajendra Nayak #define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) 1059234f0c4cSRajendra Nayak 1060234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTST */ 106156ef28acSRajendra Nayak #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 1062234f0c4cSRajendra Nayak #define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) 1063234f0c4cSRajendra Nayak 1064234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_BYPASS */ 106556ef28acSRajendra Nayak #define OMAP4430_SLAVEADDR_SHIFT 0 1066234f0c4cSRajendra Nayak #define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) 1067234f0c4cSRajendra Nayak 1068234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 106956ef28acSRajendra Nayak #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 1070234f0c4cSRajendra Nayak #define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) 1071234f0c4cSRajendra Nayak 1072234f0c4cSRajendra Nayak /* Used by PRM_SRAM_COUNT */ 107356ef28acSRajendra Nayak #define OMAP4430_SLPCNT_VALUE_SHIFT 16 1074234f0c4cSRajendra Nayak #define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) 1075234f0c4cSRajendra Nayak 1076234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ 107756ef28acSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 1078234f0c4cSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) 1079234f0c4cSRajendra Nayak 1080234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ 108156ef28acSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 1082234f0c4cSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) 1083234f0c4cSRajendra Nayak 1084234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 108556ef28acSRajendra Nayak #define OMAP4430_SR2EN_SHIFT 0 1086234f0c4cSRajendra Nayak #define OMAP4430_SR2EN_MASK BITFIELD(0, 0) 1087234f0c4cSRajendra Nayak 1088234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 108956ef28acSRajendra Nayak #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 1090234f0c4cSRajendra Nayak #define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) 1091234f0c4cSRajendra Nayak 1092234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 109356ef28acSRajendra Nayak #define OMAP4430_SR2_STATUS_SHIFT 3 1094234f0c4cSRajendra Nayak #define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) 1095234f0c4cSRajendra Nayak 1096234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 109756ef28acSRajendra Nayak #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 1098234f0c4cSRajendra Nayak #define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) 1099234f0c4cSRajendra Nayak 1100234f0c4cSRajendra Nayak /* 1101234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 1102234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_CTRL 1103234f0c4cSRajendra Nayak */ 110456ef28acSRajendra Nayak #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 1105234f0c4cSRajendra Nayak #define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) 1106234f0c4cSRajendra Nayak 1107234f0c4cSRajendra Nayak /* 1108234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 1109234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_CTRL 1110234f0c4cSRajendra Nayak */ 111156ef28acSRajendra Nayak #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 1112234f0c4cSRajendra Nayak #define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) 1113234f0c4cSRajendra Nayak 1114234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_MODE */ 111556ef28acSRajendra Nayak #define OMAP4430_SRMODEEN_SHIFT 4 1116234f0c4cSRajendra Nayak #define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) 1117234f0c4cSRajendra Nayak 1118234f0c4cSRajendra Nayak /* Used by PRM_VOLTSETUP_WARMRESET */ 111956ef28acSRajendra Nayak #define OMAP4430_STABLE_COUNT_SHIFT 0 1120234f0c4cSRajendra Nayak #define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) 1121234f0c4cSRajendra Nayak 1122234f0c4cSRajendra Nayak /* Used by PRM_VOLTSETUP_WARMRESET */ 112356ef28acSRajendra Nayak #define OMAP4430_STABLE_PRESCAL_SHIFT 8 1124234f0c4cSRajendra Nayak #define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) 1125234f0c4cSRajendra Nayak 1126234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 112756ef28acSRajendra Nayak #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 1128234f0c4cSRajendra Nayak #define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) 1129234f0c4cSRajendra Nayak 1130234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 113156ef28acSRajendra Nayak #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 1132234f0c4cSRajendra Nayak #define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) 1133234f0c4cSRajendra Nayak 1134234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTST */ 113556ef28acSRajendra Nayak #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 1136234f0c4cSRajendra Nayak #define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) 1137234f0c4cSRajendra Nayak 1138234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 113956ef28acSRajendra Nayak #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 1140234f0c4cSRajendra Nayak #define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) 1141234f0c4cSRajendra Nayak 1142234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 114356ef28acSRajendra Nayak #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 1144234f0c4cSRajendra Nayak #define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) 1145234f0c4cSRajendra Nayak 1146234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTST */ 114756ef28acSRajendra Nayak #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 1148234f0c4cSRajendra Nayak #define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) 1149234f0c4cSRajendra Nayak 1150234f0c4cSRajendra Nayak /* Used by RM_TESLA_RSTST */ 115156ef28acSRajendra Nayak #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 1152234f0c4cSRajendra Nayak #define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) 1153234f0c4cSRajendra Nayak 1154234f0c4cSRajendra Nayak /* Used by RM_TESLA_RSTST */ 115556ef28acSRajendra Nayak #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 1156234f0c4cSRajendra Nayak #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) 1157234f0c4cSRajendra Nayak 1158234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 115956ef28acSRajendra Nayak #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 1160234f0c4cSRajendra Nayak #define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) 1161234f0c4cSRajendra Nayak 1162234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 116356ef28acSRajendra Nayak #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 1164234f0c4cSRajendra Nayak #define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) 1165234f0c4cSRajendra Nayak 1166234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTST */ 116756ef28acSRajendra Nayak #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 1168234f0c4cSRajendra Nayak #define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) 1169234f0c4cSRajendra Nayak 1170234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 117156ef28acSRajendra Nayak #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 1172234f0c4cSRajendra Nayak #define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) 1173234f0c4cSRajendra Nayak 1174234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 117556ef28acSRajendra Nayak #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 1176234f0c4cSRajendra Nayak #define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) 1177234f0c4cSRajendra Nayak 1178234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTST */ 117956ef28acSRajendra Nayak #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 1180234f0c4cSRajendra Nayak #define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) 1181234f0c4cSRajendra Nayak 1182234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 118356ef28acSRajendra Nayak #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 1184234f0c4cSRajendra Nayak #define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) 1185234f0c4cSRajendra Nayak 1186234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 118756ef28acSRajendra Nayak #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 1188234f0c4cSRajendra Nayak #define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) 1189234f0c4cSRajendra Nayak 1190234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTST */ 119156ef28acSRajendra Nayak #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 1192234f0c4cSRajendra Nayak #define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) 1193234f0c4cSRajendra Nayak 1194234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 119556ef28acSRajendra Nayak #define OMAP4430_TIMEOUT_SHIFT 0 1196234f0c4cSRajendra Nayak #define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) 1197234f0c4cSRajendra Nayak 1198234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 119956ef28acSRajendra Nayak #define OMAP4430_TIMEOUTEN_SHIFT 3 1200234f0c4cSRajendra Nayak #define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) 1201234f0c4cSRajendra Nayak 1202234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 120356ef28acSRajendra Nayak #define OMAP4430_TRANSITION_EN_SHIFT 8 1204234f0c4cSRajendra Nayak #define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) 1205234f0c4cSRajendra Nayak 1206234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 120756ef28acSRajendra Nayak #define OMAP4430_TRANSITION_ST_SHIFT 8 1208234f0c4cSRajendra Nayak #define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) 1209234f0c4cSRajendra Nayak 1210234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_BYPASS */ 121156ef28acSRajendra Nayak #define OMAP4430_VALID_SHIFT 24 1212234f0c4cSRajendra Nayak #define OMAP4430_VALID_MASK BITFIELD(24, 24) 1213234f0c4cSRajendra Nayak 1214234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 121556ef28acSRajendra Nayak #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 1216234f0c4cSRajendra Nayak #define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) 1217234f0c4cSRajendra Nayak 1218234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 121956ef28acSRajendra Nayak #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 1220234f0c4cSRajendra Nayak #define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) 1221234f0c4cSRajendra Nayak 1222234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 122356ef28acSRajendra Nayak #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 1224234f0c4cSRajendra Nayak #define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) 1225234f0c4cSRajendra Nayak 1226234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 122756ef28acSRajendra Nayak #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 1228234f0c4cSRajendra Nayak #define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) 1229234f0c4cSRajendra Nayak 1230234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 123156ef28acSRajendra Nayak #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 1232234f0c4cSRajendra Nayak #define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) 1233234f0c4cSRajendra Nayak 1234234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 123556ef28acSRajendra Nayak #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 1236234f0c4cSRajendra Nayak #define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) 1237234f0c4cSRajendra Nayak 1238234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 123956ef28acSRajendra Nayak #define OMAP4430_VC_RAERR_EN_SHIFT 12 1240234f0c4cSRajendra Nayak #define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) 1241234f0c4cSRajendra Nayak 1242234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 124356ef28acSRajendra Nayak #define OMAP4430_VC_RAERR_ST_SHIFT 12 1244234f0c4cSRajendra Nayak #define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) 1245234f0c4cSRajendra Nayak 1246234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 124756ef28acSRajendra Nayak #define OMAP4430_VC_SAERR_EN_SHIFT 11 1248234f0c4cSRajendra Nayak #define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) 1249234f0c4cSRajendra Nayak 1250234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 125156ef28acSRajendra Nayak #define OMAP4430_VC_SAERR_ST_SHIFT 11 1252234f0c4cSRajendra Nayak #define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) 1253234f0c4cSRajendra Nayak 1254234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 125556ef28acSRajendra Nayak #define OMAP4430_VC_TOERR_EN_SHIFT 13 1256234f0c4cSRajendra Nayak #define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) 1257234f0c4cSRajendra Nayak 1258234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 125956ef28acSRajendra Nayak #define OMAP4430_VC_TOERR_ST_SHIFT 13 1260234f0c4cSRajendra Nayak #define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) 1261234f0c4cSRajendra Nayak 1262234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 126356ef28acSRajendra Nayak #define OMAP4430_VDDMAX_SHIFT 24 1264234f0c4cSRajendra Nayak #define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) 1265234f0c4cSRajendra Nayak 1266234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 126756ef28acSRajendra Nayak #define OMAP4430_VDDMIN_SHIFT 16 1268234f0c4cSRajendra Nayak #define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) 1269234f0c4cSRajendra Nayak 1270234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 127156ef28acSRajendra Nayak #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 1272234f0c4cSRajendra Nayak #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) 1273234f0c4cSRajendra Nayak 1274234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 127556ef28acSRajendra Nayak #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 1276234f0c4cSRajendra Nayak #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) 1277234f0c4cSRajendra Nayak 1278234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 127956ef28acSRajendra Nayak #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 1280234f0c4cSRajendra Nayak #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) 1281234f0c4cSRajendra Nayak 1282234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 128356ef28acSRajendra Nayak #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 1284234f0c4cSRajendra Nayak #define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) 1285234f0c4cSRajendra Nayak 1286234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 128756ef28acSRajendra Nayak #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 1288234f0c4cSRajendra Nayak #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) 1289234f0c4cSRajendra Nayak 1290234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 129156ef28acSRajendra Nayak #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 1292234f0c4cSRajendra Nayak #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) 1293234f0c4cSRajendra Nayak 1294234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 129556ef28acSRajendra Nayak #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 1296234f0c4cSRajendra Nayak #define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) 1297234f0c4cSRajendra Nayak 1298234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 129956ef28acSRajendra Nayak #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 1300234f0c4cSRajendra Nayak #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) 1301234f0c4cSRajendra Nayak 1302234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_VOL */ 130356ef28acSRajendra Nayak #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 1304234f0c4cSRajendra Nayak #define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) 1305234f0c4cSRajendra Nayak 1306234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_VOL */ 130756ef28acSRajendra Nayak #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 1308234f0c4cSRajendra Nayak #define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) 1309234f0c4cSRajendra Nayak 1310234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_VOL */ 131156ef28acSRajendra Nayak #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 1312234f0c4cSRajendra Nayak #define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) 1313234f0c4cSRajendra Nayak 1314234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 131556ef28acSRajendra Nayak #define OMAP4430_VPENABLE_SHIFT 0 1316234f0c4cSRajendra Nayak #define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) 1317234f0c4cSRajendra Nayak 1318234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ 131956ef28acSRajendra Nayak #define OMAP4430_VPINIDLE_SHIFT 0 1320234f0c4cSRajendra Nayak #define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) 1321234f0c4cSRajendra Nayak 1322234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ 132356ef28acSRajendra Nayak #define OMAP4430_VPVOLTAGE_SHIFT 0 1324234f0c4cSRajendra Nayak #define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) 1325234f0c4cSRajendra Nayak 1326234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 132756ef28acSRajendra Nayak #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 1328234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) 1329234f0c4cSRajendra Nayak 1330234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 133156ef28acSRajendra Nayak #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 1332234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) 1333234f0c4cSRajendra Nayak 1334234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 133556ef28acSRajendra Nayak #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 1336234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) 1337234f0c4cSRajendra Nayak 1338234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 133956ef28acSRajendra Nayak #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 1340234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) 1341234f0c4cSRajendra Nayak 1342234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 134356ef28acSRajendra Nayak #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 1344234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) 1345234f0c4cSRajendra Nayak 1346234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 134756ef28acSRajendra Nayak #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 1348234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) 1349234f0c4cSRajendra Nayak 1350234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 135156ef28acSRajendra Nayak #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 1352234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) 1353234f0c4cSRajendra Nayak 1354234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 135556ef28acSRajendra Nayak #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 1356234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) 1357234f0c4cSRajendra Nayak 1358234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 135956ef28acSRajendra Nayak #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 1360234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) 1361234f0c4cSRajendra Nayak 1362234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 136356ef28acSRajendra Nayak #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 1364234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) 1365234f0c4cSRajendra Nayak 1366234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 136756ef28acSRajendra Nayak #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 1368234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) 1369234f0c4cSRajendra Nayak 1370234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 137156ef28acSRajendra Nayak #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 1372234f0c4cSRajendra Nayak #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) 1373234f0c4cSRajendra Nayak 1374234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 137556ef28acSRajendra Nayak #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 1376234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) 1377234f0c4cSRajendra Nayak 1378234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 137956ef28acSRajendra Nayak #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 1380234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) 1381234f0c4cSRajendra Nayak 1382234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 138356ef28acSRajendra Nayak #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 1384234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) 1385234f0c4cSRajendra Nayak 1386234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 138756ef28acSRajendra Nayak #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 1388234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) 1389234f0c4cSRajendra Nayak 1390234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 139156ef28acSRajendra Nayak #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 1392234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) 1393234f0c4cSRajendra Nayak 1394234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 139556ef28acSRajendra Nayak #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 1396234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) 1397234f0c4cSRajendra Nayak 1398234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 139956ef28acSRajendra Nayak #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 1400234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) 1401234f0c4cSRajendra Nayak 1402234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 140356ef28acSRajendra Nayak #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 1404234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) 1405234f0c4cSRajendra Nayak 1406234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 140756ef28acSRajendra Nayak #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 1408234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) 1409234f0c4cSRajendra Nayak 1410234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 141156ef28acSRajendra Nayak #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 1412234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) 1413234f0c4cSRajendra Nayak 1414234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 141556ef28acSRajendra Nayak #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 1416234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) 1417234f0c4cSRajendra Nayak 1418234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 141956ef28acSRajendra Nayak #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 1420234f0c4cSRajendra Nayak #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) 1421234f0c4cSRajendra Nayak 1422234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 142356ef28acSRajendra Nayak #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 1424234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) 1425234f0c4cSRajendra Nayak 1426234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 142756ef28acSRajendra Nayak #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 1428234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) 1429234f0c4cSRajendra Nayak 1430234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 143156ef28acSRajendra Nayak #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 1432234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) 1433234f0c4cSRajendra Nayak 1434234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 143556ef28acSRajendra Nayak #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 1436234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) 1437234f0c4cSRajendra Nayak 1438234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 143956ef28acSRajendra Nayak #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 1440234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) 1441234f0c4cSRajendra Nayak 1442234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 144356ef28acSRajendra Nayak #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 1444234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) 1445234f0c4cSRajendra Nayak 1446234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 144756ef28acSRajendra Nayak #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 1448234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) 1449234f0c4cSRajendra Nayak 1450234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 145156ef28acSRajendra Nayak #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 1452234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) 1453234f0c4cSRajendra Nayak 1454234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 145556ef28acSRajendra Nayak #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 1456234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) 1457234f0c4cSRajendra Nayak 1458234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 145956ef28acSRajendra Nayak #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 1460234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) 1461234f0c4cSRajendra Nayak 1462234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 146356ef28acSRajendra Nayak #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 1464234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) 1465234f0c4cSRajendra Nayak 1466234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 146756ef28acSRajendra Nayak #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 1468234f0c4cSRajendra Nayak #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) 1469234f0c4cSRajendra Nayak 1470234f0c4cSRajendra Nayak /* Used by PRM_SRAM_COUNT */ 147156ef28acSRajendra Nayak #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 1472234f0c4cSRajendra Nayak #define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) 1473234f0c4cSRajendra Nayak 1474234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ 147556ef28acSRajendra Nayak #define OMAP4430_VSTEPMAX_SHIFT 0 1476234f0c4cSRajendra Nayak #define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) 1477234f0c4cSRajendra Nayak 1478234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ 147956ef28acSRajendra Nayak #define OMAP4430_VSTEPMIN_SHIFT 0 1480234f0c4cSRajendra Nayak #define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) 1481234f0c4cSRajendra Nayak 1482234f0c4cSRajendra Nayak /* Used by PRM_MODEM_IF_CTRL */ 148356ef28acSRajendra Nayak #define OMAP4430_WAKE_MODEM_SHIFT 0 1484234f0c4cSRajendra Nayak #define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) 1485234f0c4cSRajendra Nayak 1486234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 148756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 1488234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) 1489234f0c4cSRajendra Nayak 1490234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 149156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 1492234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) 1493234f0c4cSRajendra Nayak 1494234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 149556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 1496234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) 1497234f0c4cSRajendra Nayak 1498234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 149956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 1500234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) 1501234f0c4cSRajendra Nayak 1502234f0c4cSRajendra Nayak /* Used by PM_ABE_DMIC_WKDEP */ 150356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 1504234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) 1505234f0c4cSRajendra Nayak 1506234f0c4cSRajendra Nayak /* Used by PM_ABE_DMIC_WKDEP */ 150756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 1508234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) 1509234f0c4cSRajendra Nayak 1510234f0c4cSRajendra Nayak /* Used by PM_ABE_DMIC_WKDEP */ 151156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 1512234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) 1513234f0c4cSRajendra Nayak 1514234f0c4cSRajendra Nayak /* Used by PM_ABE_DMIC_WKDEP */ 151556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 1516234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) 1517234f0c4cSRajendra Nayak 1518234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER10_WKDEP */ 151956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 1520234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) 1521234f0c4cSRajendra Nayak 1522234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER11_WKDEP */ 152356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 1524234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) 1525234f0c4cSRajendra Nayak 1526234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER11_WKDEP */ 152756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 1528234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) 1529234f0c4cSRajendra Nayak 1530234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER2_WKDEP */ 153156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 1532234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) 1533234f0c4cSRajendra Nayak 1534234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER3_WKDEP */ 153556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 1536234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) 1537234f0c4cSRajendra Nayak 1538234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER3_WKDEP */ 153956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 1540234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) 1541234f0c4cSRajendra Nayak 1542234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER4_WKDEP */ 154356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 1544234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) 1545234f0c4cSRajendra Nayak 1546234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER4_WKDEP */ 154756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 1548234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) 1549234f0c4cSRajendra Nayak 1550234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER9_WKDEP */ 155156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 1552234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) 1553234f0c4cSRajendra Nayak 1554234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER9_WKDEP */ 155556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 1556234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) 1557234f0c4cSRajendra Nayak 1558234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 155956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 1560234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) 1561234f0c4cSRajendra Nayak 1562234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 156356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 1564234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) 1565234f0c4cSRajendra Nayak 1566234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 156756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 1568234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) 1569234f0c4cSRajendra Nayak 1570234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 157156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 1572234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) 1573234f0c4cSRajendra Nayak 1574234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 157556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 1576234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) 1577234f0c4cSRajendra Nayak 1578234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 157956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 1580234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) 1581234f0c4cSRajendra Nayak 1582234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 158356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 1584234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) 1585234f0c4cSRajendra Nayak 1586234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 158756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 1588234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) 1589234f0c4cSRajendra Nayak 1590234f0c4cSRajendra Nayak /* Used by PM_WKUP_GPIO1_WKDEP */ 159156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 1592234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) 1593234f0c4cSRajendra Nayak 1594234f0c4cSRajendra Nayak /* Used by PM_WKUP_GPIO1_WKDEP */ 159556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 1596234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) 1597234f0c4cSRajendra Nayak 1598234f0c4cSRajendra Nayak /* Used by PM_WKUP_GPIO1_WKDEP */ 159956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 1600234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) 1601234f0c4cSRajendra Nayak 1602234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO2_WKDEP */ 160356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 1604234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) 1605234f0c4cSRajendra Nayak 1606234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO2_WKDEP */ 160756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 1608234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) 1609234f0c4cSRajendra Nayak 1610234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO2_WKDEP */ 161156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 1612234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) 1613234f0c4cSRajendra Nayak 1614234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO3_WKDEP */ 161556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 1616234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) 1617234f0c4cSRajendra Nayak 1618234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO3_WKDEP */ 161956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 1620234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) 1621234f0c4cSRajendra Nayak 1622234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO4_WKDEP */ 162356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 1624234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) 1625234f0c4cSRajendra Nayak 1626234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO4_WKDEP */ 162756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 1628234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) 1629234f0c4cSRajendra Nayak 1630234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO5_WKDEP */ 163156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 1632234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) 1633234f0c4cSRajendra Nayak 1634234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO5_WKDEP */ 163556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 1636234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) 1637234f0c4cSRajendra Nayak 1638234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO6_WKDEP */ 163956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 1640234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) 1641234f0c4cSRajendra Nayak 1642234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO6_WKDEP */ 164356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 1644234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) 1645234f0c4cSRajendra Nayak 1646234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 164756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 1648234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) 1649234f0c4cSRajendra Nayak 1650234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 165156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 1652234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) 1653234f0c4cSRajendra Nayak 1654234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 165556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 1656234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) 1657234f0c4cSRajendra Nayak 1658234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 165956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 1660234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) 1661234f0c4cSRajendra Nayak 1662234f0c4cSRajendra Nayak /* Used by PM_L4PER_HECC1_WKDEP */ 166356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 1664234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) 1665234f0c4cSRajendra Nayak 1666234f0c4cSRajendra Nayak /* Used by PM_L4PER_HECC2_WKDEP */ 166756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 1668234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) 1669234f0c4cSRajendra Nayak 1670234f0c4cSRajendra Nayak /* Used by PM_L3INIT_HSI_WKDEP */ 167156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 1672234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) 1673234f0c4cSRajendra Nayak 1674234f0c4cSRajendra Nayak /* Used by PM_L3INIT_HSI_WKDEP */ 167556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 1676234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) 1677234f0c4cSRajendra Nayak 1678234f0c4cSRajendra Nayak /* Used by PM_L3INIT_HSI_WKDEP */ 167956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 1680234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) 1681234f0c4cSRajendra Nayak 1682234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C1_WKDEP */ 168356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 1684234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) 1685234f0c4cSRajendra Nayak 1686234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C1_WKDEP */ 168756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 1688234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) 1689234f0c4cSRajendra Nayak 1690234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C1_WKDEP */ 169156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 1692234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) 1693234f0c4cSRajendra Nayak 1694234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C2_WKDEP */ 169556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 1696234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) 1697234f0c4cSRajendra Nayak 1698234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C2_WKDEP */ 169956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 1700234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) 1701234f0c4cSRajendra Nayak 1702234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C2_WKDEP */ 170356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 1704234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) 1705234f0c4cSRajendra Nayak 1706234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C3_WKDEP */ 170756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 1708234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) 1709234f0c4cSRajendra Nayak 1710234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C3_WKDEP */ 171156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 1712234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) 1713234f0c4cSRajendra Nayak 1714234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C3_WKDEP */ 171556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 1716234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) 1717234f0c4cSRajendra Nayak 1718234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C4_WKDEP */ 171956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 1720234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) 1721234f0c4cSRajendra Nayak 1722234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C4_WKDEP */ 172356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 1724234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) 1725234f0c4cSRajendra Nayak 1726234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C4_WKDEP */ 172756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 1728234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) 1729234f0c4cSRajendra Nayak 1730234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C5_WKDEP */ 173156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 1732234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) 1733234f0c4cSRajendra Nayak 1734234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C5_WKDEP */ 173556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 1736234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) 1737234f0c4cSRajendra Nayak 1738234f0c4cSRajendra Nayak /* Used by PM_WKUP_KEYBOARD_WKDEP */ 173956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 1740234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) 1741234f0c4cSRajendra Nayak 1742234f0c4cSRajendra Nayak /* Used by PM_ABE_MCASP_WKDEP */ 174356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 1744234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) 1745234f0c4cSRajendra Nayak 1746234f0c4cSRajendra Nayak /* Used by PM_ABE_MCASP_WKDEP */ 174756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 1748234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) 1749234f0c4cSRajendra Nayak 1750234f0c4cSRajendra Nayak /* Used by PM_ABE_MCASP_WKDEP */ 175156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 1752234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) 1753234f0c4cSRajendra Nayak 1754234f0c4cSRajendra Nayak /* Used by PM_ABE_MCASP_WKDEP */ 175556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 1756234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) 1757234f0c4cSRajendra Nayak 1758234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP2_WKDEP */ 175956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 1760234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) 1761234f0c4cSRajendra Nayak 1762234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP2_WKDEP */ 176356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 1764234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) 1765234f0c4cSRajendra Nayak 1766234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP2_WKDEP */ 176756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 1768234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) 1769234f0c4cSRajendra Nayak 1770234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP2_WKDEP */ 177156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 1772234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) 1773234f0c4cSRajendra Nayak 1774234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP3_WKDEP */ 177556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 1776234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) 1777234f0c4cSRajendra Nayak 1778234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP3_WKDEP */ 177956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 1780234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) 1781234f0c4cSRajendra Nayak 1782234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP3_WKDEP */ 178356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 1784234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) 1785234f0c4cSRajendra Nayak 1786234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP3_WKDEP */ 178756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 1788234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) 1789234f0c4cSRajendra Nayak 1790234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP1_WKDEP */ 179156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 1792234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) 1793234f0c4cSRajendra Nayak 1794234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP1_WKDEP */ 179556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 1796234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) 1797234f0c4cSRajendra Nayak 1798234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP1_WKDEP */ 179956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 1800234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) 1801234f0c4cSRajendra Nayak 1802234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP2_WKDEP */ 180356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 1804234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) 1805234f0c4cSRajendra Nayak 1806234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP2_WKDEP */ 180756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 1808234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) 1809234f0c4cSRajendra Nayak 1810234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP2_WKDEP */ 181156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 1812234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) 1813234f0c4cSRajendra Nayak 1814234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP3_WKDEP */ 181556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 1816234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) 1817234f0c4cSRajendra Nayak 1818234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP3_WKDEP */ 181956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 1820234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) 1821234f0c4cSRajendra Nayak 1822234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP3_WKDEP */ 182356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 1824234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) 1825234f0c4cSRajendra Nayak 1826234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCBSP4_WKDEP */ 182756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 1828234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) 1829234f0c4cSRajendra Nayak 1830234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCBSP4_WKDEP */ 183156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 1832234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) 1833234f0c4cSRajendra Nayak 1834234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCBSP4_WKDEP */ 183556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 1836234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) 1837234f0c4cSRajendra Nayak 1838234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI1_WKDEP */ 183956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 1840234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) 1841234f0c4cSRajendra Nayak 1842234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI1_WKDEP */ 184356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 1844234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) 1845234f0c4cSRajendra Nayak 1846234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI1_WKDEP */ 184756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 1848234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) 1849234f0c4cSRajendra Nayak 1850234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI1_WKDEP */ 185156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 1852234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) 1853234f0c4cSRajendra Nayak 1854234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI2_WKDEP */ 185556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 1856234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) 1857234f0c4cSRajendra Nayak 1858234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI2_WKDEP */ 185956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 1860234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) 1861234f0c4cSRajendra Nayak 1862234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI2_WKDEP */ 186356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 1864234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) 1865234f0c4cSRajendra Nayak 1866234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI3_WKDEP */ 186756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 1868234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) 1869234f0c4cSRajendra Nayak 1870234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI3_WKDEP */ 187156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 1872234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) 1873234f0c4cSRajendra Nayak 1874234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI4_WKDEP */ 187556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 1876234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) 1877234f0c4cSRajendra Nayak 1878234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI4_WKDEP */ 187956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 1880234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) 1881234f0c4cSRajendra Nayak 1882234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC1_WKDEP */ 188356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 1884234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) 1885234f0c4cSRajendra Nayak 1886234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC1_WKDEP */ 188756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 1888234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) 1889234f0c4cSRajendra Nayak 1890234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC1_WKDEP */ 189156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 1892234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) 1893234f0c4cSRajendra Nayak 1894234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC1_WKDEP */ 189556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 1896234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) 1897234f0c4cSRajendra Nayak 1898234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC2_WKDEP */ 189956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 1900234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) 1901234f0c4cSRajendra Nayak 1902234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC2_WKDEP */ 190356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 1904234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) 1905234f0c4cSRajendra Nayak 1906234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC2_WKDEP */ 190756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 1908234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) 1909234f0c4cSRajendra Nayak 1910234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC2_WKDEP */ 191156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 1912234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) 1913234f0c4cSRajendra Nayak 1914234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC6_WKDEP */ 191556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 1916234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) 1917234f0c4cSRajendra Nayak 1918234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC6_WKDEP */ 191956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 1920234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) 1921234f0c4cSRajendra Nayak 1922234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC6_WKDEP */ 192356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 1924234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) 1925234f0c4cSRajendra Nayak 1926234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD3_WKDEP */ 192756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 1928234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) 1929234f0c4cSRajendra Nayak 1930234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD3_WKDEP */ 193156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 1932234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) 1933234f0c4cSRajendra Nayak 1934234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD3_WKDEP */ 193556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 1936234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) 1937234f0c4cSRajendra Nayak 1938234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD4_WKDEP */ 193956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 1940234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) 1941234f0c4cSRajendra Nayak 1942234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD4_WKDEP */ 194356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 1944234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) 1945234f0c4cSRajendra Nayak 1946234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD4_WKDEP */ 194756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 1948234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) 1949234f0c4cSRajendra Nayak 1950234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD5_WKDEP */ 195156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 1952234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) 1953234f0c4cSRajendra Nayak 1954234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD5_WKDEP */ 195556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 1956234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) 1957234f0c4cSRajendra Nayak 1958234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD5_WKDEP */ 195956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 1960234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) 1961234f0c4cSRajendra Nayak 1962234f0c4cSRajendra Nayak /* Used by PM_L3INIT_PCIESS_WKDEP */ 196356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 1964234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) 1965234f0c4cSRajendra Nayak 1966234f0c4cSRajendra Nayak /* Used by PM_L3INIT_PCIESS_WKDEP */ 196756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 1968234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) 1969234f0c4cSRajendra Nayak 1970234f0c4cSRajendra Nayak /* Used by PM_ABE_PDM_WKDEP */ 197156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 1972234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) 1973234f0c4cSRajendra Nayak 1974234f0c4cSRajendra Nayak /* Used by PM_ABE_PDM_WKDEP */ 197556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 1976234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) 1977234f0c4cSRajendra Nayak 1978234f0c4cSRajendra Nayak /* Used by PM_ABE_PDM_WKDEP */ 197956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 1980234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) 1981234f0c4cSRajendra Nayak 1982234f0c4cSRajendra Nayak /* Used by PM_ABE_PDM_WKDEP */ 198356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 1984234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) 1985234f0c4cSRajendra Nayak 1986234f0c4cSRajendra Nayak /* Used by PM_WKUP_RTC_WKDEP */ 198756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 1988234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) 1989234f0c4cSRajendra Nayak 1990234f0c4cSRajendra Nayak /* Used by PM_L3INIT_SATA_WKDEP */ 199156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 1992234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) 1993234f0c4cSRajendra Nayak 1994234f0c4cSRajendra Nayak /* Used by PM_L3INIT_SATA_WKDEP */ 199556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 1996234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) 1997234f0c4cSRajendra Nayak 1998234f0c4cSRajendra Nayak /* Used by PM_ABE_SLIMBUS_WKDEP */ 199956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 2000234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) 2001234f0c4cSRajendra Nayak 2002234f0c4cSRajendra Nayak /* Used by PM_ABE_SLIMBUS_WKDEP */ 200356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 2004234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) 2005234f0c4cSRajendra Nayak 2006234f0c4cSRajendra Nayak /* Used by PM_ABE_SLIMBUS_WKDEP */ 200756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 2008234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) 2009234f0c4cSRajendra Nayak 2010234f0c4cSRajendra Nayak /* Used by PM_ABE_SLIMBUS_WKDEP */ 201156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 2012234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) 2013234f0c4cSRajendra Nayak 2014234f0c4cSRajendra Nayak /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 201556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 2016234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) 2017234f0c4cSRajendra Nayak 2018234f0c4cSRajendra Nayak /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 201956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 2020234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) 2021234f0c4cSRajendra Nayak 2022234f0c4cSRajendra Nayak /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 202356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 2024234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) 2025234f0c4cSRajendra Nayak 2026234f0c4cSRajendra Nayak /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 202756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 2028234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) 2029234f0c4cSRajendra Nayak 2030234f0c4cSRajendra Nayak /* Used by PM_ALWON_SR_CORE_WKDEP */ 203156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 2032234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) 2033234f0c4cSRajendra Nayak 2034234f0c4cSRajendra Nayak /* Used by PM_ALWON_SR_CORE_WKDEP */ 203556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 2036234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) 2037234f0c4cSRajendra Nayak 2038234f0c4cSRajendra Nayak /* Used by PM_ALWON_SR_IVA_WKDEP */ 203956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 2040234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) 2041234f0c4cSRajendra Nayak 2042234f0c4cSRajendra Nayak /* Used by PM_ALWON_SR_IVA_WKDEP */ 204356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 2044234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) 2045234f0c4cSRajendra Nayak 2046234f0c4cSRajendra Nayak /* Used by PM_ALWON_SR_MPU_WKDEP */ 204756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 2048234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) 2049234f0c4cSRajendra Nayak 2050234f0c4cSRajendra Nayak /* Used by PM_WKUP_TIMER12_WKDEP */ 205156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 2052234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) 2053234f0c4cSRajendra Nayak 2054234f0c4cSRajendra Nayak /* Used by PM_WKUP_TIMER1_WKDEP */ 205556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 2056234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) 2057234f0c4cSRajendra Nayak 2058234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER5_WKDEP */ 205956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 2060234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) 2061234f0c4cSRajendra Nayak 2062234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER5_WKDEP */ 206356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 2064234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) 2065234f0c4cSRajendra Nayak 2066234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER6_WKDEP */ 206756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 2068234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) 2069234f0c4cSRajendra Nayak 2070234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER6_WKDEP */ 207156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 2072234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) 2073234f0c4cSRajendra Nayak 2074234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER7_WKDEP */ 207556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 2076234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) 2077234f0c4cSRajendra Nayak 2078234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER7_WKDEP */ 207956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 2080234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) 2081234f0c4cSRajendra Nayak 2082234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER8_WKDEP */ 208356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 2084234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) 2085234f0c4cSRajendra Nayak 2086234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER8_WKDEP */ 208756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 2088234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) 2089234f0c4cSRajendra Nayak 2090234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART1_WKDEP */ 209156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 2092234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) 2093234f0c4cSRajendra Nayak 2094234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART1_WKDEP */ 209556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 2096234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) 2097234f0c4cSRajendra Nayak 2098234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART2_WKDEP */ 209956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 2100234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) 2101234f0c4cSRajendra Nayak 2102234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART2_WKDEP */ 210356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 2104234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) 2105234f0c4cSRajendra Nayak 2106234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART3_WKDEP */ 210756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 2108234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) 2109234f0c4cSRajendra Nayak 2110234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART3_WKDEP */ 211156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 2112234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) 2113234f0c4cSRajendra Nayak 2114234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART3_WKDEP */ 211556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 2116234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) 2117234f0c4cSRajendra Nayak 2118234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART3_WKDEP */ 211956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 2120234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) 2121234f0c4cSRajendra Nayak 2122234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART4_WKDEP */ 212356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 2124234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) 2125234f0c4cSRajendra Nayak 2126234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART4_WKDEP */ 212756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 2128234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) 2129234f0c4cSRajendra Nayak 2130234f0c4cSRajendra Nayak /* Used by PM_L3INIT_UNIPRO1_WKDEP */ 213156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 2132234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) 2133234f0c4cSRajendra Nayak 2134234f0c4cSRajendra Nayak /* Used by PM_L3INIT_UNIPRO1_WKDEP */ 213556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 2136234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) 2137234f0c4cSRajendra Nayak 2138234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_HOST_WKDEP */ 213956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 2140234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) 2141234f0c4cSRajendra Nayak 2142234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ 214356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 2144234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) 2145234f0c4cSRajendra Nayak 2146234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ 214756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 2148234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) 2149234f0c4cSRajendra Nayak 2150234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_HOST_WKDEP */ 215156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 2152234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) 2153234f0c4cSRajendra Nayak 2154234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_OTG_WKDEP */ 215556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 2156234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) 2157234f0c4cSRajendra Nayak 2158234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_OTG_WKDEP */ 215956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 2160234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) 2161234f0c4cSRajendra Nayak 2162234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_TLL_WKDEP */ 216356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 2164234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) 2165234f0c4cSRajendra Nayak 2166234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_TLL_WKDEP */ 216756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 2168234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) 2169234f0c4cSRajendra Nayak 2170234f0c4cSRajendra Nayak /* Used by PM_WKUP_USIM_WKDEP */ 217156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 2172234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) 2173234f0c4cSRajendra Nayak 2174234f0c4cSRajendra Nayak /* Used by PM_WKUP_USIM_WKDEP */ 217556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 2176234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) 2177234f0c4cSRajendra Nayak 2178234f0c4cSRajendra Nayak /* Used by PM_WKUP_WDT2_WKDEP */ 217956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 2180234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) 2181234f0c4cSRajendra Nayak 2182234f0c4cSRajendra Nayak /* Used by PM_WKUP_WDT2_WKDEP */ 218356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 2184234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) 2185234f0c4cSRajendra Nayak 2186234f0c4cSRajendra Nayak /* Used by PM_ABE_WDT3_WKDEP */ 218756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 2188234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) 2189234f0c4cSRajendra Nayak 2190234f0c4cSRajendra Nayak /* Used by PM_L3INIT_HSI_WKDEP */ 219156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 2192234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) 2193234f0c4cSRajendra Nayak 2194234f0c4cSRajendra Nayak /* Used by PM_L3INIT_XHPI_WKDEP */ 219556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 2196234f0c4cSRajendra Nayak #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) 2197234f0c4cSRajendra Nayak 2198234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 219956ef28acSRajendra Nayak #define OMAP4430_WUCLK_CTRL_SHIFT 8 2200234f0c4cSRajendra Nayak #define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) 2201234f0c4cSRajendra Nayak 2202234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 220356ef28acSRajendra Nayak #define OMAP4430_WUCLK_STATUS_SHIFT 9 2204234f0c4cSRajendra Nayak #define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) 2205234f0c4cSRajendra Nayak #endif 2206