1234f0c4cSRajendra Nayak /* 2234f0c4cSRajendra Nayak * OMAP44xx Power Management register bits 3234f0c4cSRajendra Nayak * 4568997cfSRajendra Nayak * Copyright (C) 2009-2010 Texas Instruments, Inc. 5568997cfSRajendra Nayak * Copyright (C) 2009-2010 Nokia Corporation 6234f0c4cSRajendra Nayak * 7234f0c4cSRajendra Nayak * Paul Walmsley (paul@pwsan.com) 8234f0c4cSRajendra Nayak * Rajendra Nayak (rnayak@ti.com) 9234f0c4cSRajendra Nayak * Benoit Cousson (b-cousson@ti.com) 10234f0c4cSRajendra Nayak * 11234f0c4cSRajendra Nayak * This file is automatically generated from the OMAP hardware databases. 12234f0c4cSRajendra Nayak * We respectfully ask that any modifications to this file be coordinated 13234f0c4cSRajendra Nayak * with the public linux-omap@vger.kernel.org mailing list and the 14234f0c4cSRajendra Nayak * authors above to ensure that the autogeneration scripts are kept 15234f0c4cSRajendra Nayak * up-to-date with the file contents. 16234f0c4cSRajendra Nayak * 17234f0c4cSRajendra Nayak * This program is free software; you can redistribute it and/or modify 18234f0c4cSRajendra Nayak * it under the terms of the GNU General Public License version 2 as 19234f0c4cSRajendra Nayak * published by the Free Software Foundation. 20234f0c4cSRajendra Nayak */ 21234f0c4cSRajendra Nayak 22234f0c4cSRajendra Nayak #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 23234f0c4cSRajendra Nayak #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 24234f0c4cSRajendra Nayak 25234f0c4cSRajendra Nayak #include "prm.h" 26234f0c4cSRajendra Nayak 27234f0c4cSRajendra Nayak 28234f0c4cSRajendra Nayak /* 29234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 30234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 31234f0c4cSRajendra Nayak */ 3256ef28acSRajendra Nayak #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 33568997cfSRajendra Nayak #define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) 34234f0c4cSRajendra Nayak 35234f0c4cSRajendra Nayak /* 36234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 37234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 38234f0c4cSRajendra Nayak */ 3956ef28acSRajendra Nayak #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 40568997cfSRajendra Nayak #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) 41234f0c4cSRajendra Nayak 42234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 4356ef28acSRajendra Nayak #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 44568997cfSRajendra Nayak #define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) 45234f0c4cSRajendra Nayak 46234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 4756ef28acSRajendra Nayak #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 48568997cfSRajendra Nayak #define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) 49234f0c4cSRajendra Nayak 50234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 5156ef28acSRajendra Nayak #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 52568997cfSRajendra Nayak #define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) 53234f0c4cSRajendra Nayak 54234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 5556ef28acSRajendra Nayak #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 56568997cfSRajendra Nayak #define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) 57234f0c4cSRajendra Nayak 58234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 5956ef28acSRajendra Nayak #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 60568997cfSRajendra Nayak #define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) 61234f0c4cSRajendra Nayak 62234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 6356ef28acSRajendra Nayak #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 64568997cfSRajendra Nayak #define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) 65234f0c4cSRajendra Nayak 66234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTCTRL */ 6756ef28acSRajendra Nayak #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 68568997cfSRajendra Nayak #define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) 69234f0c4cSRajendra Nayak 70234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTCTRL */ 7156ef28acSRajendra Nayak #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 72568997cfSRajendra Nayak #define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) 73234f0c4cSRajendra Nayak 74234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTST */ 7556ef28acSRajendra Nayak #define OMAP4430_AESSMEM_STATEST_SHIFT 4 76568997cfSRajendra Nayak #define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) 77234f0c4cSRajendra Nayak 78234f0c4cSRajendra Nayak /* 79234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 80234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 81234f0c4cSRajendra Nayak */ 8256ef28acSRajendra Nayak #define OMAP4430_AIPOFF_SHIFT 8 83568997cfSRajendra Nayak #define OMAP4430_AIPOFF_MASK (1 << 8) 84234f0c4cSRajendra Nayak 85234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 8656ef28acSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 87568997cfSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) 88234f0c4cSRajendra Nayak 89234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 9056ef28acSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 91568997cfSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) 92234f0c4cSRajendra Nayak 93234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 9456ef28acSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 95568997cfSRajendra Nayak #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) 96568997cfSRajendra Nayak 97568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 98568997cfSRajendra Nayak #define OMAP4430_BYPS_RA_ERR_SHIFT 25 99568997cfSRajendra Nayak #define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) 100568997cfSRajendra Nayak 101568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 102568997cfSRajendra Nayak #define OMAP4430_BYPS_SA_ERR_SHIFT 24 103568997cfSRajendra Nayak #define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) 104568997cfSRajendra Nayak 105568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 106568997cfSRajendra Nayak #define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 107568997cfSRajendra Nayak #define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) 108568997cfSRajendra Nayak 109568997cfSRajendra Nayak /* Used by PRM_RSTST */ 110568997cfSRajendra Nayak #define OMAP4430_C2C_RST_SHIFT 10 111568997cfSRajendra Nayak #define OMAP4430_C2C_RST_MASK (1 << 10) 112234f0c4cSRajendra Nayak 113234f0c4cSRajendra Nayak /* Used by PM_CAM_PWRSTCTRL */ 11456ef28acSRajendra Nayak #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 115568997cfSRajendra Nayak #define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) 116234f0c4cSRajendra Nayak 117234f0c4cSRajendra Nayak /* Used by PM_CAM_PWRSTST */ 11856ef28acSRajendra Nayak #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 119568997cfSRajendra Nayak #define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) 120234f0c4cSRajendra Nayak 121234f0c4cSRajendra Nayak /* Used by PRM_CLKREQCTRL */ 12256ef28acSRajendra Nayak #define OMAP4430_CLKREQ_COND_SHIFT 0 123568997cfSRajendra Nayak #define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) 124234f0c4cSRajendra Nayak 125234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_CMD */ 12656ef28acSRajendra Nayak #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 127568997cfSRajendra Nayak #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) 128234f0c4cSRajendra Nayak 129234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_CMD */ 13056ef28acSRajendra Nayak #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 131568997cfSRajendra Nayak #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) 132234f0c4cSRajendra Nayak 133234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_CMD */ 13456ef28acSRajendra Nayak #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 135568997cfSRajendra Nayak #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) 136234f0c4cSRajendra Nayak 137234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 13856ef28acSRajendra Nayak #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 139568997cfSRajendra Nayak #define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) 140234f0c4cSRajendra Nayak 141234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 14256ef28acSRajendra Nayak #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 143568997cfSRajendra Nayak #define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) 144234f0c4cSRajendra Nayak 145234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 14656ef28acSRajendra Nayak #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 147568997cfSRajendra Nayak #define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) 148234f0c4cSRajendra Nayak 149234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 15056ef28acSRajendra Nayak #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 151568997cfSRajendra Nayak #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) 152234f0c4cSRajendra Nayak 153234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 15456ef28acSRajendra Nayak #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 155568997cfSRajendra Nayak #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) 156234f0c4cSRajendra Nayak 157234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTST */ 15856ef28acSRajendra Nayak #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 159568997cfSRajendra Nayak #define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) 160234f0c4cSRajendra Nayak 161234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 16256ef28acSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 163568997cfSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) 164234f0c4cSRajendra Nayak 165234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 16656ef28acSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 167568997cfSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) 168234f0c4cSRajendra Nayak 169234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTST */ 17056ef28acSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 171568997cfSRajendra Nayak #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) 172568997cfSRajendra Nayak 173568997cfSRajendra Nayak /* Used by REVISION_PRM */ 174568997cfSRajendra Nayak #define OMAP4430_CUSTOM_SHIFT 6 175568997cfSRajendra Nayak #define OMAP4430_CUSTOM_MASK (0x3 << 6) 176234f0c4cSRajendra Nayak 177234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_BYPASS */ 17856ef28acSRajendra Nayak #define OMAP4430_DATA_SHIFT 16 179568997cfSRajendra Nayak #define OMAP4430_DATA_MASK (0xff << 16) 180234f0c4cSRajendra Nayak 181234f0c4cSRajendra Nayak /* Used by PRM_DEVICE_OFF_CTRL */ 18256ef28acSRajendra Nayak #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 183568997cfSRajendra Nayak #define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) 184234f0c4cSRajendra Nayak 185234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_MODE */ 18656ef28acSRajendra Nayak #define OMAP4430_DFILTEREN_SHIFT 6 187568997cfSRajendra Nayak #define OMAP4430_DFILTEREN_MASK (1 << 6) 188234f0c4cSRajendra Nayak 189234f0c4cSRajendra Nayak /* 190234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 191234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP 192234f0c4cSRajendra Nayak */ 193568997cfSRajendra Nayak #define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 194568997cfSRajendra Nayak #define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) 195568997cfSRajendra Nayak 196568997cfSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ 197568997cfSRajendra Nayak #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 198568997cfSRajendra Nayak #define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) 199568997cfSRajendra Nayak 200568997cfSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ 201568997cfSRajendra Nayak #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 202568997cfSRajendra Nayak #define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) 203568997cfSRajendra Nayak 204568997cfSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 205568997cfSRajendra Nayak #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 206568997cfSRajendra Nayak #define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) 207568997cfSRajendra Nayak 208568997cfSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 209568997cfSRajendra Nayak #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 210568997cfSRajendra Nayak #define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) 211568997cfSRajendra Nayak 212568997cfSRajendra Nayak /* Used by PRM_IRQENABLE_MPU */ 213568997cfSRajendra Nayak #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 214568997cfSRajendra Nayak #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) 215568997cfSRajendra Nayak 216568997cfSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU */ 217568997cfSRajendra Nayak #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 218568997cfSRajendra Nayak #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) 219568997cfSRajendra Nayak 220568997cfSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ 221568997cfSRajendra Nayak #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 222568997cfSRajendra Nayak #define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) 223568997cfSRajendra Nayak 224568997cfSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ 225568997cfSRajendra Nayak #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 226568997cfSRajendra Nayak #define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) 227568997cfSRajendra Nayak 228568997cfSRajendra Nayak /* Used by PRM_IRQENABLE_MPU */ 229568997cfSRajendra Nayak #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 230568997cfSRajendra Nayak #define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) 231568997cfSRajendra Nayak 232568997cfSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU */ 233568997cfSRajendra Nayak #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 234568997cfSRajendra Nayak #define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) 235568997cfSRajendra Nayak 236568997cfSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 237568997cfSRajendra Nayak #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 238568997cfSRajendra Nayak #define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) 239568997cfSRajendra Nayak 240568997cfSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 241568997cfSRajendra Nayak #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 242568997cfSRajendra Nayak #define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) 243568997cfSRajendra Nayak 244568997cfSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 245568997cfSRajendra Nayak #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 246568997cfSRajendra Nayak #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) 247568997cfSRajendra Nayak 248568997cfSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 249568997cfSRajendra Nayak #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 250568997cfSRajendra Nayak #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) 251568997cfSRajendra Nayak 252568997cfSRajendra Nayak /* Used by PM_DSS_PWRSTCTRL */ 253568997cfSRajendra Nayak #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 254568997cfSRajendra Nayak #define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) 255568997cfSRajendra Nayak 256568997cfSRajendra Nayak /* Used by PM_DSS_PWRSTCTRL */ 257568997cfSRajendra Nayak #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 258568997cfSRajendra Nayak #define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) 259568997cfSRajendra Nayak 260568997cfSRajendra Nayak /* Used by PM_DSS_PWRSTST */ 261568997cfSRajendra Nayak #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 262568997cfSRajendra Nayak #define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) 263568997cfSRajendra Nayak 264568997cfSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 265568997cfSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 266568997cfSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) 267568997cfSRajendra Nayak 268568997cfSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 269568997cfSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 270568997cfSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) 271568997cfSRajendra Nayak 272568997cfSRajendra Nayak /* Used by PM_CORE_PWRSTST */ 273568997cfSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 274568997cfSRajendra Nayak #define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) 275568997cfSRajendra Nayak 276568997cfSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 277568997cfSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 278568997cfSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) 279568997cfSRajendra Nayak 280568997cfSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 281568997cfSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 282568997cfSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) 283568997cfSRajendra Nayak 284568997cfSRajendra Nayak /* Used by PM_CORE_PWRSTST */ 285568997cfSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 286568997cfSRajendra Nayak #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) 287568997cfSRajendra Nayak 288568997cfSRajendra Nayak /* Used by RM_MPU_RSTST */ 289568997cfSRajendra Nayak #define OMAP4430_EMULATION_RST_SHIFT 0 290568997cfSRajendra Nayak #define OMAP4430_EMULATION_RST_MASK (1 << 0) 291568997cfSRajendra Nayak 292568997cfSRajendra Nayak /* Used by RM_DUCATI_RSTST */ 293568997cfSRajendra Nayak #define OMAP4430_EMULATION_RST1ST_SHIFT 3 294568997cfSRajendra Nayak #define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) 295568997cfSRajendra Nayak 296568997cfSRajendra Nayak /* Used by RM_DUCATI_RSTST */ 297568997cfSRajendra Nayak #define OMAP4430_EMULATION_RST2ST_SHIFT 4 298568997cfSRajendra Nayak #define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) 299568997cfSRajendra Nayak 300568997cfSRajendra Nayak /* Used by RM_IVAHD_RSTST */ 301568997cfSRajendra Nayak #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 302568997cfSRajendra Nayak #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) 303568997cfSRajendra Nayak 304568997cfSRajendra Nayak /* Used by RM_IVAHD_RSTST */ 305568997cfSRajendra Nayak #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 306568997cfSRajendra Nayak #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) 307568997cfSRajendra Nayak 308568997cfSRajendra Nayak /* Used by PM_EMU_PWRSTCTRL */ 309568997cfSRajendra Nayak #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 310568997cfSRajendra Nayak #define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) 311568997cfSRajendra Nayak 312568997cfSRajendra Nayak /* Used by PM_EMU_PWRSTST */ 313568997cfSRajendra Nayak #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 314568997cfSRajendra Nayak #define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) 315234f0c4cSRajendra Nayak 316234f0c4cSRajendra Nayak /* 317234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 318234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 319234f0c4cSRajendra Nayak */ 320568997cfSRajendra Nayak #define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 321568997cfSRajendra Nayak #define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) 322234f0c4cSRajendra Nayak 323234f0c4cSRajendra Nayak /* 324234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 325234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 326234f0c4cSRajendra Nayak */ 327568997cfSRajendra Nayak #define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 328568997cfSRajendra Nayak #define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) 329234f0c4cSRajendra Nayak 330234f0c4cSRajendra Nayak /* 331234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 332234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 333234f0c4cSRajendra Nayak */ 33456ef28acSRajendra Nayak #define OMAP4430_ENFUNC4_SHIFT 6 335568997cfSRajendra Nayak #define OMAP4430_ENFUNC4_MASK (1 << 6) 336234f0c4cSRajendra Nayak 337234f0c4cSRajendra Nayak /* 338234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 339234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_SETUP 340234f0c4cSRajendra Nayak */ 34156ef28acSRajendra Nayak #define OMAP4430_ENFUNC5_SHIFT 7 342568997cfSRajendra Nayak #define OMAP4430_ENFUNC5_MASK (1 << 7) 343234f0c4cSRajendra Nayak 344234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 34556ef28acSRajendra Nayak #define OMAP4430_ERRORGAIN_SHIFT 16 346568997cfSRajendra Nayak #define OMAP4430_ERRORGAIN_MASK (0xff << 16) 347234f0c4cSRajendra Nayak 348234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 34956ef28acSRajendra Nayak #define OMAP4430_ERROROFFSET_SHIFT 24 350568997cfSRajendra Nayak #define OMAP4430_ERROROFFSET_MASK (0xff << 24) 351234f0c4cSRajendra Nayak 352234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 35356ef28acSRajendra Nayak #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 354568997cfSRajendra Nayak #define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) 355234f0c4cSRajendra Nayak 356234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 35756ef28acSRajendra Nayak #define OMAP4430_FORCEUPDATE_SHIFT 1 358568997cfSRajendra Nayak #define OMAP4430_FORCEUPDATE_MASK (1 << 1) 359234f0c4cSRajendra Nayak 360234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ 36156ef28acSRajendra Nayak #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 362568997cfSRajendra Nayak #define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) 363234f0c4cSRajendra Nayak 364234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ 36556ef28acSRajendra Nayak #define OMAP4430_FORCEWKUP_EN_SHIFT 10 366568997cfSRajendra Nayak #define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) 367234f0c4cSRajendra Nayak 368234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ 36956ef28acSRajendra Nayak #define OMAP4430_FORCEWKUP_ST_SHIFT 10 370568997cfSRajendra Nayak #define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) 371568997cfSRajendra Nayak 372568997cfSRajendra Nayak /* Used by REVISION_PRM */ 373568997cfSRajendra Nayak #define OMAP4430_FUNC_SHIFT 16 374568997cfSRajendra Nayak #define OMAP4430_FUNC_MASK (0xfff << 16) 375234f0c4cSRajendra Nayak 376234f0c4cSRajendra Nayak /* Used by PM_GFX_PWRSTCTRL */ 37756ef28acSRajendra Nayak #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 378568997cfSRajendra Nayak #define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) 379234f0c4cSRajendra Nayak 380234f0c4cSRajendra Nayak /* Used by PM_GFX_PWRSTST */ 38156ef28acSRajendra Nayak #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 382568997cfSRajendra Nayak #define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) 383234f0c4cSRajendra Nayak 384234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 38556ef28acSRajendra Nayak #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 386568997cfSRajendra Nayak #define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) 387234f0c4cSRajendra Nayak 388234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 38956ef28acSRajendra Nayak #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 390568997cfSRajendra Nayak #define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) 391234f0c4cSRajendra Nayak 392234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 39356ef28acSRajendra Nayak #define OMAP4430_GLOBAL_WUEN_SHIFT 16 394568997cfSRajendra Nayak #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) 395234f0c4cSRajendra Nayak 396234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_MODE */ 39756ef28acSRajendra Nayak #define OMAP4430_HSMCODE_SHIFT 0 398568997cfSRajendra Nayak #define OMAP4430_HSMCODE_MASK (0x7 << 0) 399234f0c4cSRajendra Nayak 400234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_MODE */ 40156ef28acSRajendra Nayak #define OMAP4430_HSMODEEN_SHIFT 3 402568997cfSRajendra Nayak #define OMAP4430_HSMODEEN_MASK (1 << 3) 403234f0c4cSRajendra Nayak 404234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_CLK */ 40556ef28acSRajendra Nayak #define OMAP4430_HSSCLH_SHIFT 16 406568997cfSRajendra Nayak #define OMAP4430_HSSCLH_MASK (0xff << 16) 407234f0c4cSRajendra Nayak 408234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_CLK */ 40956ef28acSRajendra Nayak #define OMAP4430_HSSCLL_SHIFT 24 410568997cfSRajendra Nayak #define OMAP4430_HSSCLL_MASK (0xff << 24) 411234f0c4cSRajendra Nayak 412234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 41356ef28acSRajendra Nayak #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 414568997cfSRajendra Nayak #define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) 415234f0c4cSRajendra Nayak 416234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 41756ef28acSRajendra Nayak #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 418568997cfSRajendra Nayak #define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) 419234f0c4cSRajendra Nayak 420234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTST */ 42156ef28acSRajendra Nayak #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 422568997cfSRajendra Nayak #define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) 423234f0c4cSRajendra Nayak 424234f0c4cSRajendra Nayak /* Used by RM_MPU_RSTST */ 42556ef28acSRajendra Nayak #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 426568997cfSRajendra Nayak #define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) 427234f0c4cSRajendra Nayak 428234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTST */ 42956ef28acSRajendra Nayak #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 430568997cfSRajendra Nayak #define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) 431234f0c4cSRajendra Nayak 432234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTST */ 43356ef28acSRajendra Nayak #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 434568997cfSRajendra Nayak #define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) 435234f0c4cSRajendra Nayak 436234f0c4cSRajendra Nayak /* Used by RM_IVAHD_RSTST */ 43756ef28acSRajendra Nayak #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 438568997cfSRajendra Nayak #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) 439234f0c4cSRajendra Nayak 440234f0c4cSRajendra Nayak /* Used by RM_IVAHD_RSTST */ 44156ef28acSRajendra Nayak #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 442568997cfSRajendra Nayak #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) 443234f0c4cSRajendra Nayak 444234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 44556ef28acSRajendra Nayak #define OMAP4430_ICEPICK_RST_SHIFT 9 446568997cfSRajendra Nayak #define OMAP4430_ICEPICK_RST_MASK (1 << 9) 447234f0c4cSRajendra Nayak 448234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 44956ef28acSRajendra Nayak #define OMAP4430_INITVDD_SHIFT 2 450568997cfSRajendra Nayak #define OMAP4430_INITVDD_MASK (1 << 2) 451234f0c4cSRajendra Nayak 452234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 45356ef28acSRajendra Nayak #define OMAP4430_INITVOLTAGE_SHIFT 8 454568997cfSRajendra Nayak #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) 455234f0c4cSRajendra Nayak 456234f0c4cSRajendra Nayak /* 457568997cfSRajendra Nayak * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, 458568997cfSRajendra Nayak * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, 459568997cfSRajendra Nayak * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST 460234f0c4cSRajendra Nayak */ 46156ef28acSRajendra Nayak #define OMAP4430_INTRANSITION_SHIFT 20 462568997cfSRajendra Nayak #define OMAP4430_INTRANSITION_MASK (1 << 20) 463234f0c4cSRajendra Nayak 464234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 46556ef28acSRajendra Nayak #define OMAP4430_IO_EN_SHIFT 9 466568997cfSRajendra Nayak #define OMAP4430_IO_EN_MASK (1 << 9) 467234f0c4cSRajendra Nayak 468234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 46956ef28acSRajendra Nayak #define OMAP4430_IO_ON_STATUS_SHIFT 5 470568997cfSRajendra Nayak #define OMAP4430_IO_ON_STATUS_MASK (1 << 5) 471234f0c4cSRajendra Nayak 472234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 47356ef28acSRajendra Nayak #define OMAP4430_IO_ST_SHIFT 9 474568997cfSRajendra Nayak #define OMAP4430_IO_ST_MASK (1 << 9) 475234f0c4cSRajendra Nayak 476234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 47756ef28acSRajendra Nayak #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 478568997cfSRajendra Nayak #define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) 479234f0c4cSRajendra Nayak 480234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 48156ef28acSRajendra Nayak #define OMAP4430_ISOCLK_STATUS_SHIFT 1 482568997cfSRajendra Nayak #define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) 483234f0c4cSRajendra Nayak 484234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 48556ef28acSRajendra Nayak #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 486568997cfSRajendra Nayak #define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) 487234f0c4cSRajendra Nayak 488234f0c4cSRajendra Nayak /* Used by PRM_IO_COUNT */ 48956ef28acSRajendra Nayak #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 490568997cfSRajendra Nayak #define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) 491234f0c4cSRajendra Nayak 492234f0c4cSRajendra Nayak /* Used by PM_L3INIT_PWRSTCTRL */ 49356ef28acSRajendra Nayak #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 494568997cfSRajendra Nayak #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) 495234f0c4cSRajendra Nayak 496234f0c4cSRajendra Nayak /* Used by PM_L3INIT_PWRSTCTRL */ 49756ef28acSRajendra Nayak #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 498568997cfSRajendra Nayak #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) 499234f0c4cSRajendra Nayak 500234f0c4cSRajendra Nayak /* Used by PM_L3INIT_PWRSTST */ 50156ef28acSRajendra Nayak #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 502568997cfSRajendra Nayak #define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) 503234f0c4cSRajendra Nayak 504234f0c4cSRajendra Nayak /* 505568997cfSRajendra Nayak * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, 506568997cfSRajendra Nayak * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST 507568997cfSRajendra Nayak */ 508568997cfSRajendra Nayak #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 509568997cfSRajendra Nayak #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) 510568997cfSRajendra Nayak 511568997cfSRajendra Nayak /* 512568997cfSRajendra Nayak * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, 513568997cfSRajendra Nayak * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, 514568997cfSRajendra Nayak * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL 515234f0c4cSRajendra Nayak */ 51656ef28acSRajendra Nayak #define OMAP4430_LOGICRETSTATE_SHIFT 2 517568997cfSRajendra Nayak #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) 518234f0c4cSRajendra Nayak 519234f0c4cSRajendra Nayak /* 520568997cfSRajendra Nayak * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, 521568997cfSRajendra Nayak * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, 522568997cfSRajendra Nayak * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST 523234f0c4cSRajendra Nayak */ 52456ef28acSRajendra Nayak #define OMAP4430_LOGICSTATEST_SHIFT 2 525568997cfSRajendra Nayak #define OMAP4430_LOGICSTATEST_MASK (1 << 2) 526234f0c4cSRajendra Nayak 527234f0c4cSRajendra Nayak /* 528568997cfSRajendra Nayak * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, 529234f0c4cSRajendra Nayak * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, 530234f0c4cSRajendra Nayak * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, 531234f0c4cSRajendra Nayak * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, 532568997cfSRajendra Nayak * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, 533568997cfSRajendra Nayak * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, 534568997cfSRajendra Nayak * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, 535568997cfSRajendra Nayak * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, 536568997cfSRajendra Nayak * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, 537568997cfSRajendra Nayak * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, 538568997cfSRajendra Nayak * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, 539568997cfSRajendra Nayak * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, 540568997cfSRajendra Nayak * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, 541568997cfSRajendra Nayak * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, 542568997cfSRajendra Nayak * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, 543568997cfSRajendra Nayak * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, 544568997cfSRajendra Nayak * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, 545568997cfSRajendra Nayak * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, 546568997cfSRajendra Nayak * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, 547568997cfSRajendra Nayak * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, 548568997cfSRajendra Nayak * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, 549568997cfSRajendra Nayak * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, 550568997cfSRajendra Nayak * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, 551568997cfSRajendra Nayak * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, 552568997cfSRajendra Nayak * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, 553568997cfSRajendra Nayak * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, 554568997cfSRajendra Nayak * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, 555568997cfSRajendra Nayak * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, 556568997cfSRajendra Nayak * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, 557568997cfSRajendra Nayak * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, 558568997cfSRajendra Nayak * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, 559568997cfSRajendra Nayak * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, 560568997cfSRajendra Nayak * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, 561568997cfSRajendra Nayak * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT 562234f0c4cSRajendra Nayak */ 56356ef28acSRajendra Nayak #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 564568997cfSRajendra Nayak #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) 565234f0c4cSRajendra Nayak 566234f0c4cSRajendra Nayak /* 567234f0c4cSRajendra Nayak * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, 568568997cfSRajendra Nayak * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, 569568997cfSRajendra Nayak * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, 570568997cfSRajendra Nayak * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, 571568997cfSRajendra Nayak * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, 572568997cfSRajendra Nayak * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, 573234f0c4cSRajendra Nayak * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, 574234f0c4cSRajendra Nayak * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, 575568997cfSRajendra Nayak * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, 576568997cfSRajendra Nayak * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, 577568997cfSRajendra Nayak * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, 578568997cfSRajendra Nayak * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, 579568997cfSRajendra Nayak * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, 580568997cfSRajendra Nayak * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, 581568997cfSRajendra Nayak * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, 582568997cfSRajendra Nayak * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, 583568997cfSRajendra Nayak * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT 584234f0c4cSRajendra Nayak */ 58556ef28acSRajendra Nayak #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 586568997cfSRajendra Nayak #define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) 587234f0c4cSRajendra Nayak 588234f0c4cSRajendra Nayak /* Used by RM_ABE_AESS_CONTEXT */ 58956ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 590568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) 591234f0c4cSRajendra Nayak 592234f0c4cSRajendra Nayak /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ 59356ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 594568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) 595234f0c4cSRajendra Nayak 596234f0c4cSRajendra Nayak /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ 59756ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 598568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) 599234f0c4cSRajendra Nayak 600234f0c4cSRajendra Nayak /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ 60156ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 602568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) 603234f0c4cSRajendra Nayak 604234f0c4cSRajendra Nayak /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ 60556ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 606568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) 607234f0c4cSRajendra Nayak 608234f0c4cSRajendra Nayak /* 609234f0c4cSRajendra Nayak * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, 610234f0c4cSRajendra Nayak * RM_SDMA_SDMA_CONTEXT 611234f0c4cSRajendra Nayak */ 61256ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 613568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) 614234f0c4cSRajendra Nayak 615234f0c4cSRajendra Nayak /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ 61656ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 617568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) 618234f0c4cSRajendra Nayak 619234f0c4cSRajendra Nayak /* Used by RM_DUCATI_DUCATI_CONTEXT */ 62056ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 621568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) 622234f0c4cSRajendra Nayak 623234f0c4cSRajendra Nayak /* Used by RM_DUCATI_DUCATI_CONTEXT */ 62456ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 625568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) 626234f0c4cSRajendra Nayak 627234f0c4cSRajendra Nayak /* Used by RM_EMU_DEBUGSS_CONTEXT */ 62856ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 629568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) 630234f0c4cSRajendra Nayak 631234f0c4cSRajendra Nayak /* Used by RM_GFX_GFX_CONTEXT */ 63256ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 633568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) 634234f0c4cSRajendra Nayak 635234f0c4cSRajendra Nayak /* Used by RM_IVAHD_IVAHD_CONTEXT */ 63656ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 637568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) 638234f0c4cSRajendra Nayak 639234f0c4cSRajendra Nayak /* 640234f0c4cSRajendra Nayak * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, 641234f0c4cSRajendra Nayak * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, 642234f0c4cSRajendra Nayak * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT, 643234f0c4cSRajendra Nayak * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, 644234f0c4cSRajendra Nayak * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT 645234f0c4cSRajendra Nayak */ 64656ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 647568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) 648234f0c4cSRajendra Nayak 649234f0c4cSRajendra Nayak /* Used by RM_MPU_MPU_CONTEXT */ 65056ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 651568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) 652234f0c4cSRajendra Nayak 653234f0c4cSRajendra Nayak /* Used by RM_MPU_MPU_CONTEXT */ 65456ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 655568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) 656234f0c4cSRajendra Nayak 657234f0c4cSRajendra Nayak /* Used by RM_MPU_MPU_CONTEXT */ 65856ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 659568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) 660234f0c4cSRajendra Nayak 661234f0c4cSRajendra Nayak /* 662234f0c4cSRajendra Nayak * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, 663234f0c4cSRajendra Nayak * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, 664234f0c4cSRajendra Nayak * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT 665234f0c4cSRajendra Nayak */ 66656ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 667568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) 668234f0c4cSRajendra Nayak 669234f0c4cSRajendra Nayak /* 670234f0c4cSRajendra Nayak * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, 671234f0c4cSRajendra Nayak * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT 672234f0c4cSRajendra Nayak */ 67356ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 674568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) 675234f0c4cSRajendra Nayak 676234f0c4cSRajendra Nayak /* 677234f0c4cSRajendra Nayak * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, 678234f0c4cSRajendra Nayak * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, 679234f0c4cSRajendra Nayak * RM_L4SEC_CRYPTODMA_CONTEXT 680234f0c4cSRajendra Nayak */ 68156ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 682568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) 683234f0c4cSRajendra Nayak 684234f0c4cSRajendra Nayak /* Used by RM_IVAHD_SL2_CONTEXT */ 68556ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 686568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) 687234f0c4cSRajendra Nayak 688234f0c4cSRajendra Nayak /* Used by RM_IVAHD_IVAHD_CONTEXT */ 68956ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 690568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) 691234f0c4cSRajendra Nayak 692234f0c4cSRajendra Nayak /* Used by RM_IVAHD_IVAHD_CONTEXT */ 69356ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 694568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) 695234f0c4cSRajendra Nayak 696234f0c4cSRajendra Nayak /* Used by RM_TESLA_TESLA_CONTEXT */ 69756ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 698568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) 699234f0c4cSRajendra Nayak 700234f0c4cSRajendra Nayak /* Used by RM_TESLA_TESLA_CONTEXT */ 70156ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 702568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) 703234f0c4cSRajendra Nayak 704234f0c4cSRajendra Nayak /* Used by RM_TESLA_TESLA_CONTEXT */ 70556ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 706568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) 707234f0c4cSRajendra Nayak 708234f0c4cSRajendra Nayak /* Used by RM_WKUP_SARRAM_CONTEXT */ 70956ef28acSRajendra Nayak #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 710568997cfSRajendra Nayak #define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) 711234f0c4cSRajendra Nayak 712234f0c4cSRajendra Nayak /* 713568997cfSRajendra Nayak * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, 714568997cfSRajendra Nayak * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, 715568997cfSRajendra Nayak * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL 716234f0c4cSRajendra Nayak */ 71756ef28acSRajendra Nayak #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 718568997cfSRajendra Nayak #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) 719234f0c4cSRajendra Nayak 720234f0c4cSRajendra Nayak /* Used by PRM_MODEM_IF_CTRL */ 72156ef28acSRajendra Nayak #define OMAP4430_MODEM_READY_SHIFT 1 722568997cfSRajendra Nayak #define OMAP4430_MODEM_READY_MASK (1 << 1) 723234f0c4cSRajendra Nayak 724234f0c4cSRajendra Nayak /* Used by PRM_MODEM_IF_CTRL */ 72556ef28acSRajendra Nayak #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 726568997cfSRajendra Nayak #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) 727234f0c4cSRajendra Nayak 728234f0c4cSRajendra Nayak /* Used by PRM_MODEM_IF_CTRL */ 72956ef28acSRajendra Nayak #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 730568997cfSRajendra Nayak #define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) 731234f0c4cSRajendra Nayak 732234f0c4cSRajendra Nayak /* Used by PRM_MODEM_IF_CTRL */ 73356ef28acSRajendra Nayak #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 734568997cfSRajendra Nayak #define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) 735234f0c4cSRajendra Nayak 736234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 73756ef28acSRajendra Nayak #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 738568997cfSRajendra Nayak #define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) 739234f0c4cSRajendra Nayak 740234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 74156ef28acSRajendra Nayak #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 742568997cfSRajendra Nayak #define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) 743234f0c4cSRajendra Nayak 744234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTST */ 74556ef28acSRajendra Nayak #define OMAP4430_MPU_L1_STATEST_SHIFT 4 746568997cfSRajendra Nayak #define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) 747234f0c4cSRajendra Nayak 748234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 74956ef28acSRajendra Nayak #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 750568997cfSRajendra Nayak #define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) 751234f0c4cSRajendra Nayak 752234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 75356ef28acSRajendra Nayak #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 754568997cfSRajendra Nayak #define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) 755234f0c4cSRajendra Nayak 756234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTST */ 75756ef28acSRajendra Nayak #define OMAP4430_MPU_L2_STATEST_SHIFT 6 758568997cfSRajendra Nayak #define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) 759234f0c4cSRajendra Nayak 760234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 76156ef28acSRajendra Nayak #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 762568997cfSRajendra Nayak #define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) 763234f0c4cSRajendra Nayak 764234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTCTRL */ 76556ef28acSRajendra Nayak #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 766568997cfSRajendra Nayak #define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) 767234f0c4cSRajendra Nayak 768234f0c4cSRajendra Nayak /* Used by PM_MPU_PWRSTST */ 76956ef28acSRajendra Nayak #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 770568997cfSRajendra Nayak #define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) 771234f0c4cSRajendra Nayak 772234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 77356ef28acSRajendra Nayak #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 774568997cfSRajendra Nayak #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) 775234f0c4cSRajendra Nayak 776234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 77756ef28acSRajendra Nayak #define OMAP4430_MPU_WDT_RST_SHIFT 3 778568997cfSRajendra Nayak #define OMAP4430_MPU_WDT_RST_MASK (1 << 3) 779234f0c4cSRajendra Nayak 780234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTCTRL */ 78156ef28acSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 782568997cfSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) 783234f0c4cSRajendra Nayak 784234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTCTRL */ 78556ef28acSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 786568997cfSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) 787234f0c4cSRajendra Nayak 788234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTST */ 78956ef28acSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 790568997cfSRajendra Nayak #define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) 791234f0c4cSRajendra Nayak 792234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 79356ef28acSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 794568997cfSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) 795234f0c4cSRajendra Nayak 796234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTCTRL */ 79756ef28acSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 798568997cfSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) 799234f0c4cSRajendra Nayak 800234f0c4cSRajendra Nayak /* Used by PM_CORE_PWRSTST */ 80156ef28acSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 802568997cfSRajendra Nayak #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) 803234f0c4cSRajendra Nayak 804234f0c4cSRajendra Nayak /* 805234f0c4cSRajendra Nayak * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 806234f0c4cSRajendra Nayak * PRM_VC_VAL_CMD_VDD_MPU_L 807234f0c4cSRajendra Nayak */ 80856ef28acSRajendra Nayak #define OMAP4430_OFF_SHIFT 0 809568997cfSRajendra Nayak #define OMAP4430_OFF_MASK (0xff << 0) 810234f0c4cSRajendra Nayak 811234f0c4cSRajendra Nayak /* 812234f0c4cSRajendra Nayak * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 813234f0c4cSRajendra Nayak * PRM_VC_VAL_CMD_VDD_MPU_L 814234f0c4cSRajendra Nayak */ 81556ef28acSRajendra Nayak #define OMAP4430_ON_SHIFT 24 816568997cfSRajendra Nayak #define OMAP4430_ON_MASK (0xff << 24) 817234f0c4cSRajendra Nayak 818234f0c4cSRajendra Nayak /* 819234f0c4cSRajendra Nayak * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 820234f0c4cSRajendra Nayak * PRM_VC_VAL_CMD_VDD_MPU_L 821234f0c4cSRajendra Nayak */ 82256ef28acSRajendra Nayak #define OMAP4430_ONLP_SHIFT 16 823568997cfSRajendra Nayak #define OMAP4430_ONLP_MASK (0xff << 16) 824234f0c4cSRajendra Nayak 825234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 82656ef28acSRajendra Nayak #define OMAP4430_OPP_CHANGE_SHIFT 2 827568997cfSRajendra Nayak #define OMAP4430_OPP_CHANGE_MASK (1 << 2) 828234f0c4cSRajendra Nayak 829234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 83056ef28acSRajendra Nayak #define OMAP4430_OPP_SEL_SHIFT 0 831568997cfSRajendra Nayak #define OMAP4430_OPP_SEL_MASK (0x3 << 0) 832234f0c4cSRajendra Nayak 833234f0c4cSRajendra Nayak /* Used by PRM_SRAM_COUNT */ 83456ef28acSRajendra Nayak #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 835568997cfSRajendra Nayak #define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) 836234f0c4cSRajendra Nayak 837234f0c4cSRajendra Nayak /* Used by PRM_PSCON_COUNT */ 83856ef28acSRajendra Nayak #define OMAP4430_PCHARGE_TIME_SHIFT 0 839568997cfSRajendra Nayak #define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) 840234f0c4cSRajendra Nayak 841234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTCTRL */ 84256ef28acSRajendra Nayak #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 843568997cfSRajendra Nayak #define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) 844234f0c4cSRajendra Nayak 845234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTCTRL */ 84656ef28acSRajendra Nayak #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 847568997cfSRajendra Nayak #define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) 848234f0c4cSRajendra Nayak 849234f0c4cSRajendra Nayak /* Used by PM_ABE_PWRSTST */ 85056ef28acSRajendra Nayak #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 851568997cfSRajendra Nayak #define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) 852234f0c4cSRajendra Nayak 853234f0c4cSRajendra Nayak /* Used by PRM_PHASE1_CNDP */ 85456ef28acSRajendra Nayak #define OMAP4430_PHASE1_CNDP_SHIFT 0 855568997cfSRajendra Nayak #define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) 856234f0c4cSRajendra Nayak 857234f0c4cSRajendra Nayak /* Used by PRM_PHASE2A_CNDP */ 85856ef28acSRajendra Nayak #define OMAP4430_PHASE2A_CNDP_SHIFT 0 859568997cfSRajendra Nayak #define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) 860234f0c4cSRajendra Nayak 861234f0c4cSRajendra Nayak /* Used by PRM_PHASE2B_CNDP */ 86256ef28acSRajendra Nayak #define OMAP4430_PHASE2B_CNDP_SHIFT 0 863568997cfSRajendra Nayak #define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) 864234f0c4cSRajendra Nayak 865234f0c4cSRajendra Nayak /* Used by PRM_PSCON_COUNT */ 86656ef28acSRajendra Nayak #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 867568997cfSRajendra Nayak #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) 868234f0c4cSRajendra Nayak 869234f0c4cSRajendra Nayak /* 870568997cfSRajendra Nayak * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, 871568997cfSRajendra Nayak * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, 872568997cfSRajendra Nayak * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, 873568997cfSRajendra Nayak * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL 874234f0c4cSRajendra Nayak */ 87556ef28acSRajendra Nayak #define OMAP4430_POWERSTATE_SHIFT 0 876568997cfSRajendra Nayak #define OMAP4430_POWERSTATE_MASK (0x3 << 0) 877234f0c4cSRajendra Nayak 878234f0c4cSRajendra Nayak /* 879568997cfSRajendra Nayak * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, 880568997cfSRajendra Nayak * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, 881568997cfSRajendra Nayak * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST 882234f0c4cSRajendra Nayak */ 88356ef28acSRajendra Nayak #define OMAP4430_POWERSTATEST_SHIFT 0 884568997cfSRajendra Nayak #define OMAP4430_POWERSTATEST_MASK (0x3 << 0) 885234f0c4cSRajendra Nayak 886234f0c4cSRajendra Nayak /* Used by PRM_PWRREQCTRL */ 88756ef28acSRajendra Nayak #define OMAP4430_PWRREQ_COND_SHIFT 0 888568997cfSRajendra Nayak #define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) 889234f0c4cSRajendra Nayak 890234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 89156ef28acSRajendra Nayak #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 892568997cfSRajendra Nayak #define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) 893234f0c4cSRajendra Nayak 894234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 89556ef28acSRajendra Nayak #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 896568997cfSRajendra Nayak #define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) 897234f0c4cSRajendra Nayak 898234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 89956ef28acSRajendra Nayak #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 900568997cfSRajendra Nayak #define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) 901234f0c4cSRajendra Nayak 902234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 90356ef28acSRajendra Nayak #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 904568997cfSRajendra Nayak #define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) 905234f0c4cSRajendra Nayak 906234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 90756ef28acSRajendra Nayak #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 908568997cfSRajendra Nayak #define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) 909234f0c4cSRajendra Nayak 910234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 91156ef28acSRajendra Nayak #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 912568997cfSRajendra Nayak #define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) 913234f0c4cSRajendra Nayak 914234f0c4cSRajendra Nayak /* 915234f0c4cSRajendra Nayak * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 916234f0c4cSRajendra Nayak * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 917234f0c4cSRajendra Nayak * PRM_VOLTSETUP_MPU_RET_SLEEP 918234f0c4cSRajendra Nayak */ 91956ef28acSRajendra Nayak #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 920568997cfSRajendra Nayak #define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) 921234f0c4cSRajendra Nayak 922234f0c4cSRajendra Nayak /* 923234f0c4cSRajendra Nayak * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 924234f0c4cSRajendra Nayak * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 925234f0c4cSRajendra Nayak * PRM_VOLTSETUP_MPU_RET_SLEEP 926234f0c4cSRajendra Nayak */ 92756ef28acSRajendra Nayak #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 928568997cfSRajendra Nayak #define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) 929234f0c4cSRajendra Nayak 930234f0c4cSRajendra Nayak /* 931234f0c4cSRajendra Nayak * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 932234f0c4cSRajendra Nayak * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 933234f0c4cSRajendra Nayak * PRM_VOLTSETUP_MPU_RET_SLEEP 934234f0c4cSRajendra Nayak */ 93556ef28acSRajendra Nayak #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 936568997cfSRajendra Nayak #define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) 937234f0c4cSRajendra Nayak 938234f0c4cSRajendra Nayak /* 939234f0c4cSRajendra Nayak * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 940234f0c4cSRajendra Nayak * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, 941234f0c4cSRajendra Nayak * PRM_VOLTSETUP_MPU_RET_SLEEP 942234f0c4cSRajendra Nayak */ 94356ef28acSRajendra Nayak #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 944568997cfSRajendra Nayak #define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) 945234f0c4cSRajendra Nayak 946234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 94756ef28acSRajendra Nayak #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 948568997cfSRajendra Nayak #define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) 949234f0c4cSRajendra Nayak 950234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 95156ef28acSRajendra Nayak #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 952568997cfSRajendra Nayak #define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) 953234f0c4cSRajendra Nayak 954234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 95556ef28acSRajendra Nayak #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 956568997cfSRajendra Nayak #define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) 957234f0c4cSRajendra Nayak 958234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_BYPASS */ 95956ef28acSRajendra Nayak #define OMAP4430_REGADDR_SHIFT 8 960568997cfSRajendra Nayak #define OMAP4430_REGADDR_MASK (0xff << 8) 961234f0c4cSRajendra Nayak 962234f0c4cSRajendra Nayak /* 963234f0c4cSRajendra Nayak * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 964234f0c4cSRajendra Nayak * PRM_VC_VAL_CMD_VDD_MPU_L 965234f0c4cSRajendra Nayak */ 96656ef28acSRajendra Nayak #define OMAP4430_RET_SHIFT 8 967568997cfSRajendra Nayak #define OMAP4430_RET_MASK (0xff << 8) 968234f0c4cSRajendra Nayak 969234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTCTRL */ 97056ef28acSRajendra Nayak #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 971568997cfSRajendra Nayak #define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) 972234f0c4cSRajendra Nayak 973234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTCTRL */ 97456ef28acSRajendra Nayak #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 975568997cfSRajendra Nayak #define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) 976234f0c4cSRajendra Nayak 977234f0c4cSRajendra Nayak /* Used by PM_L4PER_PWRSTST */ 97856ef28acSRajendra Nayak #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 979568997cfSRajendra Nayak #define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) 980234f0c4cSRajendra Nayak 981234f0c4cSRajendra Nayak /* 982234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 983234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_CTRL 984234f0c4cSRajendra Nayak */ 98556ef28acSRajendra Nayak #define OMAP4430_RETMODE_ENABLE_SHIFT 0 986568997cfSRajendra Nayak #define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) 987234f0c4cSRajendra Nayak 988568997cfSRajendra Nayak /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ 98956ef28acSRajendra Nayak #define OMAP4430_RST1_SHIFT 0 990568997cfSRajendra Nayak #define OMAP4430_RST1_MASK (1 << 0) 991234f0c4cSRajendra Nayak 992568997cfSRajendra Nayak /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ 99356ef28acSRajendra Nayak #define OMAP4430_RST1ST_SHIFT 0 994568997cfSRajendra Nayak #define OMAP4430_RST1ST_MASK (1 << 0) 995234f0c4cSRajendra Nayak 996568997cfSRajendra Nayak /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ 99756ef28acSRajendra Nayak #define OMAP4430_RST2_SHIFT 1 998568997cfSRajendra Nayak #define OMAP4430_RST2_MASK (1 << 1) 999234f0c4cSRajendra Nayak 1000568997cfSRajendra Nayak /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ 100156ef28acSRajendra Nayak #define OMAP4430_RST2ST_SHIFT 1 1002568997cfSRajendra Nayak #define OMAP4430_RST2ST_MASK (1 << 1) 1003234f0c4cSRajendra Nayak 1004234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ 100556ef28acSRajendra Nayak #define OMAP4430_RST3_SHIFT 2 1006568997cfSRajendra Nayak #define OMAP4430_RST3_MASK (1 << 2) 1007234f0c4cSRajendra Nayak 1008234f0c4cSRajendra Nayak /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ 100956ef28acSRajendra Nayak #define OMAP4430_RST3ST_SHIFT 2 1010568997cfSRajendra Nayak #define OMAP4430_RST3ST_MASK (1 << 2) 1011234f0c4cSRajendra Nayak 1012234f0c4cSRajendra Nayak /* Used by PRM_RSTTIME */ 101356ef28acSRajendra Nayak #define OMAP4430_RSTTIME1_SHIFT 0 1014568997cfSRajendra Nayak #define OMAP4430_RSTTIME1_MASK (0x3ff << 0) 1015234f0c4cSRajendra Nayak 1016234f0c4cSRajendra Nayak /* Used by PRM_RSTTIME */ 101756ef28acSRajendra Nayak #define OMAP4430_RSTTIME2_SHIFT 10 1018568997cfSRajendra Nayak #define OMAP4430_RSTTIME2_MASK (0x1f << 10) 1019234f0c4cSRajendra Nayak 1020234f0c4cSRajendra Nayak /* Used by PRM_RSTCTRL */ 102156ef28acSRajendra Nayak #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 1022568997cfSRajendra Nayak #define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) 1023234f0c4cSRajendra Nayak 1024234f0c4cSRajendra Nayak /* Used by PRM_RSTCTRL */ 102556ef28acSRajendra Nayak #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 1026568997cfSRajendra Nayak #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) 1027568997cfSRajendra Nayak 1028568997cfSRajendra Nayak /* Used by REVISION_PRM */ 1029568997cfSRajendra Nayak #define OMAP4430_R_RTL_SHIFT 11 1030568997cfSRajendra Nayak #define OMAP4430_R_RTL_MASK (0x1f << 11) 1031234f0c4cSRajendra Nayak 1032234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 103356ef28acSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 1034568997cfSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) 1035234f0c4cSRajendra Nayak 1036234f0c4cSRajendra Nayak /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ 103756ef28acSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 1038568997cfSRajendra Nayak #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) 1039234f0c4cSRajendra Nayak 1040234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 104156ef28acSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 1042568997cfSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) 1043234f0c4cSRajendra Nayak 1044234f0c4cSRajendra Nayak /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ 104556ef28acSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 1046568997cfSRajendra Nayak #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) 1047234f0c4cSRajendra Nayak 1048234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_CHANNEL */ 104956ef28acSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 1050568997cfSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) 1051234f0c4cSRajendra Nayak 1052234f0c4cSRajendra Nayak /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ 105356ef28acSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 1054568997cfSRajendra Nayak #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) 1055568997cfSRajendra Nayak 1056568997cfSRajendra Nayak /* Used by REVISION_PRM */ 1057568997cfSRajendra Nayak #define OMAP4430_SCHEME_SHIFT 30 1058568997cfSRajendra Nayak #define OMAP4430_SCHEME_MASK (0x3 << 30) 1059234f0c4cSRajendra Nayak 1060234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_CLK */ 106156ef28acSRajendra Nayak #define OMAP4430_SCLH_SHIFT 0 1062568997cfSRajendra Nayak #define OMAP4430_SCLH_MASK (0xff << 0) 1063234f0c4cSRajendra Nayak 1064234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_CLK */ 106556ef28acSRajendra Nayak #define OMAP4430_SCLL_SHIFT 8 1066568997cfSRajendra Nayak #define OMAP4430_SCLL_MASK (0xff << 8) 1067234f0c4cSRajendra Nayak 1068234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 106956ef28acSRajendra Nayak #define OMAP4430_SECURE_WDT_RST_SHIFT 4 1070568997cfSRajendra Nayak #define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) 1071234f0c4cSRajendra Nayak 1072234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 107356ef28acSRajendra Nayak #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 1074568997cfSRajendra Nayak #define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) 1075234f0c4cSRajendra Nayak 1076234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 107756ef28acSRajendra Nayak #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 1078568997cfSRajendra Nayak #define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) 1079234f0c4cSRajendra Nayak 1080234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTST */ 108156ef28acSRajendra Nayak #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 1082568997cfSRajendra Nayak #define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) 1083234f0c4cSRajendra Nayak 1084234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_BYPASS */ 108556ef28acSRajendra Nayak #define OMAP4430_SLAVEADDR_SHIFT 0 1086568997cfSRajendra Nayak #define OMAP4430_SLAVEADDR_MASK (0x7f << 0) 1087234f0c4cSRajendra Nayak 1088234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 108956ef28acSRajendra Nayak #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 1090568997cfSRajendra Nayak #define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) 1091234f0c4cSRajendra Nayak 1092234f0c4cSRajendra Nayak /* Used by PRM_SRAM_COUNT */ 109356ef28acSRajendra Nayak #define OMAP4430_SLPCNT_VALUE_SHIFT 16 1094568997cfSRajendra Nayak #define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) 1095234f0c4cSRajendra Nayak 1096234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ 109756ef28acSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 1098568997cfSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) 1099234f0c4cSRajendra Nayak 1100234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ 110156ef28acSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 1102568997cfSRajendra Nayak #define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) 1103568997cfSRajendra Nayak 1104568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1105568997cfSRajendra Nayak #define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 1106568997cfSRajendra Nayak #define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) 1107568997cfSRajendra Nayak 1108568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1109568997cfSRajendra Nayak #define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 1110568997cfSRajendra Nayak #define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) 1111568997cfSRajendra Nayak 1112568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1113568997cfSRajendra Nayak #define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 1114568997cfSRajendra Nayak #define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) 1115568997cfSRajendra Nayak 1116568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1117568997cfSRajendra Nayak #define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 1118568997cfSRajendra Nayak #define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) 1119568997cfSRajendra Nayak 1120568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1121568997cfSRajendra Nayak #define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 1122568997cfSRajendra Nayak #define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) 1123568997cfSRajendra Nayak 1124568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1125568997cfSRajendra Nayak #define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 1126568997cfSRajendra Nayak #define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) 1127568997cfSRajendra Nayak 1128568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1129568997cfSRajendra Nayak #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 1130568997cfSRajendra Nayak #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) 1131568997cfSRajendra Nayak 1132568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1133568997cfSRajendra Nayak #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 1134568997cfSRajendra Nayak #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) 1135568997cfSRajendra Nayak 1136568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1137568997cfSRajendra Nayak #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 1138568997cfSRajendra Nayak #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) 1139234f0c4cSRajendra Nayak 1140234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 114156ef28acSRajendra Nayak #define OMAP4430_SR2EN_SHIFT 0 1142568997cfSRajendra Nayak #define OMAP4430_SR2EN_MASK (1 << 0) 1143234f0c4cSRajendra Nayak 1144234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 114556ef28acSRajendra Nayak #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 1146568997cfSRajendra Nayak #define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) 1147234f0c4cSRajendra Nayak 1148234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 114956ef28acSRajendra Nayak #define OMAP4430_SR2_STATUS_SHIFT 3 1150568997cfSRajendra Nayak #define OMAP4430_SR2_STATUS_MASK (0x3 << 3) 1151234f0c4cSRajendra Nayak 1152234f0c4cSRajendra Nayak /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 115356ef28acSRajendra Nayak #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 1154568997cfSRajendra Nayak #define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) 1155234f0c4cSRajendra Nayak 1156234f0c4cSRajendra Nayak /* 1157234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 1158234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_CTRL 1159234f0c4cSRajendra Nayak */ 116056ef28acSRajendra Nayak #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 1161568997cfSRajendra Nayak #define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) 1162234f0c4cSRajendra Nayak 1163234f0c4cSRajendra Nayak /* 1164234f0c4cSRajendra Nayak * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 1165234f0c4cSRajendra Nayak * PRM_LDO_SRAM_MPU_CTRL 1166234f0c4cSRajendra Nayak */ 116756ef28acSRajendra Nayak #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 1168568997cfSRajendra Nayak #define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) 1169234f0c4cSRajendra Nayak 1170234f0c4cSRajendra Nayak /* Used by PRM_VC_CFG_I2C_MODE */ 117156ef28acSRajendra Nayak #define OMAP4430_SRMODEEN_SHIFT 4 1172568997cfSRajendra Nayak #define OMAP4430_SRMODEEN_MASK (1 << 4) 1173234f0c4cSRajendra Nayak 1174234f0c4cSRajendra Nayak /* Used by PRM_VOLTSETUP_WARMRESET */ 117556ef28acSRajendra Nayak #define OMAP4430_STABLE_COUNT_SHIFT 0 1176568997cfSRajendra Nayak #define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) 1177234f0c4cSRajendra Nayak 1178234f0c4cSRajendra Nayak /* Used by PRM_VOLTSETUP_WARMRESET */ 117956ef28acSRajendra Nayak #define OMAP4430_STABLE_PRESCAL_SHIFT 8 1180568997cfSRajendra Nayak #define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) 1181568997cfSRajendra Nayak 1182568997cfSRajendra Nayak /* Used by PRM_LDO_BANDGAP_SETUP */ 1183568997cfSRajendra Nayak #define OMAP4430_STARTUP_COUNT_SHIFT 0 1184568997cfSRajendra Nayak #define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) 1185568997cfSRajendra Nayak 1186568997cfSRajendra Nayak /* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ 1187568997cfSRajendra Nayak #define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 1188568997cfSRajendra Nayak #define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) 1189234f0c4cSRajendra Nayak 1190234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 119156ef28acSRajendra Nayak #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 1192568997cfSRajendra Nayak #define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) 1193234f0c4cSRajendra Nayak 1194234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 119556ef28acSRajendra Nayak #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 1196568997cfSRajendra Nayak #define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) 1197234f0c4cSRajendra Nayak 1198234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTST */ 119956ef28acSRajendra Nayak #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 1200568997cfSRajendra Nayak #define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) 1201234f0c4cSRajendra Nayak 1202234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 120356ef28acSRajendra Nayak #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 1204568997cfSRajendra Nayak #define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) 1205234f0c4cSRajendra Nayak 1206234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTCTRL */ 120756ef28acSRajendra Nayak #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 1208568997cfSRajendra Nayak #define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) 1209234f0c4cSRajendra Nayak 1210234f0c4cSRajendra Nayak /* Used by PM_IVAHD_PWRSTST */ 121156ef28acSRajendra Nayak #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 1212568997cfSRajendra Nayak #define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) 1213234f0c4cSRajendra Nayak 1214234f0c4cSRajendra Nayak /* Used by RM_TESLA_RSTST */ 121556ef28acSRajendra Nayak #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 1216568997cfSRajendra Nayak #define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) 1217234f0c4cSRajendra Nayak 1218234f0c4cSRajendra Nayak /* Used by RM_TESLA_RSTST */ 121956ef28acSRajendra Nayak #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 1220568997cfSRajendra Nayak #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) 1221234f0c4cSRajendra Nayak 1222234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 122356ef28acSRajendra Nayak #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 1224568997cfSRajendra Nayak #define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) 1225234f0c4cSRajendra Nayak 1226234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 122756ef28acSRajendra Nayak #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 1228568997cfSRajendra Nayak #define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) 1229234f0c4cSRajendra Nayak 1230234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTST */ 123156ef28acSRajendra Nayak #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 1232568997cfSRajendra Nayak #define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) 1233234f0c4cSRajendra Nayak 1234234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 123556ef28acSRajendra Nayak #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 1236568997cfSRajendra Nayak #define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) 1237234f0c4cSRajendra Nayak 1238234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 123956ef28acSRajendra Nayak #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 1240568997cfSRajendra Nayak #define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) 1241234f0c4cSRajendra Nayak 1242234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTST */ 124356ef28acSRajendra Nayak #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 1244568997cfSRajendra Nayak #define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) 1245234f0c4cSRajendra Nayak 1246234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 124756ef28acSRajendra Nayak #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 1248568997cfSRajendra Nayak #define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) 1249234f0c4cSRajendra Nayak 1250234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTCTRL */ 125156ef28acSRajendra Nayak #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 1252568997cfSRajendra Nayak #define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) 1253234f0c4cSRajendra Nayak 1254234f0c4cSRajendra Nayak /* Used by PM_TESLA_PWRSTST */ 125556ef28acSRajendra Nayak #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 1256568997cfSRajendra Nayak #define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) 1257234f0c4cSRajendra Nayak 1258234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 125956ef28acSRajendra Nayak #define OMAP4430_TIMEOUT_SHIFT 0 1260568997cfSRajendra Nayak #define OMAP4430_TIMEOUT_MASK (0xffff << 0) 1261234f0c4cSRajendra Nayak 1262234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 126356ef28acSRajendra Nayak #define OMAP4430_TIMEOUTEN_SHIFT 3 1264568997cfSRajendra Nayak #define OMAP4430_TIMEOUTEN_MASK (1 << 3) 1265234f0c4cSRajendra Nayak 1266234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 126756ef28acSRajendra Nayak #define OMAP4430_TRANSITION_EN_SHIFT 8 1268568997cfSRajendra Nayak #define OMAP4430_TRANSITION_EN_MASK (1 << 8) 1269234f0c4cSRajendra Nayak 1270234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 127156ef28acSRajendra Nayak #define OMAP4430_TRANSITION_ST_SHIFT 8 1272568997cfSRajendra Nayak #define OMAP4430_TRANSITION_ST_MASK (1 << 8) 1273234f0c4cSRajendra Nayak 1274234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_BYPASS */ 127556ef28acSRajendra Nayak #define OMAP4430_VALID_SHIFT 24 1276568997cfSRajendra Nayak #define OMAP4430_VALID_MASK (1 << 24) 1277234f0c4cSRajendra Nayak 1278234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 127956ef28acSRajendra Nayak #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 1280568997cfSRajendra Nayak #define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) 1281234f0c4cSRajendra Nayak 1282234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 128356ef28acSRajendra Nayak #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 1284568997cfSRajendra Nayak #define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) 1285568997cfSRajendra Nayak 1286568997cfSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1287568997cfSRajendra Nayak #define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 1288568997cfSRajendra Nayak #define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) 1289568997cfSRajendra Nayak 1290568997cfSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1291568997cfSRajendra Nayak #define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 1292568997cfSRajendra Nayak #define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) 1293234f0c4cSRajendra Nayak 1294234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 129556ef28acSRajendra Nayak #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 1296568997cfSRajendra Nayak #define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) 1297234f0c4cSRajendra Nayak 1298234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 129956ef28acSRajendra Nayak #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 1300568997cfSRajendra Nayak #define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) 1301234f0c4cSRajendra Nayak 1302234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 130356ef28acSRajendra Nayak #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 1304568997cfSRajendra Nayak #define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) 1305234f0c4cSRajendra Nayak 1306234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 130756ef28acSRajendra Nayak #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 1308568997cfSRajendra Nayak #define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) 1309234f0c4cSRajendra Nayak 1310234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 131156ef28acSRajendra Nayak #define OMAP4430_VC_RAERR_EN_SHIFT 12 1312568997cfSRajendra Nayak #define OMAP4430_VC_RAERR_EN_MASK (1 << 12) 1313234f0c4cSRajendra Nayak 1314234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 131556ef28acSRajendra Nayak #define OMAP4430_VC_RAERR_ST_SHIFT 12 1316568997cfSRajendra Nayak #define OMAP4430_VC_RAERR_ST_MASK (1 << 12) 1317234f0c4cSRajendra Nayak 1318234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 131956ef28acSRajendra Nayak #define OMAP4430_VC_SAERR_EN_SHIFT 11 1320568997cfSRajendra Nayak #define OMAP4430_VC_SAERR_EN_MASK (1 << 11) 1321234f0c4cSRajendra Nayak 1322234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 132356ef28acSRajendra Nayak #define OMAP4430_VC_SAERR_ST_SHIFT 11 1324568997cfSRajendra Nayak #define OMAP4430_VC_SAERR_ST_MASK (1 << 11) 1325234f0c4cSRajendra Nayak 1326234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 132756ef28acSRajendra Nayak #define OMAP4430_VC_TOERR_EN_SHIFT 13 1328568997cfSRajendra Nayak #define OMAP4430_VC_TOERR_EN_MASK (1 << 13) 1329234f0c4cSRajendra Nayak 1330234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 133156ef28acSRajendra Nayak #define OMAP4430_VC_TOERR_ST_SHIFT 13 1332568997cfSRajendra Nayak #define OMAP4430_VC_TOERR_ST_MASK (1 << 13) 1333234f0c4cSRajendra Nayak 1334234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 133556ef28acSRajendra Nayak #define OMAP4430_VDDMAX_SHIFT 24 1336568997cfSRajendra Nayak #define OMAP4430_VDDMAX_MASK (0xff << 24) 1337234f0c4cSRajendra Nayak 1338234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 133956ef28acSRajendra Nayak #define OMAP4430_VDDMIN_SHIFT 16 1340568997cfSRajendra Nayak #define OMAP4430_VDDMIN_MASK (0xff << 16) 1341234f0c4cSRajendra Nayak 1342234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 134356ef28acSRajendra Nayak #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 1344568997cfSRajendra Nayak #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) 1345234f0c4cSRajendra Nayak 1346234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 134756ef28acSRajendra Nayak #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 1348568997cfSRajendra Nayak #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) 1349234f0c4cSRajendra Nayak 1350234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 135156ef28acSRajendra Nayak #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 1352568997cfSRajendra Nayak #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) 1353234f0c4cSRajendra Nayak 1354234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 135556ef28acSRajendra Nayak #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 1356568997cfSRajendra Nayak #define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) 1357234f0c4cSRajendra Nayak 1358234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 135956ef28acSRajendra Nayak #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 1360568997cfSRajendra Nayak #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) 1361234f0c4cSRajendra Nayak 1362234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 136356ef28acSRajendra Nayak #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 1364568997cfSRajendra Nayak #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) 1365234f0c4cSRajendra Nayak 1366234f0c4cSRajendra Nayak /* Used by PRM_VOLTCTRL */ 136756ef28acSRajendra Nayak #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 1368568997cfSRajendra Nayak #define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) 1369234f0c4cSRajendra Nayak 1370234f0c4cSRajendra Nayak /* Used by PRM_RSTST */ 137156ef28acSRajendra Nayak #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 1372568997cfSRajendra Nayak #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) 1373568997cfSRajendra Nayak 1374568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1375568997cfSRajendra Nayak #define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 1376568997cfSRajendra Nayak #define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) 1377568997cfSRajendra Nayak 1378568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1379568997cfSRajendra Nayak #define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 1380568997cfSRajendra Nayak #define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) 1381568997cfSRajendra Nayak 1382568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1383568997cfSRajendra Nayak #define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 1384568997cfSRajendra Nayak #define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) 1385568997cfSRajendra Nayak 1386568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1387568997cfSRajendra Nayak #define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 1388568997cfSRajendra Nayak #define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) 1389568997cfSRajendra Nayak 1390568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1391568997cfSRajendra Nayak #define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 1392568997cfSRajendra Nayak #define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) 1393568997cfSRajendra Nayak 1394568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1395568997cfSRajendra Nayak #define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 1396568997cfSRajendra Nayak #define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) 1397568997cfSRajendra Nayak 1398568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1399568997cfSRajendra Nayak #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 1400568997cfSRajendra Nayak #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) 1401568997cfSRajendra Nayak 1402568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1403568997cfSRajendra Nayak #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 1404568997cfSRajendra Nayak #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) 1405568997cfSRajendra Nayak 1406568997cfSRajendra Nayak /* Used by PRM_VC_ERRST */ 1407568997cfSRajendra Nayak #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 1408568997cfSRajendra Nayak #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) 1409234f0c4cSRajendra Nayak 1410234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_VOL */ 141156ef28acSRajendra Nayak #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 1412568997cfSRajendra Nayak #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) 1413234f0c4cSRajendra Nayak 1414234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_VOL */ 141556ef28acSRajendra Nayak #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 1416568997cfSRajendra Nayak #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) 1417234f0c4cSRajendra Nayak 1418234f0c4cSRajendra Nayak /* Used by PRM_VC_VAL_SMPS_RA_VOL */ 141956ef28acSRajendra Nayak #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 1420568997cfSRajendra Nayak #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) 1421234f0c4cSRajendra Nayak 1422234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 142356ef28acSRajendra Nayak #define OMAP4430_VPENABLE_SHIFT 0 1424568997cfSRajendra Nayak #define OMAP4430_VPENABLE_MASK (1 << 0) 1425234f0c4cSRajendra Nayak 1426234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ 142756ef28acSRajendra Nayak #define OMAP4430_VPINIDLE_SHIFT 0 1428568997cfSRajendra Nayak #define OMAP4430_VPINIDLE_MASK (1 << 0) 1429234f0c4cSRajendra Nayak 1430234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ 143156ef28acSRajendra Nayak #define OMAP4430_VPVOLTAGE_SHIFT 0 1432568997cfSRajendra Nayak #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) 1433234f0c4cSRajendra Nayak 1434234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 143556ef28acSRajendra Nayak #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 1436568997cfSRajendra Nayak #define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) 1437234f0c4cSRajendra Nayak 1438234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 143956ef28acSRajendra Nayak #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 1440568997cfSRajendra Nayak #define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) 1441234f0c4cSRajendra Nayak 1442234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 144356ef28acSRajendra Nayak #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 1444568997cfSRajendra Nayak #define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) 1445234f0c4cSRajendra Nayak 1446234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 144756ef28acSRajendra Nayak #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 1448568997cfSRajendra Nayak #define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) 1449234f0c4cSRajendra Nayak 1450234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 145156ef28acSRajendra Nayak #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 1452568997cfSRajendra Nayak #define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) 1453234f0c4cSRajendra Nayak 1454234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 145556ef28acSRajendra Nayak #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 1456568997cfSRajendra Nayak #define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) 1457234f0c4cSRajendra Nayak 1458234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 145956ef28acSRajendra Nayak #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 1460568997cfSRajendra Nayak #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) 1461234f0c4cSRajendra Nayak 1462234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 146356ef28acSRajendra Nayak #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 1464568997cfSRajendra Nayak #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) 1465234f0c4cSRajendra Nayak 1466234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 146756ef28acSRajendra Nayak #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 1468568997cfSRajendra Nayak #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) 1469234f0c4cSRajendra Nayak 1470234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 147156ef28acSRajendra Nayak #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 1472568997cfSRajendra Nayak #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) 1473234f0c4cSRajendra Nayak 1474234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 147556ef28acSRajendra Nayak #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 1476568997cfSRajendra Nayak #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) 1477234f0c4cSRajendra Nayak 1478234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 147956ef28acSRajendra Nayak #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 1480568997cfSRajendra Nayak #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) 1481234f0c4cSRajendra Nayak 1482234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 148356ef28acSRajendra Nayak #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 1484568997cfSRajendra Nayak #define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) 1485234f0c4cSRajendra Nayak 1486234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 148756ef28acSRajendra Nayak #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 1488568997cfSRajendra Nayak #define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) 1489234f0c4cSRajendra Nayak 1490234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 149156ef28acSRajendra Nayak #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 1492568997cfSRajendra Nayak #define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) 1493234f0c4cSRajendra Nayak 1494234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 149556ef28acSRajendra Nayak #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 1496568997cfSRajendra Nayak #define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) 1497234f0c4cSRajendra Nayak 1498234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 149956ef28acSRajendra Nayak #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 1500568997cfSRajendra Nayak #define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) 1501234f0c4cSRajendra Nayak 1502234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 150356ef28acSRajendra Nayak #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 1504568997cfSRajendra Nayak #define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) 1505234f0c4cSRajendra Nayak 1506234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 150756ef28acSRajendra Nayak #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 1508568997cfSRajendra Nayak #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) 1509234f0c4cSRajendra Nayak 1510234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 151156ef28acSRajendra Nayak #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 1512568997cfSRajendra Nayak #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) 1513234f0c4cSRajendra Nayak 1514234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 151556ef28acSRajendra Nayak #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 1516568997cfSRajendra Nayak #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) 1517234f0c4cSRajendra Nayak 1518234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 151956ef28acSRajendra Nayak #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 1520568997cfSRajendra Nayak #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) 1521234f0c4cSRajendra Nayak 1522234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 152356ef28acSRajendra Nayak #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 1524568997cfSRajendra Nayak #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) 1525234f0c4cSRajendra Nayak 1526234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 152756ef28acSRajendra Nayak #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 1528568997cfSRajendra Nayak #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) 1529234f0c4cSRajendra Nayak 1530234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 153156ef28acSRajendra Nayak #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 1532568997cfSRajendra Nayak #define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) 1533234f0c4cSRajendra Nayak 1534234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 153556ef28acSRajendra Nayak #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 1536568997cfSRajendra Nayak #define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) 1537234f0c4cSRajendra Nayak 1538234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 153956ef28acSRajendra Nayak #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 1540568997cfSRajendra Nayak #define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) 1541234f0c4cSRajendra Nayak 1542234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 154356ef28acSRajendra Nayak #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 1544568997cfSRajendra Nayak #define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) 1545234f0c4cSRajendra Nayak 1546234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 154756ef28acSRajendra Nayak #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 1548568997cfSRajendra Nayak #define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) 1549234f0c4cSRajendra Nayak 1550234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 155156ef28acSRajendra Nayak #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 1552568997cfSRajendra Nayak #define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) 1553234f0c4cSRajendra Nayak 1554234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 155556ef28acSRajendra Nayak #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 1556568997cfSRajendra Nayak #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) 1557234f0c4cSRajendra Nayak 1558234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 155956ef28acSRajendra Nayak #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 1560568997cfSRajendra Nayak #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) 1561234f0c4cSRajendra Nayak 1562234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 156356ef28acSRajendra Nayak #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 1564568997cfSRajendra Nayak #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) 1565234f0c4cSRajendra Nayak 1566234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 156756ef28acSRajendra Nayak #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 1568568997cfSRajendra Nayak #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) 1569234f0c4cSRajendra Nayak 1570234f0c4cSRajendra Nayak /* Used by PRM_IRQENABLE_MPU_2 */ 157156ef28acSRajendra Nayak #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 1572568997cfSRajendra Nayak #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) 1573234f0c4cSRajendra Nayak 1574234f0c4cSRajendra Nayak /* Used by PRM_IRQSTATUS_MPU_2 */ 157556ef28acSRajendra Nayak #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 1576568997cfSRajendra Nayak #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) 1577234f0c4cSRajendra Nayak 1578234f0c4cSRajendra Nayak /* Used by PRM_SRAM_COUNT */ 157956ef28acSRajendra Nayak #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 1580568997cfSRajendra Nayak #define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) 1581234f0c4cSRajendra Nayak 1582234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ 158356ef28acSRajendra Nayak #define OMAP4430_VSTEPMAX_SHIFT 0 1584568997cfSRajendra Nayak #define OMAP4430_VSTEPMAX_MASK (0xff << 0) 1585234f0c4cSRajendra Nayak 1586234f0c4cSRajendra Nayak /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ 158756ef28acSRajendra Nayak #define OMAP4430_VSTEPMIN_SHIFT 0 1588568997cfSRajendra Nayak #define OMAP4430_VSTEPMIN_MASK (0xff << 0) 1589234f0c4cSRajendra Nayak 1590234f0c4cSRajendra Nayak /* Used by PRM_MODEM_IF_CTRL */ 159156ef28acSRajendra Nayak #define OMAP4430_WAKE_MODEM_SHIFT 0 1592568997cfSRajendra Nayak #define OMAP4430_WAKE_MODEM_MASK (1 << 0) 1593234f0c4cSRajendra Nayak 1594234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 159556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 1596568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) 1597234f0c4cSRajendra Nayak 1598234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 159956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 1600568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) 1601234f0c4cSRajendra Nayak 1602234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 160356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 1604568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) 1605234f0c4cSRajendra Nayak 1606234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 160756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 1608568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) 1609234f0c4cSRajendra Nayak 1610234f0c4cSRajendra Nayak /* Used by PM_ABE_DMIC_WKDEP */ 161156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 1612568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) 1613234f0c4cSRajendra Nayak 1614234f0c4cSRajendra Nayak /* Used by PM_ABE_DMIC_WKDEP */ 161556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 1616568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) 1617234f0c4cSRajendra Nayak 1618234f0c4cSRajendra Nayak /* Used by PM_ABE_DMIC_WKDEP */ 161956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 1620568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) 1621234f0c4cSRajendra Nayak 1622234f0c4cSRajendra Nayak /* Used by PM_ABE_DMIC_WKDEP */ 162356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 1624568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) 1625234f0c4cSRajendra Nayak 1626234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER10_WKDEP */ 162756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 1628568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) 1629234f0c4cSRajendra Nayak 1630234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER11_WKDEP */ 163156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 1632568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) 1633234f0c4cSRajendra Nayak 1634234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER11_WKDEP */ 163556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 1636568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) 1637234f0c4cSRajendra Nayak 1638234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER2_WKDEP */ 163956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 1640568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) 1641234f0c4cSRajendra Nayak 1642234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER3_WKDEP */ 164356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 1644568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) 1645234f0c4cSRajendra Nayak 1646234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER3_WKDEP */ 164756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 1648568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) 1649234f0c4cSRajendra Nayak 1650234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER4_WKDEP */ 165156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 1652568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) 1653234f0c4cSRajendra Nayak 1654234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER4_WKDEP */ 165556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 1656568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) 1657234f0c4cSRajendra Nayak 1658234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER9_WKDEP */ 165956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 1660568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) 1661234f0c4cSRajendra Nayak 1662234f0c4cSRajendra Nayak /* Used by PM_L4PER_DMTIMER9_WKDEP */ 166356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 1664568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) 1665234f0c4cSRajendra Nayak 1666234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 166756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 1668568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) 1669234f0c4cSRajendra Nayak 1670234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 167156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 1672568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) 1673234f0c4cSRajendra Nayak 1674234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 167556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 1676568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) 1677234f0c4cSRajendra Nayak 1678234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 167956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 1680568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) 1681234f0c4cSRajendra Nayak 1682234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 168356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 1684568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) 1685234f0c4cSRajendra Nayak 1686234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 168756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 1688568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) 1689234f0c4cSRajendra Nayak 1690234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 169156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 1692568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) 1693234f0c4cSRajendra Nayak 1694234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 169556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 1696568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) 1697234f0c4cSRajendra Nayak 1698234f0c4cSRajendra Nayak /* Used by PM_WKUP_GPIO1_WKDEP */ 169956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 1700568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) 1701234f0c4cSRajendra Nayak 1702234f0c4cSRajendra Nayak /* Used by PM_WKUP_GPIO1_WKDEP */ 170356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 1704568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) 1705234f0c4cSRajendra Nayak 1706234f0c4cSRajendra Nayak /* Used by PM_WKUP_GPIO1_WKDEP */ 170756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 1708568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) 1709234f0c4cSRajendra Nayak 1710234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO2_WKDEP */ 171156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 1712568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) 1713234f0c4cSRajendra Nayak 1714234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO2_WKDEP */ 171556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 1716568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) 1717234f0c4cSRajendra Nayak 1718234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO2_WKDEP */ 171956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 1720568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) 1721234f0c4cSRajendra Nayak 1722234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO3_WKDEP */ 172356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 1724568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) 1725234f0c4cSRajendra Nayak 1726234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO3_WKDEP */ 172756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 1728568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) 1729234f0c4cSRajendra Nayak 1730234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO4_WKDEP */ 173156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 1732568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) 1733234f0c4cSRajendra Nayak 1734234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO4_WKDEP */ 173556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 1736568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) 1737234f0c4cSRajendra Nayak 1738234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO5_WKDEP */ 173956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 1740568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) 1741234f0c4cSRajendra Nayak 1742234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO5_WKDEP */ 174356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 1744568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) 1745234f0c4cSRajendra Nayak 1746234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO6_WKDEP */ 174756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 1748568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) 1749234f0c4cSRajendra Nayak 1750234f0c4cSRajendra Nayak /* Used by PM_L4PER_GPIO6_WKDEP */ 175156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 1752568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) 1753234f0c4cSRajendra Nayak 1754234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 175556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 1756568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) 1757234f0c4cSRajendra Nayak 1758234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 175956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 1760568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) 1761234f0c4cSRajendra Nayak 1762234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 176356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 1764568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) 1765234f0c4cSRajendra Nayak 1766234f0c4cSRajendra Nayak /* Used by PM_DSS_DSS_WKDEP */ 176756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 1768568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) 1769234f0c4cSRajendra Nayak 1770234f0c4cSRajendra Nayak /* Used by PM_L4PER_HECC1_WKDEP */ 177156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 1772568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) 1773234f0c4cSRajendra Nayak 1774234f0c4cSRajendra Nayak /* Used by PM_L4PER_HECC2_WKDEP */ 177556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 1776568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) 1777234f0c4cSRajendra Nayak 1778234f0c4cSRajendra Nayak /* Used by PM_L3INIT_HSI_WKDEP */ 177956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 1780568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) 1781234f0c4cSRajendra Nayak 1782234f0c4cSRajendra Nayak /* Used by PM_L3INIT_HSI_WKDEP */ 178356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 1784568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) 1785234f0c4cSRajendra Nayak 1786234f0c4cSRajendra Nayak /* Used by PM_L3INIT_HSI_WKDEP */ 178756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 1788568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) 1789234f0c4cSRajendra Nayak 1790234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C1_WKDEP */ 179156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 1792568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) 1793234f0c4cSRajendra Nayak 1794234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C1_WKDEP */ 179556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 1796568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) 1797234f0c4cSRajendra Nayak 1798234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C1_WKDEP */ 179956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 1800568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) 1801234f0c4cSRajendra Nayak 1802234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C2_WKDEP */ 180356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 1804568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) 1805234f0c4cSRajendra Nayak 1806234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C2_WKDEP */ 180756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 1808568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) 1809234f0c4cSRajendra Nayak 1810234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C2_WKDEP */ 181156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 1812568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) 1813234f0c4cSRajendra Nayak 1814234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C3_WKDEP */ 181556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 1816568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) 1817234f0c4cSRajendra Nayak 1818234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C3_WKDEP */ 181956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 1820568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) 1821234f0c4cSRajendra Nayak 1822234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C3_WKDEP */ 182356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 1824568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) 1825234f0c4cSRajendra Nayak 1826234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C4_WKDEP */ 182756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 1828568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) 1829234f0c4cSRajendra Nayak 1830234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C4_WKDEP */ 183156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 1832568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) 1833234f0c4cSRajendra Nayak 1834234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C4_WKDEP */ 183556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 1836568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) 1837234f0c4cSRajendra Nayak 1838234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C5_WKDEP */ 183956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 1840568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) 1841234f0c4cSRajendra Nayak 1842234f0c4cSRajendra Nayak /* Used by PM_L4PER_I2C5_WKDEP */ 184356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 1844568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) 1845234f0c4cSRajendra Nayak 1846234f0c4cSRajendra Nayak /* Used by PM_WKUP_KEYBOARD_WKDEP */ 184756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 1848568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) 1849234f0c4cSRajendra Nayak 1850234f0c4cSRajendra Nayak /* Used by PM_ABE_MCASP_WKDEP */ 185156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 1852568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) 1853234f0c4cSRajendra Nayak 1854234f0c4cSRajendra Nayak /* Used by PM_ABE_MCASP_WKDEP */ 185556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 1856568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) 1857234f0c4cSRajendra Nayak 1858234f0c4cSRajendra Nayak /* Used by PM_ABE_MCASP_WKDEP */ 185956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 1860568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) 1861234f0c4cSRajendra Nayak 1862234f0c4cSRajendra Nayak /* Used by PM_ABE_MCASP_WKDEP */ 186356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 1864568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) 1865234f0c4cSRajendra Nayak 1866234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP2_WKDEP */ 186756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 1868568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) 1869234f0c4cSRajendra Nayak 1870234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP2_WKDEP */ 187156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 1872568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) 1873234f0c4cSRajendra Nayak 1874234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP2_WKDEP */ 187556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 1876568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) 1877234f0c4cSRajendra Nayak 1878234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP2_WKDEP */ 187956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 1880568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) 1881234f0c4cSRajendra Nayak 1882234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP3_WKDEP */ 188356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 1884568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) 1885234f0c4cSRajendra Nayak 1886234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP3_WKDEP */ 188756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 1888568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) 1889234f0c4cSRajendra Nayak 1890234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP3_WKDEP */ 189156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 1892568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) 1893234f0c4cSRajendra Nayak 1894234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCASP3_WKDEP */ 189556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 1896568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) 1897234f0c4cSRajendra Nayak 1898234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP1_WKDEP */ 189956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 1900568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) 1901234f0c4cSRajendra Nayak 1902234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP1_WKDEP */ 190356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 1904568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) 1905234f0c4cSRajendra Nayak 1906234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP1_WKDEP */ 190756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 1908568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) 1909234f0c4cSRajendra Nayak 1910234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP2_WKDEP */ 191156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 1912568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) 1913234f0c4cSRajendra Nayak 1914234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP2_WKDEP */ 191556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 1916568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) 1917234f0c4cSRajendra Nayak 1918234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP2_WKDEP */ 191956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 1920568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) 1921234f0c4cSRajendra Nayak 1922234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP3_WKDEP */ 192356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 1924568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) 1925234f0c4cSRajendra Nayak 1926234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP3_WKDEP */ 192756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 1928568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) 1929234f0c4cSRajendra Nayak 1930234f0c4cSRajendra Nayak /* Used by PM_ABE_MCBSP3_WKDEP */ 193156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 1932568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) 1933234f0c4cSRajendra Nayak 1934234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCBSP4_WKDEP */ 193556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 1936568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) 1937234f0c4cSRajendra Nayak 1938234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCBSP4_WKDEP */ 193956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 1940568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) 1941234f0c4cSRajendra Nayak 1942234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCBSP4_WKDEP */ 194356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 1944568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) 1945234f0c4cSRajendra Nayak 1946234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI1_WKDEP */ 194756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 1948568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) 1949234f0c4cSRajendra Nayak 1950234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI1_WKDEP */ 195156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 1952568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) 1953234f0c4cSRajendra Nayak 1954234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI1_WKDEP */ 195556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 1956568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) 1957234f0c4cSRajendra Nayak 1958234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI1_WKDEP */ 195956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 1960568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) 1961234f0c4cSRajendra Nayak 1962234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI2_WKDEP */ 196356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 1964568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) 1965234f0c4cSRajendra Nayak 1966234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI2_WKDEP */ 196756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 1968568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) 1969234f0c4cSRajendra Nayak 1970234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI2_WKDEP */ 197156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 1972568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) 1973234f0c4cSRajendra Nayak 1974234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI3_WKDEP */ 197556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 1976568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) 1977234f0c4cSRajendra Nayak 1978234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI3_WKDEP */ 197956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 1980568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) 1981234f0c4cSRajendra Nayak 1982234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI4_WKDEP */ 198356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 1984568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) 1985234f0c4cSRajendra Nayak 1986234f0c4cSRajendra Nayak /* Used by PM_L4PER_MCSPI4_WKDEP */ 198756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 1988568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) 1989234f0c4cSRajendra Nayak 1990234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC1_WKDEP */ 199156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 1992568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) 1993234f0c4cSRajendra Nayak 1994234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC1_WKDEP */ 199556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 1996568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) 1997234f0c4cSRajendra Nayak 1998234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC1_WKDEP */ 199956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 2000568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) 2001234f0c4cSRajendra Nayak 2002234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC1_WKDEP */ 200356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 2004568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) 2005234f0c4cSRajendra Nayak 2006234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC2_WKDEP */ 200756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 2008568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) 2009234f0c4cSRajendra Nayak 2010234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC2_WKDEP */ 201156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 2012568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) 2013234f0c4cSRajendra Nayak 2014234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC2_WKDEP */ 201556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 2016568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) 2017234f0c4cSRajendra Nayak 2018234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC2_WKDEP */ 201956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 2020568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) 2021234f0c4cSRajendra Nayak 2022234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC6_WKDEP */ 202356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 2024568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) 2025234f0c4cSRajendra Nayak 2026234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC6_WKDEP */ 202756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 2028568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) 2029234f0c4cSRajendra Nayak 2030234f0c4cSRajendra Nayak /* Used by PM_L3INIT_MMC6_WKDEP */ 203156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 2032568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) 2033234f0c4cSRajendra Nayak 2034234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD3_WKDEP */ 203556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 2036568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) 2037234f0c4cSRajendra Nayak 2038234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD3_WKDEP */ 203956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 2040568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) 2041234f0c4cSRajendra Nayak 2042234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD3_WKDEP */ 204356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 2044568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) 2045234f0c4cSRajendra Nayak 2046234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD4_WKDEP */ 204756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 2048568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) 2049234f0c4cSRajendra Nayak 2050234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD4_WKDEP */ 205156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 2052568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) 2053234f0c4cSRajendra Nayak 2054234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD4_WKDEP */ 205556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 2056568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) 2057234f0c4cSRajendra Nayak 2058234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD5_WKDEP */ 205956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 2060568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) 2061234f0c4cSRajendra Nayak 2062234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD5_WKDEP */ 206356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 2064568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) 2065234f0c4cSRajendra Nayak 2066234f0c4cSRajendra Nayak /* Used by PM_L4PER_MMCSD5_WKDEP */ 206756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 2068568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) 2069234f0c4cSRajendra Nayak 2070234f0c4cSRajendra Nayak /* Used by PM_L3INIT_PCIESS_WKDEP */ 207156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 2072568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) 2073234f0c4cSRajendra Nayak 2074234f0c4cSRajendra Nayak /* Used by PM_L3INIT_PCIESS_WKDEP */ 207556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 2076568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) 2077234f0c4cSRajendra Nayak 2078234f0c4cSRajendra Nayak /* Used by PM_ABE_PDM_WKDEP */ 207956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 2080568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) 2081234f0c4cSRajendra Nayak 2082234f0c4cSRajendra Nayak /* Used by PM_ABE_PDM_WKDEP */ 208356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 2084568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) 2085234f0c4cSRajendra Nayak 2086234f0c4cSRajendra Nayak /* Used by PM_ABE_PDM_WKDEP */ 208756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 2088568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) 2089234f0c4cSRajendra Nayak 2090234f0c4cSRajendra Nayak /* Used by PM_ABE_PDM_WKDEP */ 209156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 2092568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) 2093234f0c4cSRajendra Nayak 2094234f0c4cSRajendra Nayak /* Used by PM_WKUP_RTC_WKDEP */ 209556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 2096568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) 2097234f0c4cSRajendra Nayak 2098234f0c4cSRajendra Nayak /* Used by PM_L3INIT_SATA_WKDEP */ 209956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 2100568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) 2101234f0c4cSRajendra Nayak 2102234f0c4cSRajendra Nayak /* Used by PM_L3INIT_SATA_WKDEP */ 210356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 2104568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) 2105234f0c4cSRajendra Nayak 2106234f0c4cSRajendra Nayak /* Used by PM_ABE_SLIMBUS_WKDEP */ 210756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 2108568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) 2109234f0c4cSRajendra Nayak 2110234f0c4cSRajendra Nayak /* Used by PM_ABE_SLIMBUS_WKDEP */ 211156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 2112568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) 2113234f0c4cSRajendra Nayak 2114234f0c4cSRajendra Nayak /* Used by PM_ABE_SLIMBUS_WKDEP */ 211556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 2116568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) 2117234f0c4cSRajendra Nayak 2118234f0c4cSRajendra Nayak /* Used by PM_ABE_SLIMBUS_WKDEP */ 211956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 2120568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) 2121234f0c4cSRajendra Nayak 2122234f0c4cSRajendra Nayak /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 212356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 2124568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) 2125234f0c4cSRajendra Nayak 2126234f0c4cSRajendra Nayak /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 212756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 2128568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) 2129234f0c4cSRajendra Nayak 2130234f0c4cSRajendra Nayak /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 213156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 2132568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) 2133234f0c4cSRajendra Nayak 2134234f0c4cSRajendra Nayak /* Used by PM_L4PER_SLIMBUS2_WKDEP */ 213556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 2136568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) 2137234f0c4cSRajendra Nayak 2138234f0c4cSRajendra Nayak /* Used by PM_ALWON_SR_CORE_WKDEP */ 213956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 2140568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) 2141234f0c4cSRajendra Nayak 2142234f0c4cSRajendra Nayak /* Used by PM_ALWON_SR_CORE_WKDEP */ 214356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 2144568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) 2145234f0c4cSRajendra Nayak 2146234f0c4cSRajendra Nayak /* Used by PM_ALWON_SR_IVA_WKDEP */ 214756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 2148568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) 2149234f0c4cSRajendra Nayak 2150234f0c4cSRajendra Nayak /* Used by PM_ALWON_SR_IVA_WKDEP */ 215156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 2152568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) 2153234f0c4cSRajendra Nayak 2154234f0c4cSRajendra Nayak /* Used by PM_ALWON_SR_MPU_WKDEP */ 215556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 2156568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) 2157234f0c4cSRajendra Nayak 2158234f0c4cSRajendra Nayak /* Used by PM_WKUP_TIMER12_WKDEP */ 215956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 2160568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) 2161234f0c4cSRajendra Nayak 2162234f0c4cSRajendra Nayak /* Used by PM_WKUP_TIMER1_WKDEP */ 216356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 2164568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) 2165234f0c4cSRajendra Nayak 2166234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER5_WKDEP */ 216756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 2168568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) 2169234f0c4cSRajendra Nayak 2170234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER5_WKDEP */ 217156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 2172568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) 2173234f0c4cSRajendra Nayak 2174234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER6_WKDEP */ 217556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 2176568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) 2177234f0c4cSRajendra Nayak 2178234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER6_WKDEP */ 217956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 2180568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) 2181234f0c4cSRajendra Nayak 2182234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER7_WKDEP */ 218356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 2184568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) 2185234f0c4cSRajendra Nayak 2186234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER7_WKDEP */ 218756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 2188568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) 2189234f0c4cSRajendra Nayak 2190234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER8_WKDEP */ 219156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 2192568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) 2193234f0c4cSRajendra Nayak 2194234f0c4cSRajendra Nayak /* Used by PM_ABE_TIMER8_WKDEP */ 219556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 2196568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) 2197234f0c4cSRajendra Nayak 2198234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART1_WKDEP */ 219956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 2200568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) 2201234f0c4cSRajendra Nayak 2202234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART1_WKDEP */ 220356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 2204568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) 2205234f0c4cSRajendra Nayak 2206234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART2_WKDEP */ 220756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 2208568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) 2209234f0c4cSRajendra Nayak 2210234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART2_WKDEP */ 221156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 2212568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) 2213234f0c4cSRajendra Nayak 2214234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART3_WKDEP */ 221556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 2216568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) 2217234f0c4cSRajendra Nayak 2218234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART3_WKDEP */ 221956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 2220568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) 2221234f0c4cSRajendra Nayak 2222234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART3_WKDEP */ 222356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 2224568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) 2225234f0c4cSRajendra Nayak 2226234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART3_WKDEP */ 222756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 2228568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) 2229234f0c4cSRajendra Nayak 2230234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART4_WKDEP */ 223156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 2232568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) 2233234f0c4cSRajendra Nayak 2234234f0c4cSRajendra Nayak /* Used by PM_L4PER_UART4_WKDEP */ 223556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 2236568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) 2237234f0c4cSRajendra Nayak 2238234f0c4cSRajendra Nayak /* Used by PM_L3INIT_UNIPRO1_WKDEP */ 223956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 2240568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) 2241234f0c4cSRajendra Nayak 2242234f0c4cSRajendra Nayak /* Used by PM_L3INIT_UNIPRO1_WKDEP */ 224356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 2244568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) 2245234f0c4cSRajendra Nayak 2246234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_HOST_WKDEP */ 224756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 2248568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) 2249234f0c4cSRajendra Nayak 2250234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ 225156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 2252568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) 2253234f0c4cSRajendra Nayak 2254234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ 225556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 2256568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) 2257234f0c4cSRajendra Nayak 2258234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_HOST_WKDEP */ 225956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 2260568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) 2261234f0c4cSRajendra Nayak 2262234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_OTG_WKDEP */ 226356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 2264568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) 2265234f0c4cSRajendra Nayak 2266234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_OTG_WKDEP */ 226756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 2268568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) 2269234f0c4cSRajendra Nayak 2270234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_TLL_WKDEP */ 227156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 2272568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) 2273234f0c4cSRajendra Nayak 2274234f0c4cSRajendra Nayak /* Used by PM_L3INIT_USB_TLL_WKDEP */ 227556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 2276568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) 2277234f0c4cSRajendra Nayak 2278234f0c4cSRajendra Nayak /* Used by PM_WKUP_USIM_WKDEP */ 227956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 2280568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) 2281234f0c4cSRajendra Nayak 2282234f0c4cSRajendra Nayak /* Used by PM_WKUP_USIM_WKDEP */ 228356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 2284568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) 2285234f0c4cSRajendra Nayak 2286234f0c4cSRajendra Nayak /* Used by PM_WKUP_WDT2_WKDEP */ 228756ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 2288568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) 2289234f0c4cSRajendra Nayak 2290234f0c4cSRajendra Nayak /* Used by PM_WKUP_WDT2_WKDEP */ 229156ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 2292568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) 2293234f0c4cSRajendra Nayak 2294234f0c4cSRajendra Nayak /* Used by PM_ABE_WDT3_WKDEP */ 229556ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 2296568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) 2297234f0c4cSRajendra Nayak 2298234f0c4cSRajendra Nayak /* Used by PM_L3INIT_HSI_WKDEP */ 229956ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 2300568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) 2301234f0c4cSRajendra Nayak 2302234f0c4cSRajendra Nayak /* Used by PM_L3INIT_XHPI_WKDEP */ 230356ef28acSRajendra Nayak #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 2304568997cfSRajendra Nayak #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) 2305234f0c4cSRajendra Nayak 2306234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 230756ef28acSRajendra Nayak #define OMAP4430_WUCLK_CTRL_SHIFT 8 2308568997cfSRajendra Nayak #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) 2309234f0c4cSRajendra Nayak 2310234f0c4cSRajendra Nayak /* Used by PRM_IO_PMCTRL */ 231156ef28acSRajendra Nayak #define OMAP4430_WUCLK_STATUS_SHIFT 9 2312568997cfSRajendra Nayak #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) 2313568997cfSRajendra Nayak 2314568997cfSRajendra Nayak /* Used by REVISION_PRM */ 2315568997cfSRajendra Nayak #define OMAP4430_X_MAJOR_SHIFT 8 2316568997cfSRajendra Nayak #define OMAP4430_X_MAJOR_MASK (0x7 << 8) 2317568997cfSRajendra Nayak 2318568997cfSRajendra Nayak /* Used by REVISION_PRM */ 2319568997cfSRajendra Nayak #define OMAP4430_Y_MINOR_SHIFT 0 2320568997cfSRajendra Nayak #define OMAP4430_Y_MINOR_MASK (0x3f << 0) 2321234f0c4cSRajendra Nayak #endif 2322