1 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
2 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
3 
4 /*
5  * OMAP3430 Power/Reset Management register bits
6  *
7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
8  * Copyright (C) 2007-2008 Nokia Corporation
9  *
10  * Written by Paul Walmsley
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  */
16 
17 #include "prm.h"
18 
19 /* Shared register bits */
20 
21 /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
22 #define OMAP3430_ON_SHIFT				24
23 #define OMAP3430_ON_MASK				(0xff << 24)
24 #define OMAP3430_ONLP_SHIFT				16
25 #define OMAP3430_ONLP_MASK				(0xff << 16)
26 #define OMAP3430_RET_SHIFT				8
27 #define OMAP3430_RET_MASK				(0xff << 8)
28 #define OMAP3430_OFF_SHIFT				0
29 #define OMAP3430_OFF_MASK				(0xff << 0)
30 
31 /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
32 #define OMAP3430_ERROROFFSET_SHIFT			24
33 #define OMAP3430_ERROROFFSET_MASK			(0xff << 24)
34 #define OMAP3430_ERRORGAIN_SHIFT			16
35 #define OMAP3430_ERRORGAIN_MASK				(0xff << 16)
36 #define OMAP3430_INITVOLTAGE_SHIFT			8
37 #define OMAP3430_INITVOLTAGE_MASK			(0xff << 8)
38 #define OMAP3430_TIMEOUTEN				(1 << 3)
39 #define OMAP3430_INITVDD				(1 << 2)
40 #define OMAP3430_FORCEUPDATE				(1 << 1)
41 #define OMAP3430_VPENABLE				(1 << 0)
42 
43 /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
44 #define OMAP3430_SMPSWAITTIMEMIN_SHIFT			8
45 #define OMAP3430_SMPSWAITTIMEMIN_MASK			(0xffff << 8)
46 #define OMAP3430_VSTEPMIN_SHIFT				0
47 #define OMAP3430_VSTEPMIN_MASK				(0xff << 0)
48 
49 /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
50 #define OMAP3430_SMPSWAITTIMEMAX_SHIFT			8
51 #define OMAP3430_SMPSWAITTIMEMAX_MASK			(0xffff << 8)
52 #define OMAP3430_VSTEPMAX_SHIFT				0
53 #define OMAP3430_VSTEPMAX_MASK				(0xff << 0)
54 
55 /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
56 #define OMAP3430_VDDMAX_SHIFT				24
57 #define OMAP3430_VDDMAX_MASK				(0xff << 24)
58 #define OMAP3430_VDDMIN_SHIFT				16
59 #define OMAP3430_VDDMIN_MASK				(0xff << 16)
60 #define OMAP3430_TIMEOUT_SHIFT				0
61 #define OMAP3430_TIMEOUT_MASK				(0xffff << 0)
62 
63 /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
64 #define OMAP3430_VPVOLTAGE_SHIFT			0
65 #define OMAP3430_VPVOLTAGE_MASK				(0xff << 0)
66 
67 /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
68 #define OMAP3430_VPINIDLE				(1 << 0)
69 
70 /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
71 #define OMAP3430_EN_PER_SHIFT				7
72 #define OMAP3430_EN_PER_MASK				(1 << 7)
73 
74 /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
75 #define OMAP3430_MEMORYCHANGE				(1 << 3)
76 
77 /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
78 #define OMAP3430_LOGICSTATEST				(1 << 2)
79 
80 /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
81 #define OMAP3430_LASTLOGICSTATEENTERED			(1 << 2)
82 
83 /*
84  * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
85  * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
86  * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
87  */
88 #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT			0
89 #define OMAP3430_LASTPOWERSTATEENTERED_MASK			(0x3 << 0)
90 
91 /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
92 #define OMAP3430_WKUP_ST				(1 << 0)
93 
94 /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
95 #define OMAP3430_WKUP_EN					(1 << 0)
96 
97 /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
98 #define OMAP3430_GRPSEL_MMC2				(1 << 25)
99 #define OMAP3430_GRPSEL_MMC1				(1 << 24)
100 #define OMAP3430_GRPSEL_MCSPI4				(1 << 21)
101 #define OMAP3430_GRPSEL_MCSPI3				(1 << 20)
102 #define OMAP3430_GRPSEL_MCSPI2				(1 << 19)
103 #define OMAP3430_GRPSEL_MCSPI1				(1 << 18)
104 #define OMAP3430_GRPSEL_I2C3				(1 << 17)
105 #define OMAP3430_GRPSEL_I2C2				(1 << 16)
106 #define OMAP3430_GRPSEL_I2C1				(1 << 15)
107 #define OMAP3430_GRPSEL_UART2				(1 << 14)
108 #define OMAP3430_GRPSEL_UART1				(1 << 13)
109 #define OMAP3430_GRPSEL_GPT11				(1 << 12)
110 #define OMAP3430_GRPSEL_GPT10				(1 << 11)
111 #define OMAP3430_GRPSEL_MCBSP5				(1 << 10)
112 #define OMAP3430_GRPSEL_MCBSP1				(1 << 9)
113 #define OMAP3430_GRPSEL_HSOTGUSB			(1 << 4)
114 #define OMAP3430_GRPSEL_D2D				(1 << 3)
115 
116 /*
117  * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
118  * PM_PWSTCTRL_PER shared bits
119  */
120 #define OMAP3430_MEMONSTATE_SHIFT			16
121 #define OMAP3430_MEMONSTATE_MASK			(0x3 << 16)
122 #define OMAP3430_MEMRETSTATE				(1 << 8)
123 
124 /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
125 #define OMAP3430_GRPSEL_GPIO6				(1 << 17)
126 #define OMAP3430_GRPSEL_GPIO5				(1 << 16)
127 #define OMAP3430_GRPSEL_GPIO4				(1 << 15)
128 #define OMAP3430_GRPSEL_GPIO3				(1 << 14)
129 #define OMAP3430_GRPSEL_GPIO2				(1 << 13)
130 #define OMAP3430_GRPSEL_UART3				(1 << 11)
131 #define OMAP3430_GRPSEL_GPT9				(1 << 10)
132 #define OMAP3430_GRPSEL_GPT8				(1 << 9)
133 #define OMAP3430_GRPSEL_GPT7				(1 << 8)
134 #define OMAP3430_GRPSEL_GPT6				(1 << 7)
135 #define OMAP3430_GRPSEL_GPT5				(1 << 6)
136 #define OMAP3430_GRPSEL_GPT4				(1 << 5)
137 #define OMAP3430_GRPSEL_GPT3				(1 << 4)
138 #define OMAP3430_GRPSEL_GPT2				(1 << 3)
139 #define OMAP3430_GRPSEL_MCBSP4				(1 << 2)
140 #define OMAP3430_GRPSEL_MCBSP3				(1 << 1)
141 #define OMAP3430_GRPSEL_MCBSP2				(1 << 0)
142 
143 /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
144 #define OMAP3430_GRPSEL_IO				(1 << 8)
145 #define OMAP3430_GRPSEL_SR2				(1 << 7)
146 #define OMAP3430_GRPSEL_SR1				(1 << 6)
147 #define OMAP3430_GRPSEL_GPIO1				(1 << 3)
148 #define OMAP3430_GRPSEL_GPT12				(1 << 1)
149 #define OMAP3430_GRPSEL_GPT1				(1 << 0)
150 
151 /* Bits specific to each register */
152 
153 /* RM_RSTCTRL_IVA2 */
154 #define OMAP3430_RST3_IVA2				(1 << 2)
155 #define OMAP3430_RST2_IVA2				(1 << 1)
156 #define OMAP3430_RST1_IVA2				(1 << 0)
157 
158 /* RM_RSTST_IVA2 specific bits */
159 #define OMAP3430_EMULATION_VSEQ_RST			(1 << 13)
160 #define OMAP3430_EMULATION_VHWA_RST			(1 << 12)
161 #define OMAP3430_EMULATION_IVA2_RST			(1 << 11)
162 #define OMAP3430_IVA2_SW_RST3				(1 << 10)
163 #define OMAP3430_IVA2_SW_RST2				(1 << 9)
164 #define OMAP3430_IVA2_SW_RST1				(1 << 8)
165 
166 /* PM_WKDEP_IVA2 specific bits */
167 
168 /* PM_PWSTCTRL_IVA2 specific bits */
169 #define OMAP3430_L2FLATMEMONSTATE_SHIFT			22
170 #define OMAP3430_L2FLATMEMONSTATE_MASK			(0x3 << 22)
171 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT		20
172 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK		(0x3 << 20)
173 #define OMAP3430_L1FLATMEMONSTATE_SHIFT			18
174 #define OMAP3430_L1FLATMEMONSTATE_MASK			(0x3 << 18)
175 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT		16
176 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK		(0x3 << 16)
177 #define OMAP3430_L2FLATMEMRETSTATE			(1 << 11)
178 #define OMAP3430_SHAREDL2CACHEFLATRETSTATE		(1 << 10)
179 #define OMAP3430_L1FLATMEMRETSTATE			(1 << 9)
180 #define OMAP3430_SHAREDL1CACHEFLATRETSTATE		(1 << 8)
181 
182 /* PM_PWSTST_IVA2 specific bits */
183 #define OMAP3430_L2FLATMEMSTATEST_SHIFT			10
184 #define OMAP3430_L2FLATMEMSTATEST_MASK			(0x3 << 10)
185 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT		8
186 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK		(0x3 << 8)
187 #define OMAP3430_L1FLATMEMSTATEST_SHIFT			6
188 #define OMAP3430_L1FLATMEMSTATEST_MASK			(0x3 << 6)
189 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT		4
190 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK		(0x3 << 4)
191 
192 /* PM_PREPWSTST_IVA2 specific bits */
193 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT		10
194 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK			(0x3 << 10)
195 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT	8
196 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK		(0x3 << 8)
197 #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT		6
198 #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK			(0x3 << 6)
199 #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT	4
200 #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK		(0x3 << 4)
201 
202 /* PRM_IRQSTATUS_IVA2 specific bits */
203 #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST	(1 << 2)
204 #define OMAP3430_FORCEWKUP_ST				(1 << 1)
205 
206 /* PRM_IRQENABLE_IVA2 specific bits */
207 #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN		(1 << 2)
208 #define OMAP3430_FORCEWKUP_EN					(1 << 1)
209 
210 /* PRM_REVISION specific bits */
211 
212 /* PRM_SYSCONFIG specific bits */
213 
214 /* PRM_IRQSTATUS_MPU specific bits */
215 #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT		25
216 #define OMAP3430ES2_SND_PERIPH_DPLL_ST			(1 << 25)
217 #define OMAP3430_VC_TIMEOUTERR_ST			(1 << 24)
218 #define OMAP3430_VC_RAERR_ST				(1 << 23)
219 #define OMAP3430_VC_SAERR_ST				(1 << 22)
220 #define OMAP3430_VP2_TRANXDONE_ST			(1 << 21)
221 #define OMAP3430_VP2_EQVALUE_ST				(1 << 20)
222 #define OMAP3430_VP2_NOSMPSACK_ST			(1 << 19)
223 #define OMAP3430_VP2_MAXVDD_ST				(1 << 18)
224 #define OMAP3430_VP2_MINVDD_ST				(1 << 17)
225 #define OMAP3430_VP2_OPPCHANGEDONE_ST			(1 << 16)
226 #define OMAP3430_VP1_TRANXDONE_ST			(1 << 15)
227 #define OMAP3430_VP1_EQVALUE_ST				(1 << 14)
228 #define OMAP3430_VP1_NOSMPSACK_ST			(1 << 13)
229 #define OMAP3430_VP1_MAXVDD_ST				(1 << 12)
230 #define OMAP3430_VP1_MINVDD_ST				(1 << 11)
231 #define OMAP3430_VP1_OPPCHANGEDONE_ST			(1 << 10)
232 #define OMAP3430_IO_ST					(1 << 9)
233 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST		(1 << 8)
234 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT	8
235 #define OMAP3430_MPU_DPLL_ST				(1 << 7)
236 #define OMAP3430_MPU_DPLL_ST_SHIFT			7
237 #define OMAP3430_PERIPH_DPLL_ST				(1 << 6)
238 #define OMAP3430_PERIPH_DPLL_ST_SHIFT			6
239 #define OMAP3430_CORE_DPLL_ST				(1 << 5)
240 #define OMAP3430_CORE_DPLL_ST_SHIFT			5
241 #define OMAP3430_TRANSITION_ST				(1 << 4)
242 #define OMAP3430_EVGENOFF_ST				(1 << 3)
243 #define OMAP3430_EVGENON_ST				(1 << 2)
244 #define OMAP3430_FS_USB_WKUP_ST				(1 << 1)
245 
246 /* PRM_IRQENABLE_MPU specific bits */
247 #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT		25
248 #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN			(1 << 25)
249 #define OMAP3430_VC_TIMEOUTERR_EN				(1 << 24)
250 #define OMAP3430_VC_RAERR_EN					(1 << 23)
251 #define OMAP3430_VC_SAERR_EN					(1 << 22)
252 #define OMAP3430_VP2_TRANXDONE_EN				(1 << 21)
253 #define OMAP3430_VP2_EQVALUE_EN					(1 << 20)
254 #define OMAP3430_VP2_NOSMPSACK_EN				(1 << 19)
255 #define OMAP3430_VP2_MAXVDD_EN					(1 << 18)
256 #define OMAP3430_VP2_MINVDD_EN					(1 << 17)
257 #define OMAP3430_VP2_OPPCHANGEDONE_EN				(1 << 16)
258 #define OMAP3430_VP1_TRANXDONE_EN				(1 << 15)
259 #define OMAP3430_VP1_EQVALUE_EN					(1 << 14)
260 #define OMAP3430_VP1_NOSMPSACK_EN				(1 << 13)
261 #define OMAP3430_VP1_MAXVDD_EN					(1 << 12)
262 #define OMAP3430_VP1_MINVDD_EN					(1 << 11)
263 #define OMAP3430_VP1_OPPCHANGEDONE_EN				(1 << 10)
264 #define OMAP3430_IO_EN						(1 << 9)
265 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN		(1 << 8)
266 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT	8
267 #define OMAP3430_MPU_DPLL_RECAL_EN				(1 << 7)
268 #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT			7
269 #define OMAP3430_PERIPH_DPLL_RECAL_EN				(1 << 6)
270 #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT			6
271 #define OMAP3430_CORE_DPLL_RECAL_EN				(1 << 5)
272 #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT			5
273 #define OMAP3430_TRANSITION_EN					(1 << 4)
274 #define OMAP3430_EVGENOFF_EN					(1 << 3)
275 #define OMAP3430_EVGENON_EN					(1 << 2)
276 #define OMAP3430_FS_USB_WKUP_EN					(1 << 1)
277 
278 /* RM_RSTST_MPU specific bits */
279 #define OMAP3430_EMULATION_MPU_RST			(1 << 11)
280 
281 /* PM_WKDEP_MPU specific bits */
282 #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT		5
283 #define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK		(1 << 5)
284 #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT		2
285 #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK		(1 << 2)
286 
287 /* PM_EVGENCTRL_MPU */
288 #define OMAP3430_OFFLOADMODE_SHIFT			3
289 #define OMAP3430_OFFLOADMODE_MASK			(0x3 << 3)
290 #define OMAP3430_ONLOADMODE_SHIFT			1
291 #define OMAP3430_ONLOADMODE_MASK			(0x3 << 1)
292 #define OMAP3430_ENABLE					(1 << 0)
293 
294 /* PM_EVGENONTIM_MPU */
295 #define OMAP3430_ONTIMEVAL_SHIFT			0
296 #define OMAP3430_ONTIMEVAL_MASK				(0xffffffff << 0)
297 
298 /* PM_EVGENOFFTIM_MPU */
299 #define OMAP3430_OFFTIMEVAL_SHIFT			0
300 #define OMAP3430_OFFTIMEVAL_MASK			(0xffffffff << 0)
301 
302 /* PM_PWSTCTRL_MPU specific bits */
303 #define OMAP3430_L2CACHEONSTATE_SHIFT			16
304 #define OMAP3430_L2CACHEONSTATE_MASK			(0x3 << 16)
305 #define OMAP3430_L2CACHERETSTATE			(1 << 8)
306 #define OMAP3430_LOGICL1CACHERETSTATE			(1 << 2)
307 
308 /* PM_PWSTST_MPU specific bits */
309 #define OMAP3430_L2CACHESTATEST_SHIFT			6
310 #define OMAP3430_L2CACHESTATEST_MASK			(0x3 << 6)
311 #define OMAP3430_LOGICL1CACHESTATEST			(1 << 2)
312 
313 /* PM_PREPWSTST_MPU specific bits */
314 #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT		6
315 #define OMAP3430_LASTL2CACHESTATEENTERED_MASK		(0x3 << 6)
316 #define OMAP3430_LASTLOGICL1CACHESTATEENTERED		(1 << 2)
317 
318 /* RM_RSTCTRL_CORE */
319 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON		(1 << 1)
320 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST			(1 << 0)
321 
322 /* RM_RSTST_CORE specific bits */
323 #define OMAP3430_MODEM_SECURITY_VIOL_RST		(1 << 10)
324 #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON	(1 << 9)
325 #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST		(1 << 8)
326 
327 /* PM_WKEN1_CORE specific bits */
328 
329 /* PM_MPUGRPSEL1_CORE specific bits */
330 #define OMAP3430_GRPSEL_FSHOSTUSB			(1 << 5)
331 
332 /* PM_IVA2GRPSEL1_CORE specific bits */
333 
334 /* PM_WKST1_CORE specific bits */
335 
336 /* PM_PWSTCTRL_CORE specific bits */
337 #define OMAP3430_MEM2ONSTATE_SHIFT			18
338 #define OMAP3430_MEM2ONSTATE_MASK			(0x3 << 18)
339 #define OMAP3430_MEM1ONSTATE_SHIFT			16
340 #define OMAP3430_MEM1ONSTATE_MASK			(0x3 << 16)
341 #define OMAP3430_MEM2RETSTATE				(1 << 9)
342 #define OMAP3430_MEM1RETSTATE				(1 << 8)
343 
344 /* PM_PWSTST_CORE specific bits */
345 #define OMAP3430_MEM2STATEST_SHIFT			6
346 #define OMAP3430_MEM2STATEST_MASK			(0x3 << 6)
347 #define OMAP3430_MEM1STATEST_SHIFT			4
348 #define OMAP3430_MEM1STATEST_MASK			(0x3 << 4)
349 
350 /* PM_PREPWSTST_CORE specific bits */
351 #define OMAP3430_LASTMEM2STATEENTERED_SHIFT		6
352 #define OMAP3430_LASTMEM2STATEENTERED_MASK		(0x3 << 6)
353 #define OMAP3430_LASTMEM1STATEENTERED_SHIFT		4
354 #define OMAP3430_LASTMEM1STATEENTERED_MASK		(0x3 << 4)
355 
356 /* RM_RSTST_GFX specific bits */
357 
358 /* PM_WKDEP_GFX specific bits */
359 #define OMAP3430_PM_WKDEP_GFX_EN_IVA2			(1 << 2)
360 
361 /* PM_PWSTCTRL_GFX specific bits */
362 
363 /* PM_PWSTST_GFX specific bits */
364 
365 /* PM_PREPWSTST_GFX specific bits */
366 
367 /* PM_WKEN_WKUP specific bits */
368 #define OMAP3430_EN_IO					(1 << 8)
369 
370 /* PM_MPUGRPSEL_WKUP specific bits */
371 
372 /* PM_IVA2GRPSEL_WKUP specific bits */
373 
374 /* PM_WKST_WKUP specific bits */
375 #define OMAP3430_ST_IO					(1 << 8)
376 
377 /* PRM_CLKSEL */
378 #define OMAP3430_SYS_CLKIN_SEL_SHIFT			0
379 #define OMAP3430_SYS_CLKIN_SEL_MASK			(0x7 << 0)
380 
381 /* PRM_CLKOUT_CTRL */
382 #define OMAP3430_CLKOUT_EN				(1 << 7)
383 #define OMAP3430_CLKOUT_EN_SHIFT			7
384 
385 /* RM_RSTST_DSS specific bits */
386 
387 /* PM_WKEN_DSS */
388 #define OMAP3430_PM_WKEN_DSS_EN_DSS			(1 << 0)
389 
390 /* PM_WKDEP_DSS specific bits */
391 #define OMAP3430_PM_WKDEP_DSS_EN_IVA2			(1 << 2)
392 
393 /* PM_PWSTCTRL_DSS specific bits */
394 
395 /* PM_PWSTST_DSS specific bits */
396 
397 /* PM_PREPWSTST_DSS specific bits */
398 
399 /* RM_RSTST_CAM specific bits */
400 
401 /* PM_WKDEP_CAM specific bits */
402 #define OMAP3430_PM_WKDEP_CAM_EN_IVA2			(1 << 2)
403 
404 /* PM_PWSTCTRL_CAM specific bits */
405 
406 /* PM_PWSTST_CAM specific bits */
407 
408 /* PM_PREPWSTST_CAM specific bits */
409 
410 /* PM_PWSTCTRL_USBHOST specific bits */
411 #define OMAP3430ES2_SAVEANDRESTORE_SHIFT		(1 << 4)
412 
413 /* RM_RSTST_PER specific bits */
414 
415 /* PM_WKEN_PER specific bits */
416 
417 /* PM_MPUGRPSEL_PER specific bits */
418 
419 /* PM_IVA2GRPSEL_PER specific bits */
420 
421 /* PM_WKST_PER specific bits */
422 
423 /* PM_WKDEP_PER specific bits */
424 #define OMAP3430_PM_WKDEP_PER_EN_IVA2			(1 << 2)
425 
426 /* PM_PWSTCTRL_PER specific bits */
427 
428 /* PM_PWSTST_PER specific bits */
429 
430 /* PM_PREPWSTST_PER specific bits */
431 
432 /* RM_RSTST_EMU specific bits */
433 
434 /* PM_PWSTST_EMU specific bits */
435 
436 /* PRM_VC_SMPS_SA */
437 #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT		16
438 #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK		(0x7f << 16)
439 #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT		0
440 #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK		(0x7f << 0)
441 
442 /* PRM_VC_SMPS_VOL_RA */
443 #define OMAP3430_VOLRA1_SHIFT				16
444 #define OMAP3430_VOLRA1_MASK				(0xff << 16)
445 #define OMAP3430_VOLRA0_SHIFT				0
446 #define OMAP3430_VOLRA0_MASK				(0xff << 0)
447 
448 /* PRM_VC_SMPS_CMD_RA */
449 #define OMAP3430_CMDRA1_SHIFT				16
450 #define OMAP3430_CMDRA1_MASK				(0xff << 16)
451 #define OMAP3430_CMDRA0_SHIFT				0
452 #define OMAP3430_CMDRA0_MASK				(0xff << 0)
453 
454 /* PRM_VC_CMD_VAL_0 specific bits */
455 
456 /* PRM_VC_CMD_VAL_1 specific bits */
457 
458 /* PRM_VC_CH_CONF */
459 #define OMAP3430_CMD1					(1 << 20)
460 #define OMAP3430_RACEN1					(1 << 19)
461 #define OMAP3430_RAC1					(1 << 18)
462 #define OMAP3430_RAV1					(1 << 17)
463 #define OMAP3430_PRM_VC_CH_CONF_SA1			(1 << 16)
464 #define OMAP3430_CMD0					(1 << 4)
465 #define OMAP3430_RACEN0					(1 << 3)
466 #define OMAP3430_RAC0					(1 << 2)
467 #define OMAP3430_RAV0					(1 << 1)
468 #define OMAP3430_PRM_VC_CH_CONF_SA0			(1 << 0)
469 
470 /* PRM_VC_I2C_CFG */
471 #define OMAP3430_HSMASTER				(1 << 5)
472 #define OMAP3430_SREN					(1 << 4)
473 #define OMAP3430_HSEN					(1 << 3)
474 #define OMAP3430_MCODE_SHIFT				0
475 #define OMAP3430_MCODE_MASK				(0x7 << 0)
476 
477 /* PRM_VC_BYPASS_VAL */
478 #define OMAP3430_VALID					(1 << 24)
479 #define OMAP3430_DATA_SHIFT				16
480 #define OMAP3430_DATA_MASK				(0xff << 16)
481 #define OMAP3430_REGADDR_SHIFT				8
482 #define OMAP3430_REGADDR_MASK				(0xff << 8)
483 #define OMAP3430_SLAVEADDR_SHIFT			0
484 #define OMAP3430_SLAVEADDR_MASK				(0x7f << 0)
485 
486 /* PRM_RSTCTRL */
487 #define OMAP3430_RST_DPLL3				(1 << 2)
488 #define OMAP3430_RST_GS					(1 << 1)
489 
490 /* PRM_RSTTIME */
491 #define OMAP3430_RSTTIME2_SHIFT				8
492 #define OMAP3430_RSTTIME2_MASK				(0x1f << 8)
493 #define OMAP3430_RSTTIME1_SHIFT				0
494 #define OMAP3430_RSTTIME1_MASK				(0xff << 0)
495 
496 /* PRM_RSTST */
497 #define OMAP3430_ICECRUSHER_RST				(1 << 10)
498 #define OMAP3430_ICEPICK_RST				(1 << 9)
499 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST		(1 << 8)
500 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST		(1 << 7)
501 #define OMAP3430_EXTERNAL_WARM_RST			(1 << 6)
502 #define OMAP3430_SECURE_WD_RST				(1 << 5)
503 #define OMAP3430_MPU_WD_RST				(1 << 4)
504 #define OMAP3430_SECURITY_VIOL_RST			(1 << 3)
505 #define OMAP3430_GLOBAL_SW_RST				(1 << 1)
506 #define OMAP3430_GLOBAL_COLD_RST			(1 << 0)
507 
508 /* PRM_VOLTCTRL */
509 #define OMAP3430_SEL_VMODE				(1 << 4)
510 #define OMAP3430_SEL_OFF				(1 << 3)
511 #define OMAP3430_AUTO_OFF				(1 << 2)
512 #define OMAP3430_AUTO_RET				(1 << 1)
513 #define OMAP3430_AUTO_SLEEP				(1 << 0)
514 
515 /* PRM_SRAM_PCHARGE */
516 #define OMAP3430_PCHARGE_TIME_SHIFT			0
517 #define OMAP3430_PCHARGE_TIME_MASK			(0xff << 0)
518 
519 /* PRM_CLKSRC_CTRL */
520 #define OMAP3430_SYSCLKDIV_SHIFT			6
521 #define OMAP3430_SYSCLKDIV_MASK				(0x3 << 6)
522 #define OMAP3430_AUTOEXTCLKMODE_SHIFT			3
523 #define OMAP3430_AUTOEXTCLKMODE_MASK			(0x3 << 3)
524 #define OMAP3430_SYSCLKSEL_SHIFT			0
525 #define OMAP3430_SYSCLKSEL_MASK				(0x3 << 0)
526 
527 /* PRM_VOLTSETUP1 */
528 #define OMAP3430_SETUP_TIME2_SHIFT			16
529 #define OMAP3430_SETUP_TIME2_MASK			(0xffff << 16)
530 #define OMAP3430_SETUP_TIME1_SHIFT			0
531 #define OMAP3430_SETUP_TIME1_MASK			(0xffff << 0)
532 
533 /* PRM_VOLTOFFSET */
534 #define OMAP3430_OFFSET_TIME_SHIFT			0
535 #define OMAP3430_OFFSET_TIME_MASK			(0xffff << 0)
536 
537 /* PRM_CLKSETUP */
538 #define OMAP3430_SETUP_TIME_SHIFT			0
539 #define OMAP3430_SETUP_TIME_MASK			(0xffff << 0)
540 
541 /* PRM_POLCTRL */
542 #define OMAP3430_OFFMODE_POL				(1 << 3)
543 #define OMAP3430_CLKOUT_POL				(1 << 2)
544 #define OMAP3430_CLKREQ_POL				(1 << 1)
545 #define OMAP3430_EXTVOL_POL				(1 << 0)
546 
547 /* PRM_VOLTSETUP2 */
548 #define OMAP3430_OFFMODESETUPTIME_SHIFT			0
549 #define OMAP3430_OFFMODESETUPTIME_MASK			(0xffff << 0)
550 
551 /* PRM_VP1_CONFIG specific bits */
552 
553 /* PRM_VP1_VSTEPMIN specific bits */
554 
555 /* PRM_VP1_VSTEPMAX specific bits */
556 
557 /* PRM_VP1_VLIMITTO specific bits */
558 
559 /* PRM_VP1_VOLTAGE specific bits */
560 
561 /* PRM_VP1_STATUS specific bits */
562 
563 /* PRM_VP2_CONFIG specific bits */
564 
565 /* PRM_VP2_VSTEPMIN specific bits */
566 
567 /* PRM_VP2_VSTEPMAX specific bits */
568 
569 /* PRM_VP2_VLIMITTO specific bits */
570 
571 /* PRM_VP2_VOLTAGE specific bits */
572 
573 /* PRM_VP2_STATUS specific bits */
574 
575 /* RM_RSTST_NEON specific bits */
576 
577 /* PM_WKDEP_NEON specific bits */
578 
579 /* PM_PWSTCTRL_NEON specific bits */
580 
581 /* PM_PWSTST_NEON specific bits */
582 
583 /* PM_PREPWSTST_NEON specific bits */
584 
585 #endif
586