1ddd04b98SVaibhav Hiremath /* 2ddd04b98SVaibhav Hiremath * AM33XX PRM_XXX register bits 3ddd04b98SVaibhav Hiremath * 4ddd04b98SVaibhav Hiremath * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ 5ddd04b98SVaibhav Hiremath * 6ddd04b98SVaibhav Hiremath * This program is free software; you can redistribute it and/or 7ddd04b98SVaibhav Hiremath * modify it under the terms of the GNU General Public License as 8ddd04b98SVaibhav Hiremath * published by the Free Software Foundation version 2. 9ddd04b98SVaibhav Hiremath * 10ddd04b98SVaibhav Hiremath * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11ddd04b98SVaibhav Hiremath * kind, whether express or implied; without even the implied warranty 12ddd04b98SVaibhav Hiremath * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13ddd04b98SVaibhav Hiremath * GNU General Public License for more details. 14ddd04b98SVaibhav Hiremath */ 15ddd04b98SVaibhav Hiremath 16ddd04b98SVaibhav Hiremath #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H 17ddd04b98SVaibhav Hiremath #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H 18ddd04b98SVaibhav Hiremath 19ddd04b98SVaibhav Hiremath #include "prm.h" 20ddd04b98SVaibhav Hiremath 21ddd04b98SVaibhav Hiremath /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ 22ddd04b98SVaibhav Hiremath #define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1 23ddd04b98SVaibhav Hiremath #define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1) 24ddd04b98SVaibhav Hiremath 25ddd04b98SVaibhav Hiremath /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ 26ddd04b98SVaibhav Hiremath #define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2 27ddd04b98SVaibhav Hiremath #define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) 28ddd04b98SVaibhav Hiremath 29ddd04b98SVaibhav Hiremath /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ 30ddd04b98SVaibhav Hiremath #define AM33XX_AIPOFF_SHIFT 8 31ddd04b98SVaibhav Hiremath #define AM33XX_AIPOFF_MASK (1 << 8) 32ddd04b98SVaibhav Hiremath 33ddd04b98SVaibhav Hiremath /* Used by PM_WKUP_PWRSTST */ 34ddd04b98SVaibhav Hiremath #define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17 35ddd04b98SVaibhav Hiremath #define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17) 36ddd04b98SVaibhav Hiremath 37ddd04b98SVaibhav Hiremath /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ 38ddd04b98SVaibhav Hiremath #define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0 39ddd04b98SVaibhav Hiremath #define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0) 40ddd04b98SVaibhav Hiremath 41ddd04b98SVaibhav Hiremath /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ 42ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12 43ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12) 44ddd04b98SVaibhav Hiremath 45ddd04b98SVaibhav Hiremath /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ 46ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12 47ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12) 48ddd04b98SVaibhav Hiremath 49ddd04b98SVaibhav Hiremath /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ 50ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14 51ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14) 52ddd04b98SVaibhav Hiremath 53ddd04b98SVaibhav Hiremath /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ 54ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14 55ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14) 56ddd04b98SVaibhav Hiremath 57ddd04b98SVaibhav Hiremath /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ 58ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15 59ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15) 60ddd04b98SVaibhav Hiremath 61ddd04b98SVaibhav Hiremath /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ 62ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13 63ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13) 64ddd04b98SVaibhav Hiremath 65ddd04b98SVaibhav Hiremath /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ 66ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11 67ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11) 68ddd04b98SVaibhav Hiremath 69ddd04b98SVaibhav Hiremath /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ 70ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11 71ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11) 72ddd04b98SVaibhav Hiremath 73ddd04b98SVaibhav Hiremath /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ 74ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13 75ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13) 76ddd04b98SVaibhav Hiremath 77ddd04b98SVaibhav Hiremath /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ 78ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15 79ddd04b98SVaibhav Hiremath #define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15) 80ddd04b98SVaibhav Hiremath 81ddd04b98SVaibhav Hiremath /* Used by RM_WKUP_RSTST */ 82ddd04b98SVaibhav Hiremath #define AM33XX_EMULATION_M3_RST_SHIFT 6 83ddd04b98SVaibhav Hiremath #define AM33XX_EMULATION_M3_RST_MASK (1 << 6) 84ddd04b98SVaibhav Hiremath 85ddd04b98SVaibhav Hiremath /* Used by RM_MPU_RSTST */ 86ddd04b98SVaibhav Hiremath #define AM33XX_EMULATION_MPU_RST_SHIFT 5 87ddd04b98SVaibhav Hiremath #define AM33XX_EMULATION_MPU_RST_MASK (1 << 5) 88ddd04b98SVaibhav Hiremath 89ddd04b98SVaibhav Hiremath /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ 90ddd04b98SVaibhav Hiremath #define AM33XX_ENFUNC1_EXPORT_SHIFT 3 91ddd04b98SVaibhav Hiremath #define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3) 92ddd04b98SVaibhav Hiremath 93ddd04b98SVaibhav Hiremath /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ 94ddd04b98SVaibhav Hiremath #define AM33XX_ENFUNC3_EXPORT_SHIFT 5 95ddd04b98SVaibhav Hiremath #define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5) 96ddd04b98SVaibhav Hiremath 97ddd04b98SVaibhav Hiremath /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ 98ddd04b98SVaibhav Hiremath #define AM33XX_ENFUNC4_SHIFT 6 99ddd04b98SVaibhav Hiremath #define AM33XX_ENFUNC4_MASK (1 << 6) 100ddd04b98SVaibhav Hiremath 101ddd04b98SVaibhav Hiremath /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ 102ddd04b98SVaibhav Hiremath #define AM33XX_ENFUNC5_SHIFT 7 103ddd04b98SVaibhav Hiremath #define AM33XX_ENFUNC5_MASK (1 << 7) 104ddd04b98SVaibhav Hiremath 105ddd04b98SVaibhav Hiremath /* Used by PRM_RSTST */ 106ddd04b98SVaibhav Hiremath #define AM33XX_EXTERNAL_WARM_RST_SHIFT 5 107ddd04b98SVaibhav Hiremath #define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5) 108ddd04b98SVaibhav Hiremath 109ddd04b98SVaibhav Hiremath /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ 110ddd04b98SVaibhav Hiremath #define AM33XX_FORCEWKUP_EN_SHIFT 10 111ddd04b98SVaibhav Hiremath #define AM33XX_FORCEWKUP_EN_MASK (1 << 10) 112ddd04b98SVaibhav Hiremath 113ddd04b98SVaibhav Hiremath /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ 114ddd04b98SVaibhav Hiremath #define AM33XX_FORCEWKUP_ST_SHIFT 10 115ddd04b98SVaibhav Hiremath #define AM33XX_FORCEWKUP_ST_MASK (1 << 10) 116ddd04b98SVaibhav Hiremath 117ddd04b98SVaibhav Hiremath /* Used by PM_GFX_PWRSTCTRL */ 118ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_ONSTATE_SHIFT 17 119ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) 120ddd04b98SVaibhav Hiremath 121ddd04b98SVaibhav Hiremath /* Used by PM_GFX_PWRSTCTRL */ 122ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_RETSTATE_SHIFT 6 123ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) 124ddd04b98SVaibhav Hiremath 125ddd04b98SVaibhav Hiremath /* Used by PM_GFX_PWRSTST */ 126ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_STATEST_SHIFT 4 127ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) 128ddd04b98SVaibhav Hiremath 129ddd04b98SVaibhav Hiremath /* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */ 130ddd04b98SVaibhav Hiremath #define AM33XX_GFX_RST_SHIFT 0 131ddd04b98SVaibhav Hiremath #define AM33XX_GFX_RST_MASK (1 << 0) 132ddd04b98SVaibhav Hiremath 133ddd04b98SVaibhav Hiremath /* Used by PRM_RSTST */ 134ddd04b98SVaibhav Hiremath #define AM33XX_GLOBAL_COLD_RST_SHIFT 0 135ddd04b98SVaibhav Hiremath #define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0) 136ddd04b98SVaibhav Hiremath 137ddd04b98SVaibhav Hiremath /* Used by PRM_RSTST */ 138ddd04b98SVaibhav Hiremath #define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1 139ddd04b98SVaibhav Hiremath #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) 140ddd04b98SVaibhav Hiremath 141ddd04b98SVaibhav Hiremath /* Used by RM_WKUP_RSTST */ 142ddd04b98SVaibhav Hiremath #define AM33XX_ICECRUSHER_M3_RST_SHIFT 7 143ddd04b98SVaibhav Hiremath #define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7) 144ddd04b98SVaibhav Hiremath 145ddd04b98SVaibhav Hiremath /* Used by RM_MPU_RSTST */ 146ddd04b98SVaibhav Hiremath #define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6 147ddd04b98SVaibhav Hiremath #define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6) 148ddd04b98SVaibhav Hiremath 149ddd04b98SVaibhav Hiremath /* Used by PRM_RSTST */ 150ddd04b98SVaibhav Hiremath #define AM33XX_ICEPICK_RST_SHIFT 9 151ddd04b98SVaibhav Hiremath #define AM33XX_ICEPICK_RST_MASK (1 << 9) 152ddd04b98SVaibhav Hiremath 153ddd04b98SVaibhav Hiremath /* Used by RM_PER_RSTCTRL */ 154ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_LRST_SHIFT 1 155ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_LRST_MASK (1 << 1) 156ddd04b98SVaibhav Hiremath 157ddd04b98SVaibhav Hiremath /* Used by PM_PER_PWRSTCTRL */ 158ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5 159ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) 160ddd04b98SVaibhav Hiremath 161ddd04b98SVaibhav Hiremath /* Used by PM_PER_PWRSTCTRL */ 162ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7 163ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) 164ddd04b98SVaibhav Hiremath 165ddd04b98SVaibhav Hiremath /* Used by PM_PER_PWRSTST */ 166ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_STATEST_SHIFT 23 167ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) 168ddd04b98SVaibhav Hiremath 169ddd04b98SVaibhav Hiremath /* 170ddd04b98SVaibhav Hiremath * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, 171ddd04b98SVaibhav Hiremath * PM_WKUP_PWRSTST, PM_RTC_PWRSTST 172ddd04b98SVaibhav Hiremath */ 173ddd04b98SVaibhav Hiremath #define AM33XX_INTRANSITION_SHIFT 20 174ddd04b98SVaibhav Hiremath #define AM33XX_INTRANSITION_MASK (1 << 20) 175ddd04b98SVaibhav Hiremath 176ddd04b98SVaibhav Hiremath /* Used by PM_CEFUSE_PWRSTST */ 177ddd04b98SVaibhav Hiremath #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 178ddd04b98SVaibhav Hiremath #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) 179ddd04b98SVaibhav Hiremath 180ddd04b98SVaibhav Hiremath /* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */ 181ddd04b98SVaibhav Hiremath #define AM33XX_LOGICRETSTATE_SHIFT 2 182ddd04b98SVaibhav Hiremath #define AM33XX_LOGICRETSTATE_MASK (1 << 2) 183ddd04b98SVaibhav Hiremath 184ddd04b98SVaibhav Hiremath /* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */ 185ddd04b98SVaibhav Hiremath #define AM33XX_LOGICRETSTATE_3_3_SHIFT 3 186ddd04b98SVaibhav Hiremath #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) 187ddd04b98SVaibhav Hiremath 188ddd04b98SVaibhav Hiremath /* 189ddd04b98SVaibhav Hiremath * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, 190ddd04b98SVaibhav Hiremath * PM_WKUP_PWRSTST, PM_RTC_PWRSTST 191ddd04b98SVaibhav Hiremath */ 192ddd04b98SVaibhav Hiremath #define AM33XX_LOGICSTATEST_SHIFT 2 193ddd04b98SVaibhav Hiremath #define AM33XX_LOGICSTATEST_MASK (1 << 2) 194ddd04b98SVaibhav Hiremath 195ddd04b98SVaibhav Hiremath /* 196ddd04b98SVaibhav Hiremath * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, 197ddd04b98SVaibhav Hiremath * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL 198ddd04b98SVaibhav Hiremath */ 199ddd04b98SVaibhav Hiremath #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 200ddd04b98SVaibhav Hiremath #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) 201ddd04b98SVaibhav Hiremath 202ddd04b98SVaibhav Hiremath /* Used by PM_MPU_PWRSTCTRL */ 203ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_ONSTATE_SHIFT 18 204ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) 205ddd04b98SVaibhav Hiremath 206ddd04b98SVaibhav Hiremath /* Used by PM_MPU_PWRSTCTRL */ 207ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_RETSTATE_SHIFT 22 208ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) 209ddd04b98SVaibhav Hiremath 210ddd04b98SVaibhav Hiremath /* Used by PM_MPU_PWRSTST */ 211ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_STATEST_SHIFT 6 212ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) 213ddd04b98SVaibhav Hiremath 214ddd04b98SVaibhav Hiremath /* Used by PM_MPU_PWRSTCTRL */ 215ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_ONSTATE_SHIFT 20 216ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) 217ddd04b98SVaibhav Hiremath 218ddd04b98SVaibhav Hiremath /* Used by PM_MPU_PWRSTCTRL */ 219ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_RETSTATE_SHIFT 23 220ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) 221ddd04b98SVaibhav Hiremath 222ddd04b98SVaibhav Hiremath /* Used by PM_MPU_PWRSTST */ 223ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_STATEST_SHIFT 8 224ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) 225ddd04b98SVaibhav Hiremath 226ddd04b98SVaibhav Hiremath /* Used by PM_MPU_PWRSTCTRL */ 227ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_ONSTATE_SHIFT 16 228ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) 229ddd04b98SVaibhav Hiremath 230ddd04b98SVaibhav Hiremath /* Used by PM_MPU_PWRSTCTRL */ 231ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_RETSTATE_SHIFT 24 232ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) 233ddd04b98SVaibhav Hiremath 234ddd04b98SVaibhav Hiremath /* Used by PM_MPU_PWRSTST */ 235ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_STATEST_SHIFT 4 236ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) 237ddd04b98SVaibhav Hiremath 238ddd04b98SVaibhav Hiremath /* Used by PRM_RSTST */ 239ddd04b98SVaibhav Hiremath #define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2 240ddd04b98SVaibhav Hiremath #define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) 241ddd04b98SVaibhav Hiremath 242ddd04b98SVaibhav Hiremath /* Used by PRM_SRAM_COUNT */ 243ddd04b98SVaibhav Hiremath #define AM33XX_PCHARGECNT_VALUE_SHIFT 0 244ddd04b98SVaibhav Hiremath #define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0) 245ddd04b98SVaibhav Hiremath 246ddd04b98SVaibhav Hiremath /* Used by RM_PER_RSTCTRL */ 247ddd04b98SVaibhav Hiremath #define AM33XX_PCI_LRST_SHIFT 0 248ddd04b98SVaibhav Hiremath #define AM33XX_PCI_LRST_MASK (1 << 0) 249ddd04b98SVaibhav Hiremath 250ddd04b98SVaibhav Hiremath /* Renamed from PCI_LRST Used by RM_PER_RSTST */ 251ddd04b98SVaibhav Hiremath #define AM33XX_PCI_LRST_5_5_SHIFT 5 252ddd04b98SVaibhav Hiremath #define AM33XX_PCI_LRST_5_5_MASK (1 << 5) 253ddd04b98SVaibhav Hiremath 254ddd04b98SVaibhav Hiremath /* Used by PM_PER_PWRSTCTRL */ 255ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_ONSTATE_SHIFT 25 256ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) 257ddd04b98SVaibhav Hiremath 258ddd04b98SVaibhav Hiremath /* Used by PM_PER_PWRSTCTRL */ 259ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_RETSTATE_SHIFT 29 260ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) 261ddd04b98SVaibhav Hiremath 262ddd04b98SVaibhav Hiremath /* Used by PM_PER_PWRSTST */ 263ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_STATEST_SHIFT 17 264ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) 265ddd04b98SVaibhav Hiremath 266ddd04b98SVaibhav Hiremath /* 267ddd04b98SVaibhav Hiremath * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, 268ddd04b98SVaibhav Hiremath * PM_MPU_PWRSTCTRL 269ddd04b98SVaibhav Hiremath */ 270ddd04b98SVaibhav Hiremath #define AM33XX_POWERSTATE_SHIFT 0 271ddd04b98SVaibhav Hiremath #define AM33XX_POWERSTATE_MASK (0x3 << 0) 272ddd04b98SVaibhav Hiremath 273ddd04b98SVaibhav Hiremath /* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */ 274ddd04b98SVaibhav Hiremath #define AM33XX_POWERSTATEST_SHIFT 0 275ddd04b98SVaibhav Hiremath #define AM33XX_POWERSTATEST_MASK (0x3 << 0) 276ddd04b98SVaibhav Hiremath 277ddd04b98SVaibhav Hiremath /* Used by PM_PER_PWRSTCTRL */ 278ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_ONSTATE_SHIFT 30 279ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) 280ddd04b98SVaibhav Hiremath 281ddd04b98SVaibhav Hiremath /* Used by PM_PER_PWRSTCTRL */ 282ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_RETSTATE_SHIFT 27 283ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) 284ddd04b98SVaibhav Hiremath 285ddd04b98SVaibhav Hiremath /* Used by PM_PER_PWRSTST */ 286ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_STATEST_SHIFT 21 287ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) 288ddd04b98SVaibhav Hiremath 289ddd04b98SVaibhav Hiremath /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ 290ddd04b98SVaibhav Hiremath #define AM33XX_RETMODE_ENABLE_SHIFT 0 291ddd04b98SVaibhav Hiremath #define AM33XX_RETMODE_ENABLE_MASK (1 << 0) 292ddd04b98SVaibhav Hiremath 293ddd04b98SVaibhav Hiremath /* Used by REVISION_PRM */ 294ddd04b98SVaibhav Hiremath #define AM33XX_REV_SHIFT 0 295ddd04b98SVaibhav Hiremath #define AM33XX_REV_MASK (0xff << 0) 296ddd04b98SVaibhav Hiremath 297ddd04b98SVaibhav Hiremath /* Used by PRM_RSTTIME */ 298ddd04b98SVaibhav Hiremath #define AM33XX_RSTTIME1_SHIFT 0 299ddd04b98SVaibhav Hiremath #define AM33XX_RSTTIME1_MASK (0xff << 0) 300ddd04b98SVaibhav Hiremath 301ddd04b98SVaibhav Hiremath /* Used by PRM_RSTTIME */ 302ddd04b98SVaibhav Hiremath #define AM33XX_RSTTIME2_SHIFT 8 303ddd04b98SVaibhav Hiremath #define AM33XX_RSTTIME2_MASK (0x1f << 8) 304ddd04b98SVaibhav Hiremath 305ddd04b98SVaibhav Hiremath /* Used by PRM_RSTCTRL */ 306ddd04b98SVaibhav Hiremath #define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1 307ddd04b98SVaibhav Hiremath #define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) 308ddd04b98SVaibhav Hiremath 309ddd04b98SVaibhav Hiremath /* Used by PRM_RSTCTRL */ 310ddd04b98SVaibhav Hiremath #define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0 311ddd04b98SVaibhav Hiremath #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) 312ddd04b98SVaibhav Hiremath 313ddd04b98SVaibhav Hiremath /* Used by PRM_SRAM_COUNT */ 314ddd04b98SVaibhav Hiremath #define AM33XX_SLPCNT_VALUE_SHIFT 16 315ddd04b98SVaibhav Hiremath #define AM33XX_SLPCNT_VALUE_MASK (0xff << 16) 316ddd04b98SVaibhav Hiremath 317ddd04b98SVaibhav Hiremath /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ 318ddd04b98SVaibhav Hiremath #define AM33XX_SRAMLDO_STATUS_SHIFT 8 319ddd04b98SVaibhav Hiremath #define AM33XX_SRAMLDO_STATUS_MASK (1 << 8) 320ddd04b98SVaibhav Hiremath 321ddd04b98SVaibhav Hiremath /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ 322ddd04b98SVaibhav Hiremath #define AM33XX_SRAM_IN_TRANSITION_SHIFT 9 323ddd04b98SVaibhav Hiremath #define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9) 324ddd04b98SVaibhav Hiremath 325ddd04b98SVaibhav Hiremath /* Used by PRM_SRAM_COUNT */ 326ddd04b98SVaibhav Hiremath #define AM33XX_STARTUP_COUNT_SHIFT 24 327ddd04b98SVaibhav Hiremath #define AM33XX_STARTUP_COUNT_MASK (0xff << 24) 328ddd04b98SVaibhav Hiremath 329ddd04b98SVaibhav Hiremath /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ 330ddd04b98SVaibhav Hiremath #define AM33XX_TRANSITION_EN_SHIFT 8 331ddd04b98SVaibhav Hiremath #define AM33XX_TRANSITION_EN_MASK (1 << 8) 332ddd04b98SVaibhav Hiremath 333ddd04b98SVaibhav Hiremath /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ 334ddd04b98SVaibhav Hiremath #define AM33XX_TRANSITION_ST_SHIFT 8 335ddd04b98SVaibhav Hiremath #define AM33XX_TRANSITION_ST_MASK (1 << 8) 336ddd04b98SVaibhav Hiremath 337ddd04b98SVaibhav Hiremath /* Used by PRM_SRAM_COUNT */ 338ddd04b98SVaibhav Hiremath #define AM33XX_VSETUPCNT_VALUE_SHIFT 8 339ddd04b98SVaibhav Hiremath #define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8) 340ddd04b98SVaibhav Hiremath 341ddd04b98SVaibhav Hiremath /* Used by PRM_RSTST */ 342ddd04b98SVaibhav Hiremath #define AM33XX_WDT0_RST_SHIFT 3 343ddd04b98SVaibhav Hiremath #define AM33XX_WDT0_RST_MASK (1 << 3) 344ddd04b98SVaibhav Hiremath 345ddd04b98SVaibhav Hiremath /* Used by PRM_RSTST */ 346ddd04b98SVaibhav Hiremath #define AM33XX_WDT1_RST_SHIFT 4 347ddd04b98SVaibhav Hiremath #define AM33XX_WDT1_RST_MASK (1 << 4) 348ddd04b98SVaibhav Hiremath 349ddd04b98SVaibhav Hiremath /* Used by RM_WKUP_RSTCTRL */ 350ddd04b98SVaibhav Hiremath #define AM33XX_WKUP_M3_LRST_SHIFT 3 351ddd04b98SVaibhav Hiremath #define AM33XX_WKUP_M3_LRST_MASK (1 << 3) 352ddd04b98SVaibhav Hiremath 353ddd04b98SVaibhav Hiremath /* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */ 354ddd04b98SVaibhav Hiremath #define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5 355ddd04b98SVaibhav Hiremath #define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5) 356ddd04b98SVaibhav Hiremath 357ddd04b98SVaibhav Hiremath #endif 358