1*52e6676eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2ddd04b98SVaibhav Hiremath /* 3ddd04b98SVaibhav Hiremath * AM33XX PRM_XXX register bits 4ddd04b98SVaibhav Hiremath * 53aa36fddSAlexander A. Klimov * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ 6ddd04b98SVaibhav Hiremath */ 7ddd04b98SVaibhav Hiremath 8ddd04b98SVaibhav Hiremath #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H 9ddd04b98SVaibhav Hiremath #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H 10ddd04b98SVaibhav Hiremath 11ddd04b98SVaibhav Hiremath #include "prm.h" 12ddd04b98SVaibhav Hiremath 13ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) 14ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) 15ddd04b98SVaibhav Hiremath #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) 16ddd04b98SVaibhav Hiremath #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) 177323f219STony Lindgren #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) 18ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) 19ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) 20ddd04b98SVaibhav Hiremath #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) 21ddd04b98SVaibhav Hiremath #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 22ddd04b98SVaibhav Hiremath #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) 23ddd04b98SVaibhav Hiremath #define AM33XX_LOGICRETSTATE_MASK (1 << 2) 24ddd04b98SVaibhav Hiremath #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) 25ddd04b98SVaibhav Hiremath #define AM33XX_LOGICSTATEST_SHIFT 2 26ddd04b98SVaibhav Hiremath #define AM33XX_LOGICSTATEST_MASK (1 << 2) 27ddd04b98SVaibhav Hiremath #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 28ddd04b98SVaibhav Hiremath #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) 29ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) 30ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) 31ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) 32ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) 33ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) 34ddd04b98SVaibhav Hiremath #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) 35ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) 36ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) 37ddd04b98SVaibhav Hiremath #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) 38ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) 39ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) 40ddd04b98SVaibhav Hiremath #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) 41ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) 42ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) 43ddd04b98SVaibhav Hiremath #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) 44ddd04b98SVaibhav Hiremath #endif 45